On 9/1/19 10:10 AM, Bill Slade wrote:
Hello,
This is a topic that interest me greatly as well. Some of the work we have done uses
a digital frequency tracking loop to generate frequency errors directly from sampled
data using a sampling system and ethernet system of our own design. We opted
Correction:
On Sun, Sep 1, 2019 at 8:24 PM Jan-Derk Bakker wrote:
> Especially with the addition of the LPF the simulator is showing quite
> literally unbelievably good performance (example: running the ZCD over
> 1/40th of the sine for an input signal of 0dBm/-10dBFS gives single digit
>
Dear Jim,
Thank you for your feedback.
The very short version: this design works 'on paper', but there are a few
undocumented unknowns that I can only resolve by actually building and
testing it.
>
> 1. The input bandwidth of the digitizer chip is 750 MHz (very
> impressive), but what happens
Hello,
This is a topic that interest me greatly as well. Some of the work we have
done uses a digital frequency tracking loop to generate frequency errors
directly from sampled data using a sampling system and ethernet system of our
own design. We opted for using a look-up table-based DDS in
Jan-Derk-
Excellent and exciting work! Thanks for sharing with the newsgroup...
I have a couple of questions:
1. The input bandwidth of the digitizer chip is 750 MHz (very impressive), but
what happens to input noise that is aliased? When sampling at 10MHz (plus
offset) everything above
