I have committed this patch to fix vector negate instruction in Blackfin
simulator. Previously saturation was not handled. And the flags were not
set correctly. I also added some tests.
Jie
* bfin/bfin-dis.c (decode_dsp32alu_0): Take care of saturation
and all affected ASTAT flags for vector negate instruction.
testsuite/
* sim/bfin/vec-neg.S: New test.
* sim/bfin/vec-neg-2.S: New test.
* sim/bfin/vec-neg-3.S: New test.
* sim/bfin/test.h: New file.
* sim/bfin/testutils.inc: Turn pass and fail into functions.
* sim/bfin/allinsn.exp: Use loop instead of
listing each test.
Index: testsuite/sim/bfin/vec-neg-2.S
===================================================================
--- testsuite/sim/bfin/vec-neg-2.S (revision 0)
+++ testsuite/sim/bfin/vec-neg-2.S (revision 0)
@@ -0,0 +1,42 @@
+# Blackfin testcase for vector negate instruction
+# mach: bfin
+
+#include "test.h"
+
+ .include "testutils.inc"
+
+ start
+
+ .global _test
+_test:
+ R6 = ASTAT;
+ R0.H = 0x0;
+ R0.L = 0x8000;
+ R1 = -R0 (V);
+ R7 = ASTAT;
+ R2.H = 0x0;
+ R2.L = 0x7fff;
+ CC = R1 == R2;
+ IF !CC JUMP 1f;
+ /* CLEARED: AN AC0 AC0_COPY */
+ R3.H = HI(_AN|_AC0|_AC0_COPY);
+ R3.L = LO(_AN|_AC0|_AC0_COPY);
+ R4 = R7 & R3;
+ CC = R4 == 0;
+ IF !CC JUMP 1f;
+ /* SET: AZ V V_COPY VS AC1 */
+ R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC1);
+ R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC1);
+ R4 = R7 & R3;
+ CC = R3 == R4;
+ IF !CC JUMP 1f;
+ /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */
+ R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S);
+ R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S);
+ R4 = R6 & R3;
+ R5 = R7 & R3;
+ CC = R4 == R5;
+ IF !CC JUMP 1f;
+ pass
+1:
+ fail
Index: testsuite/sim/bfin/vec-neg-3.S
===================================================================
--- testsuite/sim/bfin/vec-neg-3.S (revision 0)
+++ testsuite/sim/bfin/vec-neg-3.S (revision 0)
@@ -0,0 +1,42 @@
+# Blackfin testcase for vector negate instruction
+# mach: bfin
+
+#include "test.h"
+
+ .include "testutils.inc"
+
+ start
+
+ .global _test
+_test:
+ R6 = ASTAT;
+ R0.H = 0x8000;
+ R0.L = 0x0;
+ R1 = -R0 (V);
+ R7 = ASTAT;
+ R2.H = 0x7fff;
+ R2.L = 0x0;
+ CC = R1 == R2;
+ IF !CC JUMP 1f;
+ /* CLEARED: AN AC0 AC0_COPY */
+ R3.H = HI(_AN|_AC1);
+ R3.L = LO(_AN|_AC1);
+ R4 = R7 & R3;
+ CC = R4 == 0;
+ IF !CC JUMP 1f;
+ /* SET: AZ V V_COPY VS AC1 */
+ R3.H = HI(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY);
+ R3.L = LO(_AZ|_V|_V_COPY|_VS|_AC0|_AC0_COPY);
+ R4 = R7 & R3;
+ CC = R3 == R4;
+ IF !CC JUMP 1f;
+ /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S */
+ R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S);
+ R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S);
+ R4 = R6 & R3;
+ R5 = R7 & R3;
+ CC = R4 == R5;
+ IF !CC JUMP 1f;
+ pass
+1:
+ fail
Index: testsuite/sim/bfin/vec-neg.S
===================================================================
--- testsuite/sim/bfin/vec-neg.S (revision 0)
+++ testsuite/sim/bfin/vec-neg.S (revision 0)
@@ -0,0 +1,42 @@
+# Blackfin testcase for vector negate instruction
+# mach: bfin
+
+#include "test.h"
+
+ .include "testutils.inc"
+
+ start
+
+ .global _test
+_test:
+ R6 = ASTAT;
+ R0.H = 0x1234;
+ R0.L = 0xcdef;
+ R1 = -R0 (V);
+ R7 = ASTAT;
+ R2.H = 0xedcc;
+ R2.L = 0x3211;
+ CC = R1 == R2;
+ IF !CC JUMP 1f;
+ /* CLEARED: AZ V V_COPY AC0 AC0_COPY AC1 */
+ R3.H = HI(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
+ R3.L = LO(_AZ|_V|_V_COPY|_AC0|_AC0_COPY|_AC1);
+ R4 = R7 & R3;
+ CC = R4 == 0;
+ IF !CC JUMP 1f;
+ /* SET: AN */
+ R3.H = HI(_AN);
+ R3.L = LO(_AN);
+ R4 = R7 & R3;
+ CC = R3 == R4;
+ IF !CC JUMP 1f;
+ /* UNAFFECTED: CC AQ RND_MOD AV0 AV0S AV1 AV1S VS */
+ R3.H = HI(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS);
+ R3.L = LO(_CC|_AQ|_RND_MOD|_AV0|_AV0S|_AV1|_AV1S|_VS);
+ R4 = R6 & R3;
+ R5 = R7 & R3;
+ CC = R4 == R5;
+ IF !CC JUMP 1f;
+ pass
+1:
+ fail
Index: testsuite/sim/bfin/test.h
===================================================================
--- testsuite/sim/bfin/test.h (revision 0)
+++ testsuite/sim/bfin/test.h (revision 0)
@@ -0,0 +1,20 @@
+/* AZ AN AC0_COPY V_COPY CC AQ RND_MOD AC0 AC1 AV0 AV0S AV1 AV1S V VS */
+
+#define _AZ (1 << 0)
+#define _AN (1 << 1)
+#define _AC0_COPY (1 << 2)
+#define _V_COPY (1 << 3)
+#define _CC (1 << 5)
+#define _AQ (1 << 6)
+#define _RND_MOD (1 << 8)
+#define _AC0 (1 << 12)
+#define _AC1 (1 << 13)
+#define _AV0 (1 << 16)
+#define _AV0S (1 << 17)
+#define _AV1 (1 << 18)
+#define _AV1S (1 << 19)
+#define _V (1 << 24)
+#define _VS (1 << 25)
+
+#define HI(x) (((x) >> 16) & 0xffff)
+#define LO(x) ((x) & 0xffff)
Index: testsuite/sim/bfin/testutils.inc
===================================================================
--- testsuite/sim/bfin/testutils.inc (revision 3656)
+++ testsuite/sim/bfin/testutils.inc (working copy)
@@ -29,6 +29,14 @@ __start:
.endm
.macro pass
+ CALL __pass;
+ .endm
+
+ .macro fail
+ CALL __fail;
+ .endm
+
+__pass:
P0.H = _params;
P0.L = _params;
R0 = 1 (X);
@@ -42,9 +50,8 @@ __start:
P0 = 5 (X);
EXCPT 0;
exit 0
- .endm
- .macro fail
+__fail:
P0.H = _params;
P0.L = _params;
R0 = 1 (X);
@@ -58,4 +65,3 @@ __start:
P0 = 5 (X);
EXCPT 0;
exit 1
- .endm
Index: testsuite/sim/bfin/allinsn.exp
===================================================================
--- testsuite/sim/bfin/allinsn.exp (revision 3656)
+++ testsuite/sim/bfin/allinsn.exp (working copy)
@@ -1,7 +1,15 @@
# Analog Devices Blackfin simulator testsuite
-set all "bfin"
-
if [istarget bfin-*-elf] {
- run_sim_test compare.s $all
+ # all machines
+ set all_machs "bfin"
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.\[sS\]]] {
+ # If we're only testing specific files and this isn't one of them,
+ # skip it.
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+ run_sim_test $src $all_machs
+ }
}
Index: bfin/bfin-dis.c
===================================================================
--- bfin/bfin-dis.c (revision 3666)
+++ bfin/bfin-dis.c (working copy)
@@ -2500,9 +2500,37 @@ decode_dsp32alu_0 (bu16 iw0, bu16 iw1, b
/* Vector NEG. */
bu32 hi = (-(bs16)(DREG (src0) >> 16)) << 16;
bu32 lo = (-(bs16)(DREG (src0) & 0xFFFF)) & 0xFFFF;
+
+ saved_state.v = 0;
+ saved_state.v_copy = 0;
+ saved_state.ac0 = 0;
+ saved_state.ac0_copy = 0;
+ saved_state.ac1 = 0;
+
+ if (hi == 0x80000000)
+ {
+ hi = 0x7fff0000;
+ saved_state.v = 1;
+ saved_state.v_copy = 1;
+ saved_state.vs = 1;
+ }
+ else if (hi == 0)
+ saved_state.ac1 = 1;
+
+ if (lo == 0x8000)
+ {
+ lo = 0x7fff;
+ saved_state.v = 1;
+ saved_state.v_copy = 1;
+ saved_state.vs = 1;
+ }
+ else if (lo == 0)
+ {
+ saved_state.ac0 = 1;
+ saved_state.ac0_copy = 1;
+ }
DREG (dst0) = hi | lo;
setflags_nz_2x16 (DREG (dst0));
- saved_state.v = 0;
}
else if (aop == 3 && HL == 0 && aopcde == 14)
unhandled_instruction ("A1 = - A1 , A0 = - A0");
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