On Thu, Sep 21, 2017 at 4:07 AM, ex vito wrote:
> On 2017-09-20, at 22:33, Bryan Murdock wrote:
>
> Welcome to the club! :)
Thanks!
>> Now I have a crazy idea. I'd like that Python code that my Verilog
>> calls out to to use twisted. OK, actually I've already done that, my
>> Verilog calls ou
I submitted one pull request, based on Amber's previous patch:
https://github.com/LeastAuthority/txkube/pull/150
that brings the test failures down to only 1 failed test with Twisted
17.5.0 on Python 2.7.
For the last failing test, it looks like
It looks like changes which went into Twisted 17.1
On 2017-09-21, at 2:13, Moshe Zadka wrote:
> OK I opened a ticket with a plan, after discussing with Mark Williams.
>
> 1. Make a custom class that implements the Sequence ABC and pretends to be
> sized the old size.
> 2. Internally all access will be moved to attributes
> 3. All sequence metho
On 2017-09-20, at 22:33, Bryan Murdock wrote:
> I've been writing Verilog simulations for years, and tinkering with
> Python for years. In the last couple years I have been calling out to
> Python from Verilog simulations, which has been awesome. Just this
> week I tried twisted out for the fir
