On Fri, Oct 03, 2008 at 03:09:06PM -0500, Jon Loeliger wrote:
> Petri Lehtinen wrote:
>> On Thu, Oct 02, 2008 at 07:05:53PM -0400, Jerry Van Baren wrote:
>> [snip]
>>> diff --git a/include/libfdt.h b/include/libfdt.h
>>> index 5492a53..7cad68c 100644
>>> --- a/include/libfdt.h
>>> +++ b/include/lib
Hello
2008/10/2 Scott Wood <[EMAIL PROTECTED]>:
> On Wed, Oct 01, 2008 at 06:04:02PM -0700, Roman Mashak wrote:
>> As far as I understand not all manufacturers adhere to CFI standards,
>> so this is flash chip's problem rather then board itself.
>> CFI is for both NAND and NOR flash devices (even
The ID EEPROM on MPC8572DS board locates on I2C bus 1. Its the storage for
system information like mac addresses etc. This patch enables it.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8572DS.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff
On Fri, Oct 03, 2008 at 03:09:06PM -0500, Jon Loeliger wrote:
> Petri Lehtinen wrote:
>> On Thu, Oct 02, 2008 at 07:05:53PM -0400, Jerry Van Baren wrote:
>> [snip]
>>> diff --git a/include/libfdt.h b/include/libfdt.h
>>> index 5492a53..7cad68c 100644
>>> --- a/include/libfdt.h
>>> +++ b/include/li
Dear Wolfgang,
On Sat, 2008-10-04 at 01:33 +0200, Wolfgang Denk wrote:
> Dear Haiying,
>
> In message <[EMAIL PROTECTED]> you wrote:
> > MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus
> > 1
> > according to the board spec, and adds the 2nd i2c bus offset.
> >
> > Si
On Sat, 2008-10-04 at 01:35 +0200, Wolfgang Denk wrote:
> Dear Haiying Wang,
>
> In message <[EMAIL PROTECTED]> you wrote:
> > Fix some bugs:
> > 1. Correctly set intlv_ctl in cs_config.
> > 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> > 3. Set base_address an
Hello,
I have a question relating to doing saveenv from the u-boot command line
(after hitting key to stop autoboot), and having u-boot come up during
the next reboot with the saved environment.
First of all, I apologize in advance if this question is out of place in
this mailing list.
This ma
Wolfgang Denk wrote:
> Dear Adam Graham,
[snip]
>> + * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
>> + * memory region. Right now the cache should still be disabled in U-Boot
>> + * because of the EMAC driver, that need it's buffer descriptor to be
>> located
>
> Ni
SDRC MCFG Register configuration corrected for SDP3430.
Signed-off-by: Shankarganesh K <[EMAIL PROTECTED]>
---
board/omap/board-sdp343x.c | 45
+
1 file changed, 13 insertions(+), 32 deletions(-)
Index: U-BOOT_V2/board/omap/board-sdp343x.c
===
Dear Timur,
In message <[EMAIL PROTECTED]> you wrote:
>
> The PRINTD is irrelevant. If these platforms really want to debug single I2C
> operations, they can add the code back. It's just debug code, so I would
> think
> that it's not worth sacrificing the improved code simplicity just for that
Dear Timur,
In message <[EMAIL PROTECTED]> you wrote:
>
> Who is the maintainer for I2C? I don't know who needs to ACK this
> patch for it to go in, and I don't know who's supposed to pick it up,
> either.
In case there is no specific custodian, I will be the default.
Best regards,
Wolfgang D
Dear Haiying Wang,
In message <[EMAIL PROTECTED]> you wrote:
> Fix some bugs:
> 1. Correctly set intlv_ctl in cs_config.
> 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
> 3. Set base_address and total memory for each ddr controller in memory
> controller int
Dear Haiying,
In message <[EMAIL PROTECTED]> you wrote:
> MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
> according to the board spec, and adds the 2nd i2c bus offset.
>
> Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
I see "[PATCH 1/3] Minor fixes for I2C addre
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> After changing SDRAM_CLKTR phase value rerun the memory preload
> initialization sequence (INITPLR) to reset and relock the memory DLL.
> Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects
> the phase relat
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board
> is a dual processor board with each processor providing independent resources
> for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has
Dear "Nikita V. Youshchenko",
In message <[EMAIL PROTECTED]> you wrote:
>
> ads5121: support for running from memory
Ummm... (NOR) flash is memory, too. I guess you mean explicitely
running from RAM, don't you? Then please write what you mean.
> - helps u-boot to find it's environment in
Wolfgang Denk wrote:
>> -void i2c_reg_write(uchar chip, uchar reg, uchar val)
>> -{
>> -PRINTD("i2c_reg_write: chip=0x%02x, reg=0x%02x, val=0x%02x\n", chip,
>> -reg, val);
>> -i2c_write(chip, reg, 0, &val, 1);
>> -}
>> -
>
> This does not exactly look identical to me.
Dear Timur Tabi,
In message <[EMAIL PROTECTED]> you wrote:
> All implementations of the functions i2c_reg_read() and i2c_reg_write() are
> identical. We can save space and simplify the code by converting these
> functions into inlines and putting them in i2c.h.
Actually they are not identical:
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> Provide a weak defined routine to retrieve the CPU number for reference
> boards that have multiple CPU's. Default behavior is the existing single CPU
> print output. Reference boards with multiple CPU's need to provide a board
> s
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> This patch add the capability to configure a PPC440 based IBM SDRAM
> Controller with static, compiled-in, values. PPC440 memory subsystem
> includes a Memory Queue core.
Line too long.
> + * This DDR2 setup code can dynamically se
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board
> is a dual processor board with each processor providing independent resources
> for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has
Wolfgang,
Who is the maintainer for I2C? I don't know who needs to ACK this
patch for it to go in, and I don't know who's supposed to pick it up,
either.
On Thu, Oct 2, 2008 at 10:06 AM, Timur Tabi <[EMAIL PROTECTED]> wrote:
> All implementations of the functions i2c_reg_read() and i2c_reg_write
Hi Alemao,
> In my MPC8360 board I have the BMS bit (from the reset configuration
> word high register, CFG_HRCW_HIGH in u-boot) seted to '0', that means:
>
>8 Mbytes at 0x_ to 0x007F_
Yep, an 8MB window starting at address zero.
The processor will jump to address 0x100 when
Hi all,
In my MPC8360 board I have the BMS bit (from the reset configuration
word high register, CFG_HRCW_HIGH in u-boot) seted to '0', that means:
8 Mbytes at 0x_ to 0x007F_
But then still in u-boot I set my DDR & Flash:
CFG_DDR_BASE 0x
CFG_FLASH_B
Petri Lehtinen wrote:
> On Thu, Oct 02, 2008 at 07:05:53PM -0400, Jerry Van Baren wrote:
> [snip]
>> diff --git a/include/libfdt.h b/include/libfdt.h
>> index 5492a53..7cad68c 100644
>> --- a/include/libfdt.h
>> +++ b/include/libfdt.h
>> @@ -459,6 +459,32 @@ static inline void *fdt_getprop_w(void *
On Thu, Oct 02, 2008 at 07:05:53PM -0400, Jerry Van Baren wrote:
[snip]
> diff --git a/include/libfdt.h b/include/libfdt.h
> index 5492a53..7cad68c 100644
> --- a/include/libfdt.h
> +++ b/include/libfdt.h
> @@ -459,6 +459,32 @@ static inline void *fdt_getprop_w(void *fdt, int
> nodeoffset,
> uint
Scott,
many thanks for the review!
As this code is directly taken from some TI code, it seems I have to
find somebody who can answer your questions and rework the code now.
Will do so now. Unfortunately, I don't know a lot about NAND.
Thanks
Dirk
Scott Wood wrote:
> On Fri, Oct 03, 2008 at 1
On Fri, Oct 03, 2008 at 12:40:25PM +0200, [EMAIL PROTECTED] wrote:
> +#include
> +#include
> +#include
> +#include
> +
> +#if defined(CONFIG_CMD_NAND)
> +
> +#include
Move the #ifdef to the Makefile.
> +/*
> + * nand_read_buf16 - [DEFAULT] read chip data into buffer
> + * @mtd: MTD devic
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/f
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interlea
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/main.c| 37 +++
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cp
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: James Yang <[EMAIL PROTECTED]>
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
board/f
* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.
* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interlea
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/ctrl_regs.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6297141..1783e92 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/
* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cpu/mpc8xxx/ddr/main.c| 37 +++
Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.
* move ddr dimm parameters header file from
Current new DDR code has included DDR interleaving support but has not
been tested out. The following patches fix the bugs for common code,
enable run time configuration of memory controller interleaving mode and
bank interleaving mode and add board specific parameters table to
decides the ddr cont
Fix some bugs:
1. Correctly set intlv_ctl in cs_config.
2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
3. Set base_address and total memory for each ddr controller in memory
controller interleaving mode.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
cp
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8536DS.h |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index 2578bef..0ecf2a2 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/M
MPC8572DS has two i2c buses. This patch moves the DDR SPD_EEPROM to i2c bus 1
according to the board spec, and adds the 2nd i2c bus offset.
Signed-off-by: Haiying Wang <[EMAIL PROTECTED]>
---
include/configs/MPC8572DS.h |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git
On Thu, Oct 2, 2008 at 9:39 PM, Nobuhiro Iwamatsu <[EMAIL PROTECTED]> wrote:
> Hi, all
>
> 2008/10/3 Ben Warren <[EMAIL PROTECTED]>:
>> Jean-Christophe PLAGNIOL-VILLARD wrote:
>>> On 23:07 Wed 01 Oct , Ben Warren wrote:
>>>
Hi Nobuhiro-san,
Nobuhiro Iwamatsu wrote:
> get
Changed MIMC200 board setup and config to use CONFIG_DISABLE_CONSOLE.
Also fixed default uImage location.
Signed-off-by: Mark Jackson <[EMAIL PROTECTED]>
---
board/mimc/mimc200/mimc200.c |2 +-
include/configs/mimc200.h|6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
dif
Subject: [PATCH 12/12 v2] ARM: OMAP3: Add Overo board
From: Dirk Behme <[EMAIL PROTECTED]>
Add Overo board
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)
Makefile |3
board/omap3
Subject: [PATCH 11/12 v2] ARM: OMAP3: Add EVM board
From: Dirk Behme <[EMAIL PROTECTED]>
Add EVM board
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)
Makefile|3
board/omap3/evm/M
Subject: [PATCH 10/12 v2] ARM: OMAP3: Add BeagleBoard
From: Dirk Behme <[EMAIL PROTECTED]>
Add BeagleBoard
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Rebase against u-boot-arm.git next (CFG vs. CONFIG changes)
Makefile |7
board/omap
Subject: [PATCH 09/12 v2] ARM: OMAP3: Add I2C support
From: Dirk Behme <[EMAIL PROTECTED]>
Add I2C support
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Remove SMC911X network init as proposed by Ben Warren. Thanks!
drivers/i2c/Makefile |1
drivers/i2c
Subject: [PATCH 08/12 v2] ARM: OMAP3: Add MMC support
From: Dirk Behme <[EMAIL PROTECTED]>
Add MMC support
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in v2:
- Move MMC driver to drivers/mmc/ as suggested by Haavard Skinnemoen. Thanks!
---
drivers/mmc/Makefile
Subject: [PATCH 07/12 v2] ARM: OMAP3: Add memory and syslib common files, add
NAND support
From: Dirk Behme <[EMAIL PROTECTED]>
Add memory and syslib common files, add NAND support
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Move common ARM Cortex A8 code to cpu
Subject: [PATCH 06/12 v2] ARM: OMAP3: Add board, clock and interrupts common
files
From: Dirk Behme <[EMAIL PROTECTED]>
Add board, clock, cpu and interrupts common files
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Move common ARM Cortex A8 code to cpu/arm_cortex
Subject: [PATCH 05/12 v2] ARM: OMAP3: Add lowlevel init and sys_info common
files
From: Dirk Behme <[EMAIL PROTECTED]>
Add assembly lowlevel init and sys_info common files
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Move common ARM Cortex A8 code to cpu/arm_cort
From: Dirk Behme <[EMAIL PROTECTED]>
Add ARM Cortex A8 common directory
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
cpu/arm_cortexa8/Makefile | 43 +++
cpu/arm_cortexa8/config.mk | 36 +++
cpu/arm_cortexa8/cpu.c | 221 +++
cpu/arm_cortexa8/start.S | 522 ++
Subject: [PATCH 03/12 v2] ARM: OMAP3: Add overo pin mux, omap3 and prototype
headers
From: Dirk Behme <[EMAIL PROTECTED]>
Add overo pin mux, omap3 and prototype headers
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
Changes in version v2:
- Update Overo pin mux to add and pull down X_GATE,
Subject: [PATCH 02/12 v2] ARM: OMAP3: Add i2c, memory and additional pin mux
headers
From: Dirk Behme <[EMAIL PROTECTED]>
Add OMAP3 I2C, memory and additional pin mux headers
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
include/asm-arm/arch-omap3/i2c.h | 128 ++
include/asm-
Subject: [PATCH 01/12 v2] ARM: OMAP3: Add pin mux, clock and cpu headers
From: Dirk Behme <[EMAIL PROTECTED]>
Add pin mux, clock and cpu header files for OMAP3.
Signed-off-by: Dirk Behme <[EMAIL PROTECTED]>
---
include/asm-arm/arch-omap3/bits.h | 48 +++
include/asm-arm/arch-omap3/cl
Subject: [PATCH 00/12 v2] ARM: OMAP3: Add support for some of TIs ARM-Cortex A8
OMAP3 boards
This patch series adds U-Boot v1 support for some of TI's ARM-Cortex A8 based
OMAP3 boards. These are BeagleBoard [1][2], EVM [3] and Overo [4].
The patch series is based on U-Boot tar ball [5] for Beag
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