Hi ,
The kernel source is working fine with zImage. The kernel boots up comfortable
when given boot_zImage command from uboot. I think there are less chances for
MMU configuration trouble.
Is there any extra configuration required for loading the uncompressed image.?
thanks regardsGIGIN
---
Dear MrGates,
In message 89e1f23fa74d47e7b01be455b231e...@mrgates you wrote:
(gdb) step
_start () at start.S:41
41 in start.S
...
_start () at start.S:47
47 in start.S
(gdb)
reset () at start.S:108
108 in start.S
...
reset () at start.S:124
124 in start.S
(gdb)
2011/1/6 YiChao Ma y...@mail.ustc.edu.cn:
hi:
My question is why e500 unlock_ram_in_cache in board.c ,and e300
unlock_ram_in_cache in bootm.c?
I also find this weeks ago.Maybe we can conmbine them.
___
U-Boot mailing list
U-Boot@lists.denx.de
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller
is connected with switch or we use both of the two pcie controller.
Signed-off-by: Baidu Boy liucai@gmail.com
---
arch/powerpc/cpu/mpc83xx/pcie.c |8 ++--
1 files changed, 6 insertions(+), 2
This patch fix a problem for the pcie enumeration when the mpc83xx pcie
controller
is connected with switch or we use both of the two pcie controller.
Signed-off-by: Baidu Boy liucai@gmail.com
---
Changes for v2:
- Avoid line wrap in the patch
arch/powerpc/cpu/mpc83xx/pcie.c |8
On Jan 3, 2011, at 3:47 PM, Wolfgang Denk wrote:
Dear York Sun,
In message 1294089991.24386.58.ca...@oslab-l1 you wrote:
Hm... I have no idea whish sort of buggy code you are referring to
here, but in this case we shoul start and fix that buggy code, right?
Making a buffer in a
From: seedshope bocui...@gmail.com
CONFIG_SYS_INIT_SP_ADDR point the last PHY of IRAM
and substract the global size.
Signed-off-by: seedshope bocui...@googlemail.com
diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index 671f2c7..037db4f 100644
---
From: seedshope bocui...@gmail.com
Remove u-boot-nand.lds from board/samsung/smdk6400 and
use the common u-boot.lds of arm1176 cpu layer. This
patch also fix the building errors:
arch/arm/cpu/arm1176/s3c64xx/libs3c64xx.o: In function `mem_ctrl_asm_init':
From: seedshope bocui...@gmail.com
Modify u-boot.lds from nand_spl/board/samsung/smdk6400.
start.o: In function `clbss_l':
nand_spl/board/samsung/smdk6400/start.S:357: undefined reference to
`coloured_LED_init'
nand_spl/board/samsung/smdk6400/start.S:358: undefined reference to `red_LED_on'
On Fri, 2011-01-07 at 09:14 -0600, Kumar Gala wrote:
On Jan 3, 2011, at 3:47 PM, Wolfgang Denk wrote:
Dear York Sun,
In message 1294089991.24386.58.ca...@oslab-l1 you wrote:
Hm... I have no idea whish sort of buggy code you are referring to
here, but in this case we shoul start
Dear Kumar Gala,
In message 740df509-6661-4611-be1b-bbb629012...@kernel.crashing.org you wrote:
Making a buffer in a function's stack and make use of it out of the
scope, that's the buggy code I am referring.
That is bad indeed, and needs to be fixed.
Where is that happening?
Dear York Sun,
In message 1294418957.8466.8.ca...@oslab-l1 you wrote:
fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=off,addr_hash=false
With the buffer size 128, the sub function gets
ctlr_intlv=cacheline,bank_intlv=cs0_. It is not because the buffer is
not enough, but the
On Fri, 7 Jan 2011 20:42:51 +0800
Baidu Boy liucai@gmail.com wrote:
Signed-off-by: Baidu Boy liucai@gmail.com
Sign-offs (and ideally the From: field as well) should contain your
real name.
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index
Dear Mr. Frysinger,
the Blackfin U-Boot GPIO command (see arch/blackfin/cpu/cmd_gpio.c)
specifies the port/pin naming in the form [p][port]#, e.g. PF11.
The pin portion of the specified GPIO is limited to 0..15.
While this is correct for Blackfins with different bank names (e.g.
BF537 with PF,
On Thu, 6 Jan 2011 11:11:21 +0800
YiChao Ma y...@mail.ustc.edu.cn wrote:
hi:
My question is why e500 unlock_ram_in_cache in board.c ,and e300
unlock_ram_in_cache in bootm.c?
e500 uses the data cache for normal caching after it's done with
the locked SRAM. e300 doesn't -- mainly as a
On Friday, January 07, 2011 15:50:30 Andreas Pretzsch wrote:
the Blackfin U-Boot GPIO command (see arch/blackfin/cpu/cmd_gpio.c)
specifies the port/pin naming in the form [p][port]#, e.g. PF11.
The pin portion of the specified GPIO is limited to 0..15.
While this is correct for Blackfins with
On Jan 7, 2011, at 11:52 AM, Wolfgang Denk wrote:
Dear York Sun,
In message 1294418957.8466.8.ca...@oslab-l1 you wrote:
fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=off,addr_hash=false
With the buffer size 128, the sub function gets
ctlr_intlv=cacheline,bank_intlv=cs0_.
Le 07/01/2011 16:53, seedshope a écrit :
From: seedshopebocui...@gmail.com
CONFIG_SYS_INIT_SP_ADDR point the last PHY of IRAM
and substract the global size.
Signed-off-by: seedshopebocui...@googlemail.com
Please fix the From: line in all patches in this set; it should not
appear in the
Le 07/01/2011 16:53, seedshope a écrit :
From: seedshopebocui...@gmail.com
Remove u-boot-nand.lds from board/samsung/smdk6400 and
use the common u-boot.lds of arm1176 cpu layer. This
patch also fix the building errors:
arch/arm/cpu/arm1176/s3c64xx/libs3c64xx.o: In function
Hi seedshope,
Le 07/01/2011 16:53, seedshope a écrit :
From: seedshopebocui...@gmail.com
Modify u-boot.lds from nand_spl/board/samsung/smdk6400.
You're also modifying start.S. If you mention files in the patch
summary, then please mention them all.
start.o: In function `clbss_l':
Hi John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
Signed-off-by: John Rigbyjohn.ri...@linaro.org
+
+void board_init_f(unsigned long bootflag)
+{
+ nand_boot();
+}
+
I see that you have added a call to nand_boot() in start.S too.
Which is the intended one?
If we jump to
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU
- Add generic ARMv7 cache maintenance operations that affect all
caches known to
Le 22/12/2010 12:54, Aneesh V a écrit :
make default implementation of cache_flush() weakly linked so that
sub-architectures can override it
Signed-off-by: Aneesh Vane...@ti.com
Acked-by: Albert Aribaud albert.arib...@free.fr
Amicalement,
--
Albert.
On Fri, Jan 7, 2011 at 11:33 PM, Aneesh V ane...@ti.com wrote:
Hi John,
On Tuesday 28 December 2010 06:17 AM, John Rigby wrote:
Signed-off-by: John Rigbyjohn.ri...@linaro.org
+
+void board_init_f(unsigned long bootflag)
+{
+ nand_boot();
+}
+
I see that you have added a call to
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
- Enable I-cache on bootup
- Enable MMU and D-cache immediately after relocation
- Do necessary initialization before enabling d-cache and MMU
- Changes to cleanup_before_linux()
- Make changes according to the new framework
Hi Aneesh,
Le 22/12/2010 12:54, Aneesh V a écrit :
1. make sure that page table setup is not done multiple times
2. flush_dcache_all() is more appropriate while disabling cache
than a range flush on the entire memory(flush_cache())
Provide a default implementation for
Le 28/12/2010 20:51, Paulraj, Sandeep a écrit :
Subject: [U-Boot] [PATCH 0/8] armv7: cache maintenance operations
With D-cache and MMU enabled for ARM in u-boot it becomes imperative to
support a minimal set of cache maintenance operations and necessary
initializations before enabling MMU.
Hi,
Le 05/01/2011 06:27, Minkyu Kang a écrit :
How about v1 patch for NULL pointer.
Do you agreed with this patch?
http://patchwork.ozlabs.org/patch/76784/
This one I'm okay with; please repost as a non-RFC, simple, [PATCH].
If so, I'm going to make a patch for all of ARM CPUs.
That would
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