Dear Minkyu,
On 7 December 2012 13:19, Minkyu Kang wrote:
> Dear Chander,
>
> On 02/11/12 19:51, Chander Kashyap wrote:
>> ping
>>
>> On 2 October 2012 15:16, Chander Kashyap wrote:
>>> This patch series popultes Register addresses, clock structure and
>>> gpio structure for Exynos4x12.
>>>
>>>
Dear Chander,
On 02/11/12 19:51, Chander Kashyap wrote:
> ping
>
> On 2 October 2012 15:16, Chander Kashyap wrote:
>> This patch series popultes Register addresses, clock structure and
>> gpio structure for Exynos4x12.
>>
>> Changes in v2:
>> - Fixed the GPIO base address macro for exyno
Add dataflash boot support on at91sam9x5ek board
Signed-off-by: Bo Shen
---
boards.cfg |1 +
include/configs/at91sam9x5ek.h | 10 ++
2 files changed, 11 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 70a1569..e799d9b 100644
--- a/boards.cfg
+++ b/boar
Dear Jaehoon,
On 22/11/12 13:22, Jaehoon Chung wrote:
> To get exactly clock value for mmc, support the get_mmc_clk() like
> set_mmc_clk().
>
> Signed-off-by: Jaehoon Chung
> Signed-off-by: Kyungmin Park
> ---
> arch/arm/cpu/armv7/exynos/clock.c | 107
>
On 12/6/2012 5:12 PM, Stefan Roese wrote:
Hi Vipin,
On 12/06/2012 10:05 AM, Vipin Kumar wrote:
As you can see, I have added your Acked-by to patches 2, 3, 4, 6
The reset are still pending. If you can quickly close them, I can send a
pull-request for these patches
I'm fine with all patches now
On 12/7/2012 12:57 AM, Scott Wood wrote:
On 12/06/2012 01:21:28 AM, Vipin Kumar wrote:
This patch forces to read the bad block marker from location 0 in
large page
nand devices and location 5 in small page devices.
Signed-off-by: Vipin Kumar
Reviewed-by: Shiraz Hashim
---
drivers/mtd/nand/fsm
This converts MPC8313ERDB NAND boot to use the new SPL infrastructure.
Signed-off-by: Scott Wood
Cc: Kim Phillips
---
board/freescale/mpc8313erdb/mpc8313erdb.c | 10 +--
boards.cfg |4 +-
include/configs/MPC8313ERDB.h | 43 +++
This adds arch support for PPC mpc83xx to boot "minimal" (4K) SPLs
using the new infrastructure.
Existing nand_spl targets are updated to deal with the name change
from nand_init.c to spl_minimal.c (as in theory this isn't limited
to NAND anymore).
Signed-off-by: Scott Wood
Cc: Kim Phillips
---
This was already used by some SPL targets, and allows the pad amount to
be specified by board config headers rather than only in makefile
fragments.
Also supply a pad-to of zero if the variable is undefined. It works
without this, but this avoids relying on undocumented behavior.
Signed-off-by:
Hi Tom,
I have included a config change 'Fix coreboot config to boot on
Chromebook' as I found after all this work that it did not actually
boot correctly without this. I hope that is ok. This should be the
final pull request for x86 until 'next' opens.
The following changes since commit 468ebf1
On Fri, Nov 09, 2012 at 10:22:11AM +0100, Piotr Wilczek wrote:
> This patch series provides a new command - "gpt" for eMMC partition table
> (in the GPT format) restoration.
>
> As a pre-work, some cleanup at the part_efi.c file was performed to
> remove custom macros and make GPT related structu
On 12/06/2012 07:18 PM, Daniel Stodden wrote:
On Thu, 2012-12-06 at 11:59 +0100, Sebastian Hesselbarth wrote:
So finally, we have three options:
- leave kwboot as is and hope the user will know about Dove's inability to
use the boot sequence
- add a note to usage() and kwboot that Dove doen't li
On 12/06/2012 01:21:28 AM, Vipin Kumar wrote:
This patch forces to read the bad block marker from location 0 in
large page
nand devices and location 5 in small page devices.
Signed-off-by: Vipin Kumar
Reviewed-by: Shiraz Hashim
---
drivers/mtd/nand/fsmc_nand.c | 2 +-
1 file changed, 1 inse
On 12/01/2012 11:02:05 AM, Deltour, Stephane wrote:
I had a few boards with NAND related problems. In Linux a file was
written to a JFFS2 partition in NAND, but u-boot was unable to read
the
same file correctly from the JFFS2. This happened to be often the case
if the NAND had a few bad blocks
On 11/28/2012 03:06:00 PM, Phil Sutter wrote:
Hi,
On Tue, Nov 27, 2012 at 04:04:15PM -0600, Scott Wood wrote:
> On 11/21/2012 06:59:19 AM, Phil Sutter wrote:
> > Without this patch, when the currently chosen environment to be
> > written
> > has bad blocks, saveenv fails completely. Instead, whe
On Thu, 2012-12-06 at 11:59 +0100, Sebastian Hesselbarth wrote:
> On 12/05/2012 11:15 PM, Daniel Stodden wrote:
> > On Sun, 2012-12-02 at 20:15 +0100, Luka Perkov wrote:
> >> On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
> >>> On Dove kwboot can also be used to boot an u-bo
Dear Simon Glass,
> Hi Marek,
>
> On Thu, Dec 6, 2012 at 10:02 AM, Marek Vasut wrote:
> > Dear Simon Glass,
> >
> > [...]
> >
> >> > [...]
> >> >
> >> > error output should be really puts() or printf() ...
> >>
> >> Ick that bloats the code badly for an uncommon case. Would really
> >> prefe
Hi Marek,
On Thu, Dec 6, 2012 at 10:02 AM, Marek Vasut wrote:
> Dear Simon Glass,
>
> [...]
>
>> > [...]
>> >
>> > error output should be really puts() or printf() ...
>>
>> Ick that bloats the code badly for an uncommon case. Would really
>> prefer to avoid this.
>
> What do you mean? Are you sa
Dear Simon Glass,
[...]
> > [...]
> >
> > error output should be really puts() or printf() ...
>
> Ick that bloats the code badly for an uncommon case. Would really
> prefer to avoid this.
What do you mean? Are you saying this debug() is correct and this is triggered
often? How come?
> > You
Hi Marek,
On Thu, Dec 6, 2012 at 9:39 AM, Marek Vasut wrote:
> Dear Rajeshwari Shinde,
>
>> Adding fdt support to ehci-exynos in order to parse
>> register base addresses from the device node.
>>
>> Signed-off-by: Vivek Gautam
>> Signed-off-by: Rajeshwari Shinde
>> ---
>> Chnages in V2:
>>
Dear Rajeshwari Shinde,
Subject ... add "device" node ...
> This patch adds the device node required for USB
>
> Signed-off-by: Vivek Gautam
> ---
> Chnages in V2:
> - None
> arch/arm/dts/exynos5250.dtsi |7 +++
> 1 files changed, 7 insertions(+), 0 deletions(-)
>
> diff --git a
Dear Rajeshwari Shinde,
> Adding fdt support to ehci-exynos in order to parse
> register base addresses from the device node.
>
> Signed-off-by: Vivek Gautam
> Signed-off-by: Rajeshwari Shinde
> ---
> Chnages in V2:
> - Removed checkpatch errors.
> drivers/usb/host/ehci-exynos.c | 59
>
Dear Vipin Kumar,
> Few pen drives take longer than usual for enumeration. The u-boot unlike
> linux does not depend on interrupts and works in polling and timeout mode.
Good, can you maybe poll the register instead of adding arbitrary delay which
will cause trouble to everyone even if they neve
On Thu, Dec 06, 2012 at 03:57:42PM +0100, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following fix:
>
> The following changes since commit fb3d2b8a3fc26ffb0127fd0fed90ff5f074e67d7:
>
> Makefile: Add target for combined spl/u-boot.bin & u-boot.img (2012-12-05
> 17:31:30 +0100)
>
> are
On 06/12/2012 16:23, Lukasz Majewski wrote:
> Do not compile in FDT related code, when it is not supported.
>
> Signed-off-by: Lukasz Majewski
> Signed-off-by: Kyungmin Park
> ---
> common/cmd_spl.c |2 ++
> 1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/common/cmd_spl.c
Do not compile in FDT related code, when it is not supported.
Signed-off-by: Lukasz Majewski
Signed-off-by: Kyungmin Park
---
common/cmd_spl.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/common/cmd_spl.c b/common/cmd_spl.c
index 9ec054a..e3c543b 100644
--- a/common
Support for a new command (defined at envs) - spl_export generates
the ATAGS image necessary for fast boot. Afterwards, it is stored
at ext4 partition.
Generated image format:
CRC [4B] SIZE [4B] PAYLOAD(ATAGS/DT) [SIZE]
Remarks:
- CRC is calculated only for PAYLOAD
- SIZE is the size of PAYLOAD
Hi Tom,
please pull the following fix:
The following changes since commit fb3d2b8a3fc26ffb0127fd0fed90ff5f074e67d7:
Makefile: Add target for combined spl/u-boot.bin & u-boot.img (2012-12-05
17:31:30 +0100)
are available in the git repository at:
git://www.denx.de/git/u-boot-ppc4xx.git mas
On 11/02/2012 02:30 PM, Matthias Fuchs wrote:
> This patch fixes an issue with overlapping PCI regions
> on boards with more than 64MB RAM.
>
> Signed-off-by: Matthias Fuchs
Applied.
Thanks,
Stefan
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Patch 66863b05 [cfi_flash: add support for Spansion flash PPB sector
protection] introduced the PPB (Persistent Protection Bit) locking for
Spansion chips. But right now the sector protection status (locked vs
unlocked) is set to unlocked for all sectors upon bootup. The real
sector protection stat
Report the usage of the Advanced Sector Protection (PPB) to the user
upon 'flinfo' command. E.g:
Bank # 1: CFI conformant flash (16 x 16) Size: 64 MB in 512 Sectors
AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2301
Advanced Sector Protection (PPB) enabled
Erase timeout:
Not only Spansion supports the Persistent Protection Bits (PPB) locking.
Other devices like the Micron JS28F512M29EWx also support this type
of locking/unlocking. Detection of support is done in the same way as
done for the Spansion chips - via the 0x49 CFI word.
This patch enables this PPB protec
Consolidate manufacturer matching into the function manufact_match()
and use it.
Signed-off-by: Stefan Roese
---
drivers/mtd/cfi_flash.c | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index b2dfc53..d865c40 1
This patch adds the a4m2k MPC5200B board port. Its a derivate of
the a3m071 board with only minor changes.
Additionally this patch includes some clean-up changes:
- Remove I2C support from a3m071 as its unused
- Fix/enhance default env variables
- Fix some comments
- Add newly introduced CONFIG_SP
On MPC5200, the initial RAM (and gd) is located in the internal
SRAM. So we can actually call the preloader console init code
before calling initdram(). This makes serial output (printf)
available very early, even before SDRAM init, which has been
an U-Boot priciple from day 1.
Signed-off-by: Stef
On 12/06/2012 10:29 AM, Vipin Kumar wrote:
> Signed-off-by: Vipin Kumar
Is this new build target really needed? Please take a look at the
recently added/renamed targets (e.g. u-boot-with-spl.bin or u-boot-img.bin).
If this does not fit, then please add a short description about this new
build ta
On 12/06/2012 10:15 AM, Vipin Kumar wrote:
> C3 is a cryptographic controller which is used by the SPL when DDR ECC support
> is enabled.
>
> Basically, the DDR ECC feature requires the initialization of ECC values
> before
> the DDR can actually be used. To accomplish this, the complete on board
On 12/06/12 11:03, Vipin Kumar wrote:
> On 12/6/2012 1:06 PM, Igor Grinberg wrote:
>> On 12/06/12 08:58, Vipin Kumar wrote:
>>> On 12/6/2012 12:17 PM, Igor Grinberg wrote:
On 12/06/12 08:30, Vipin Kumar wrote:
> Few pen drives take longer than usual for enumeration. The u-boot unlike
Hi Vipin,
On 12/06/2012 10:05 AM, Vipin Kumar wrote:
> As you can see, I have added your Acked-by to patches 2, 3, 4, 6
> The reset are still pending. If you can quickly close them, I can send a
> pull-request for these patches
I'm fine with all patches now. But please wait still a few days for
When reading more then one file via nfs and in the mount/unmountall process
occurs a time out the boot process will be aborted, although eventually the
respons from the NFS server arrives.
This patch does not increment the rpc_id for the communication with the server
when we resend a command timed
Hello Wolfgang, hello all,
sorry for re-sending, but the list didn't accept an attachment.
On 12/05/2012 11:20 PM, Wolfgang Denk wrote:
Dear Matthias Brugger,
In message <50bf9cc3.9020...@gmail.com> you wrote:
I run into an NFS issue when trying to load two files from nfs for
booting (uImage
On 12/06/2012 09:47 AM, Vipin Kumar wrote:
> This patch adds mtd device support for smi devices
>
> Signed-off-by: Vipin Kumar
Acked-by: Stefan Roese
Thanks,
Stefan
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On 12/06/2012 09:47 AM, Vipin Kumar wrote:
> The write loop is checking for dest_addr alignment with page size. This
> sometimes leads to smi controller coming out of write mode and eventually the
> next write failing with ERF1 being set.
>
> To avoid this, write to flash in a tight loop and write
On 12/06/2012 09:47 AM, Vipin Kumar wrote:
> SMI controller reports an error when the code tries to write on the flash area
> with Write Enable command not issued or the bank has come out of the write
> mode.
>
> This error is reported even with a fresh write once the ERF1 or ERF2 is set.
> Clear
On 12/06/2012 10:56 AM, Vipin Kumar wrote:
>>> +#ifdef CONFIG_BOOT_PARAMS_P
>>> + /* Boot params passed to Linux */
>>> + gd->bd->bi_boot_params = CONFIG_BOOT_PARAMS_P;
>>> +#endif
>>
>> Again an ugly #ifdef. Why not something like this instead:
>>
>> Define a default earlier in the code (is
On 12/05/2012 11:15 PM, Daniel Stodden wrote:
On Sun, 2012-12-02 at 20:15 +0100, Luka Perkov wrote:
On Sun, Dec 02, 2012 at 03:36:22PM +0100, Sebastian Hesselbarth wrote:
On Dove kwboot can also be used to boot an u-boot image into RAM.
In contrast to Kirkwood, Dove does not support the UART bo
On Wed, Dec 5, 2012 at 9:39 PM, Wolfram Sang wrote:
> Both patches are correct. Check the kernel code again, please,
> especially the function arguments.
Ok, all is clear after reading the comments of the kernel
gpmi_reset_block function.
Regards,
Fabio Estevam
In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.
To avoid generation of an ext
There are three couple (hcnt/lcnt) of registers for each
speed (SS/FS/HS). The driver needs to set the proper couple
of regs according to what speed we are setting.
Signed-off-by: Armando Visconti
---
drivers/i2c/designware_i2c.c | 28 +---
1 files changed, 13 insertion
Changes from V1:
Added two patches that I missed to send...
Armando Visconti (5):
designware_i2c.c: Added the support for MULTI_BUS
designware_i2c: Added s/w generation of stop bit
designware_i2c: Fixed the setting of the i2c bus speed
designware_i2c.h: Fixed the correct values for SCL low
This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).
Signed-off-by: Armando Visconti
---
drivers/i2c/designware_i2c.c | 82 +-
1 files changed, 81 insertions(+), 1 deletions(-)
diff --git a/drivers/i2c/designware_i2c.c
Signed-off-by: Armando Visconti
---
drivers/i2c/designware_i2c.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index 0dc8884..2faf4a8 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_i2c.
Signed-off-by: Armando Visconti
---
drivers/i2c/designware_i2c.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/designware_i2c.h b/drivers/i2c/designware_i2c.h
index e004152..0dc8884 100644
--- a/drivers/i2c/designware_i2c.h
+++ b/drivers/i2c/designware_
On 12/6/2012 3:14 PM, Stefan Roese wrote:
On 12/06/2012 10:29 AM, Vipin Kumar wrote:
A lot of ARM boards are using board_init routine just to initialize boot_params
variable in the global data structure.
This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
which is ass
C3 is a cryptographic controller which is used by the SPL when DDR ECC support
is enabled.
Basically, the DDR ECC feature requires the initialization of ECC values before
the DDR can actually be used. To accomplish this, the complete on board DDR is
initialized with zeroes. This initialization can
On 12/06/2012 10:29 AM, Vipin Kumar wrote:
> A lot of ARM boards are using board_init routine just to initialize
> boot_params
> variable in the global data structure.
>
> This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
> which is assigned to gd->bd->bi_boot_params
A lot of ARM boards are using board_init routine just to initialize boot_params
variable in the global data structure.
This patch lets the board config files to define a CONFIG_BOOT_PARAMS_P option
which is assigned to gd->bd->bi_boot_params automatically
Consequently, many board_init routines wo
Signed-off-by: Vipin Kumar
---
Makefile | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Makefile b/Makefile
index 8a04727..7f416f4 100644
--- a/Makefile
+++ b/Makefile
@@ -499,6 +499,13 @@ $(obj)u-boot.sb: $(obj)u-boot.bin
$(obj)spl/u-boot-spl.bin
elftosb -z
Certain ARMV7 cpus eg. CortexA9 contains a local and a global timer within the
CPU core itself. This patch adds generic support for local timer.
Signed-off-by: Vipin Kumar
---
arch/arm/cpu/armv7/Makefile | 11 ++-
arch/arm/cpu/armv7/ca9_ltimer.c | 152 ++
Hello Stefan,
As you can see, I have added your Acked-by to patches 2, 3, 4, 6
The reset are still pending. If you can quickly close them, I can send a
pull-request for these patches
Thanks for a fast review
Regards
Vipin
On 12/6/2012 2:17 PM, Vipin KUMAR wrote:
Modifications in v2 (Review
On 12/6/2012 1:06 PM, Igor Grinberg wrote:
On 12/06/12 08:58, Vipin Kumar wrote:
On 12/6/2012 12:17 PM, Igor Grinberg wrote:
On 12/06/12 08:30, Vipin Kumar wrote:
Few pen drives take longer than usual for enumeration. The u-boot unlike linux
does not depend on interrupts and works in polling a
On 12/6/2012 2:02 PM, Stefan Roese wrote:
On 12/06/2012 09:19 AM, Vipin Kumar wrote:
Since I'm the CFI (NOR parallel) flash custodian, I can take these
patches through my repository as well. If there is a dependency with
some of your platforms patches, then the patches can go through your ST
rep
The page size is a flash dependent property and the driver was using a macro in
place of page size. This patch uses the proper page size wrt the flash device
connected on board
Signed-off-by: Vipin Kumar
Acked-by: Stefan Roese
---
drivers/mtd/st_smi.c | 41
This patch adds mtd device support for smi devices
Signed-off-by: Vipin Kumar
---
drivers/mtd/st_smi.c | 167 ++-
1 file changed, 166 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 0ed6c0d..c4780c3 1006
The write loop is checking for dest_addr alignment with page size. This
sometimes leads to smi controller coming out of write mode and eventually the
next write failing with ERF1 being set.
To avoid this, write to flash in a tight loop and write bytewise to also support
not word aligned data bytes
At the start of an smi_write, if the destination address is page aligned, the
Write Enable command is getting issued twice. This patch fixes it by keeping a
flag.
Signed-off-by: Vipin Kumar
Acked-by: Stefan Roese
---
drivers/mtd/st_smi.c | 13 +
1 file changed, 5 insertions(+), 8 de
From: Armando Visconti
Signed-off-by: Vipin Kumar
Signed-off-by: Armando Visconti
Acked-by: Stefan Roese
---
drivers/mtd/st_smi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 30bfa3f..99b9576 100644
--- a/drivers/mtd/st_smi.c
+++ b/driv
Signed-off-by: Vipin Kumar
Acked-by: Stefan Roese
---
drivers/mtd/st_smi.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/st_smi.c b/drivers/mtd/st_smi.c
index 63b10fc..30bfa3f 100644
--- a/drivers/mtd/st_smi.c
+++ b/drivers/mtd/st_smi.c
@@
SMI controller reports an error when the code tries to write on the flash area
with Write Enable command not issued or the bank has come out of the write mode.
This error is reported even with a fresh write once the ERF1 or ERF2 is set.
Clear these flags while initiating a fresh write
Signed-off-
Modifications in v2 (Review comments incorporation)
- Use setbits_le32 and clrbits_le32 whereever applicable in patch-set
- Define smi_mtd_init() routine irrespective of CONFIG_MTD_DEVICE
Modifications in v1
- Add MTD support for smi driver
- Write to flash in a tight loop
- Alphabetically sort th
On 12/6/2012 1:32 PM, Stefan Roese wrote:
On 12/06/2012 07:21 AM, Vipin Kumar wrote:
This patch adds mtd device support for smi devices
Signed-off-by: Vipin Kumar
---
drivers/mtd/st_smi.c | 167 ++-
1 file changed, 165 insertions(+), 2 deletion
On 12/06/2012 09:19 AM, Vipin Kumar wrote:
>> Since I'm the CFI (NOR parallel) flash custodian, I can take these
>> patches through my repository as well. If there is a dependency with
>> some of your platforms patches, then the patches can go through your ST
>> repo as well, after successful revie
The at91sam9m10g45 also support WDRBT bit, add support for it
Signed-off-by: Bo Shen
---
drivers/spi/atmel_spi.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index c7a51f7..ce7d460 100644
--- a/drivers/spi/atmel_spi.c
++
On 12/6/2012 1:05 PM, Stefan Roese wrote:
Hi Vipin,
On 12/06/2012 07:21 AM, Vipin Kumar wrote:
Hello,
This patch-set adds simple fixes for smi driver used in spear devices.
Modifications include
- Add MTD support for smi driver
- Write to flash in a tight loop
- Alphabetically sort the list o
On 12/6/2012 1:07 PM, Stefan Roese wrote:
On 12/06/2012 07:21 AM, Vipin Kumar wrote:
SMI controller reports an error when the code tries to write on the flash area
with Write Enable command not issued or the bank has come out of the write mode.
This error is reported even with a fresh write onc
(Added Mike to Cc)
On 12/06/2012 07:56 AM, Vipin Kumar wrote:
> From: Armando Visconti
>
> This patch adds the support for the ARM PL022 SPI controller for the standard
> variant (0x00041022), which has a 16bit wide and 8 locations deep TX/RX FIFO.
>
> Signed-off-by: Armando Visconti
> Signed-
On 12/06/2012 07:21 AM, Vipin Kumar wrote:
> This patch adds mtd device support for smi devices
>
> Signed-off-by: Vipin Kumar
> ---
> drivers/mtd/st_smi.c | 167
> ++-
> 1 file changed, 165 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/
On 12/06/12 08:30, Vipin Kumar wrote:
> Few pen drives take longer than usual for enumeration. The u-boot unlike linux
> does not depend on interrupts and works in polling and timeout mode.
>
> This patch increases this timeout to increase the set of usb sticks that can
> be
> enumerated by u-boo
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