Hello Jens,
Thanks for your quick response.
Actually I tried with U-Boot latest release (u-boot-2013.01.01.tar.bz2)
also.But I am not able to see the SPLASH SCREEN.
So, please share the SPLASH SCREEN image enable procedure for latest U-boot
(u-boot-2013.01.01.tar.bz2) source code for i.mx53loc
The netargs variable was referencing the non-existing variable
console_mainline. Change that to console variable instead.
Signed-off-by: Alexandre Pereira da Silva
---
include/configs/mx23_olinuxino.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/mx23_oli
From: Nishanth Menon
For production systems it is better to use script images since
they are protected by checksums and carry valuable information
like name and timestamp. Also, you can't validate the content
passed to env import.
But for development, it is easier to use the env import command a
With the kernel moving all towards device tree, this series
adds support to make the device tree boot as the default
for OMAP4/5 platforms.
Nishanth Menon (1):
omap5: Allow use of a plain text env file
Sricharan R (4):
ARM: OMAP5: Rename omap5_evm to omap5_uevm
ARM: OMAP5: Set fdt_high to e
Now with kernel moving to all device tree, the default
boot command is changed to pass the device tree blob.
Also, adding the findfdt command to get the dt-blob
based on the board.
Thanks to Tom Rini for suggesting this.
Acked-by: Nishanth Menon
Signed-off-by: Sricharan R
Tested-by: Nishanth M
The omap5-uevm is the reference board name for OMAP5 soc
based platform. So rename it accordingly.
Acked-by: Nishanth Menon
Signed-off-by: Sricharan R
Tested-by: Nishanth Menon
---
[V2] Formatted the patch using -M option to detect renames
and edited the subject
[V3] No change
board/t
While booting with dt blob, if fdt_high is not set to
0x, the dt blob gets relocated to a high ram address,
which the kernel is not able to use without HIGHMEM.
So set it to 0x to avoid the issue.
Acked-by: Nishanth Menon
Signed-off-by: Sricharan R
Tested-by: Nishanth Menon
---
So with OMAP added to multi platform kernel,
the uImage no more contains a valid load address.
With the uboot already supporting zImage,
change the default boot command to bootz
instead.
Acked-by: Nishanth Menon
Signed-off-by: Sricharan R
Tested-by: Nishanth Menon
---
include/configs/omap4_com
On Mon, Mar 25, 2013 at 11:25 PM, Fabio Estevam wrote:
> Hi Eric,
>
> On Mon, Mar 25, 2013 at 4:14 PM, Eric Nelson
> wrote:
>
>> The Gstreamer VPU plugin breaks on Solo and Quad if get_board_rev()
>> doesn't return 0x61xxx or 0x63xxx. Oddly, the code in vpu_lib.c
>> loads firmware based on the 61
Hi Eric,
On Mon, Mar 25, 2013 at 4:14 PM, Eric Nelson
wrote:
> The Gstreamer VPU plugin breaks on Solo and Quad if get_board_rev()
> doesn't return 0x61xxx or 0x63xxx. Oddly, the code in vpu_lib.c
> loads firmware based on the 61 or 63 reference and yet still
> nominally works on a Solo with a h
When we copy code/data to the main memory, we may need to flush the
cache if required by architecture. It uses the existing function
flush_cache. Syntax is
flush_cache
The addr and size are given in hexadecimal. Like memory command, there is
no sanity check for the parameters.
Signed-off-by: Y
From: Manfred Huber
Due to a Bug in the ROM code of some OMAP3 devices, the TEMT bit is not
set if UART3 is configured before (only THRE is set). Reason is the
disabling of UART3 even though the Transmitter is not empty. Enabling
UART3 allows the Transmitter to be empty.
Signed-off-by: Manfr
Hi Stefan,
> Why don't you just change the mask to support both PHY's with one
struct here? Something like this:
>
> static struct phy_driver ksz9021_driver = {
> - .name = "Micrel ksz9021",
> + .name = "Micrel ksz90x1",
> .uid = 0x221610,
> - .mask = 0xf0,
> + .mask =
Hi,
On Sun, 24 Mar 2013 01:53:08 +0100
Anatolij Gustschin wrote:
> From: Pali Rohár
>
> The "bootmenu" command uses U-Boot menu interfaces and provides
> a simple mechanism for creating menus with several boot items.
Could you please test v4 patches. I've tested them in sandbox and
on a frame
From: Abbas Raza
Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit
interface.
Due to this reason the mmc 8bit default mode f
Hi Fabio,
On 03/16/2013 01:27 PM, Eric Nelson wrote:
Hi Fabio,
>
That said, I don't think any of this can or should be done
without identifying the down-stream code that might break.
I've seen code that scrapes /proc/cpuinfo for the "Revision:"
line and uses that.
My memory is hazy, but I
Hi Sricharan,
On Mon, Mar 25, 2013 at 12:47 PM, Sricharan R wrote:
>All of TWL[46]03[05]_i2c_[write/read]_u8 is doing the same. (ie)
> i2c_write(chip_no, reg, 1, &val, 1);
> i2c_read(chip_no, reg, 1, val, 1);
>
> We always seem to use 1 byte addresses and length.
>
> Then
Hi Nishanth,
On Saturday 23 March 2013 03:03 AM, Nishanth Menon wrote:
> V1: http://patchwork.ozlabs.org/patch/227112/
>
> This series helps standardize register parameters for TWL4030, 6030 and 6035
> used in various OMAP3,4,5 based platforms.
> For historical reasons, we have been following val
Albert,
Please pull u-boot-tegra/master into ARM/master. Thanks!
./MAKEALL for all the Tegra boards is OK, running a ./MAKEALL -a arm
now. Checkpatch.pl is clean.
The following changes since commit b6379e15a70cc2e22486e5962927d9de374d877b:
Merge branch 'u-boot-ti/master' into 'u-boot-arm/mast
From: Ed Swarthout
Only clear IRE bit in qixis brdcfg5 register and keep other bits
unchanged.
Signed-off-by: Ed Swarthout
Signed-off-by: York Sun
---
board/freescale/t4qds/t4240qds_qixis.h |2 +-
board/freescale/t4qds/t4qds.c |4 ++--
2 files changed, 3 insertions(+), 3 dele
From: Ramneek Mehresh
Fix USB device-tree fixup to properly handle device-tree fixup and
print appropriate message when wrong/junk "dr_mode" or "phy_type"
are mentioned in hwconfig string
Signed-off-by: Ramneek Mehresh
---
arch/powerpc/cpu/mpc8xxx/fdt.c |5 +
1 file changed, 5 insertio
From: Poonam Aggrwal
B4420 is a subset of B4860. Merge them in config_mpc85xx.h to simplify
the defines.
- Removed #define CONFIG_SYS_FSL_NUM_CLUSTERS as this is used nowhere.
- defined CONFIG_SYS_NUM_FM1_10GEC to 0 for B4420 as it does not have 10G.
Also move CONFIG_E6500 out of B4860QDSds.h in
From: Roy ZANG
Some legacy RGMII phys don't have in band signaling for the
speed information. so set the RGMII MAC mode according to
the speed got from PHY.
Signed-off-by: Roy Zang
Reported-by: John Traill
---
arch/powerpc/include/asm/fsl_memac.h |4
drivers/net/fm/memac.c
From: Shaohui Xie
Current driver of p5040 assumes 10G port follows 1G port DTSEC5 in
eth port enum structure, it will assign mdio mux depend on this assumption.
This is not true with Fman V3, which added more 1G ports after port DTSEC5
in eth port enum structure, then 10G ports on p5040 will have
From: Shaohui Xie
PC board has different serdes clock setting with PB board, it uses same
serdes frequency setting on bank2 as on bank1. PC board can be distingushed
from PB board by checking CPLD version, if running on PC board, then fix
the serdes reference clock frequency of bank2.
Signed-off
From: Ruchika Gupta
Boot ROM code creates TLB entries for 3.5G space before entering
the u-boot. Earlier we were deleting these entries after early
initialization of CPU. In recent past, code has been added
to invalidate all these entries before relocation of u-boot code.
So this code to delete T
From: Shaohui Xie
Provided a default RCW for P5040, then it can use PBL to build
ramboot image.
Signed-off-by: Shaohui Xie
---
board/freescale/corenet_ds/rcw_p5040ds.cfg | 11 +++
include/configs/corenet_ds.h |2 ++
2 files changed, 13 insertions(+)
create mode 100
T4160 is a subset of T4240. Merge them in config_mpc85xx.h to simplify
the defines. Also move CONFIG_E6500 out of t4qds.h into config_mpc85xx.h.
Signed-off-by: York Sun
---
arch/powerpc/include/asm/config_mpc85xx.h | 44 +++--
include/configs/t4qds.h |
Allow VDD voltage overriding with a command. This is an add-on feasture of
VID. To override VDD, use command vdd_override with the value of voltage
in mV, for example
vdd_override
The above example will set the VDD to 1.050 volt. Any wrong value out of
range of 0.8188 to 1.2125 volt or invalid s
To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.
Core clocks are generated by e
From: Suresh Gupta
- Added SERDES2 PRTCLs = 0x98, 0x9E
- Default Phy Addresses for Teranetics PHY on XAUI card
The PHY addresses of Teranetics PHY on XAUI riser card are assigned
based on the slot it is in. Switches SW4[2:4] and SW6[2:4] on
AMC2PEX-2S On B4860QDS, AMC2PEX
From: James Yang
Add e6500 L2 replacement policy selection. This is compile-time config.
Signed-off-by: James Yang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
arch/powerpc/cpu/mpc85xx/start.S |1 +
arch/powerpc/include/asm/processor.h |9 +
3 files changed, 11 inse
From: Shaohui Xie
TN80xx has same PHY ID as TN2020, but it needs different setting to register
30.93 which used to select line, so we read register 30.32 which has
bit 15:12 to indicate PHY hardware version, for TN20xx we will get 3 or 2,
for TN80xx we will get 5 or 4.
Signed-off-by: Shaohui Xie
The workaround has been updated to use a slightly different magic number.
Change from 0x3000 to 0x30003000.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/ddr-gen3.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
b/arch/power
From: Shengzhou Liu
1, Implemented board_ft_fman_fixup_port() to fix port for kernel.
2, Implemented fdt_fixup_board_enet() to fix node status of different
slots and interfaces.
3, Adding detection of slot present for XGMII interface.
4, There is no PHY for XFI, so removed related phy address
From: Xie Xiaobo
SPANSION recommend S25FL128S supersedes S25FL129P, and the two flash
memory have the same device ID and Memory architecture. So they can
use the same config parameters.
Signed-off-by: Xie Xiaobo
---
drivers/mtd/spi/spansion.c |2 +-
1 file changed, 1 insertion(+), 1 deleti
From: Shaveta Leekha
Signed-off-by: Shaveta Leekha
---
arch/powerpc/include/asm/fsl_law.h |2 ++
board/freescale/b4860qds/law.c |3 +++
include/configs/B4860QDS.h |9 +
3 files changed, 14 insertions(+)
diff --git a/arch/powerpc/include/asm/fsl_law.h
b/arch/pow
From: Stephen George
Debug trace buffers are memory mapped in DCSR space beyond 4M.
Signed-off-by: Stephen George
---
board/freescale/b4860qds/law.c |3 ++-
board/freescale/b4860qds/tlb.c |2 +-
board/freescale/t4qds/law.c|3 ++-
board/freescale/t4qds/tlb.c|2 +-
doc/RE
From: Ed Swarthout
Use QIXIS measurement registers to obtain sysclk and ddr clock. This
allows using non-standard clock speeds, set by directly writing to
clock chip or store the values in qixis clock data eeprom.
Signed-off-by: Ed Swarthout
Signed-off-by: York Sun
---
board/freescale/t4qds/t
From: Shaveta Leekha
Crossbar switches were wrongly programmed to
route the CPRI lanes to SFP as the connectivity table
was not correct.
Modified it correctly for SFPs connections.
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/fdt.c |5
board/freescale/b
From: Liu Gang
Misalignment will be found in the doc/README.srio-pcie-boot-corenet
file when the tabs are set to 8 characters. And the standard for u-boot
should be 8 character tabs!
Signed-off-by: Liu Gang
---
doc/README.srio-pcie-boot-corenet | 12 ++--
1 file changed, 6 insertions
From: Shengzhou Liu
QSGMII card has different PHY address against previous SGMII card.
We check the type of card in slots and set correct PHY address to
avoid complainning "PHY reset timed out" during u-boot booting up.
Signed-off-by: Shengzhou Liu
---
board/freescale/t4qds/eth.c | 19 ++
SW7[4] is the new bit which controls the mapping of eMMC vs SDHC.
Signed-off-by: York Sun
---
board/freescale/t4qds/t4qds.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index b48855e..f0f280b 100644
---
Allow DDR clock runs faster than SPD specifes. This may cause memory
failure, but the user should know what is going to happen when using
higher than expected DDR clock.
Signed-off-by: Ed Swarthout
Signed-off-by: York Sun
---
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|2 --
1 file
From: Ed Swarthout
QIXIS includes frequency measurement functions for each major processor
clock input. After reset (and after clocks are stable), QIXIS measures
the clocks against a reference frequency and stores the results in
CLK_FREQ registers. A base register supplies a multiplier which allo
T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/Makefile |3 +
.../cpu/mpc8
From: Shaohui Xie
Signed-off-by: Shaohui Xie
---
boards.cfg |3 +++
1 file changed, 3 insertions(+)
diff --git a/boards.cfg b/boards.cfg
index 024a29e..c70d041 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -874,6 +874,9 @@ P5020DS_SECURE_BOOT powerpc mpc85xx
corenet_ds
"cpu status" should check if core is disabled before printing
the spin table location.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/mp.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index 43d4836..861c8e0 100644
-
From: Shaohui Xie
Added a default RCW(1_28_6_12) and PBI configure file for T4240, so it can use
PBL tool to produce the ramboot image.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/t4_pbi.cfg | 36
board/freescale/t4qds/t4_rcw.cfg |7 +++
From: Roy Zang
fix the following build error:
pcie.c: In function 'mpc83xx_pcie_init_bus':
pcie.c:315:34: error: 'PCI_LTSSM' undeclared (first use in this
function)
pcie.c:315:34: note: each undeclared identifier is reported only once
for each function it appears in
pcie.c:316:15: error: 'PCI_LTS
From: James Yang
Enable L2 cache parity/ECC error checking.
Signed-off-by: James Yang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c |2 +-
arch/powerpc/cpu/mpc85xx/start.S|2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/pow
B4860QDS requires DDRC2 has 0 as base address and DDRC1 has higher address.
This is the requirement for DSP cores to run in 32-bit address space.
Signed-off-by: York Sun
---
board/freescale/b4860qds/ddr.c | 72
1 file changed, 72 insertions(+)
diff --g
From: Shaohui Xie
QSGMII card assumed to be used by default, but if SGMII card is used,
it will use different PHY address, but we don't know which card is used
until we access PHY on the card. So we check the card type slot by slot,
if we can read a PHY ID by reading a SGMII PHY address on a slot
From: Liu Gang
There are some duplicate SRIO macro definitions should be remove
in below header files:
include/configs/P3041DS.h
include/configs/P4080DS.h
include/configs/P5020DS.h
Signed-off-by: Liu Gang
---
include/configs/P3041DS.h |4
include/configs/P4080
This gives boards flexibility to assign other than default addresses to each
DDR controller. For example, DDR controler 2 can have 0 as the base and DDR
controller 1 has higher memory.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c |7 ++-
1 file changed, 6 insertions(+)
From: Shaohui Xie
Use QSGMII card PHY address as default SGMII card PHY address, QSGMII card
PHY address is variable depends on different slot.
Signed-off-by: Shaohui Xie
---
board/freescale/t4qds/eth.c | 123 +++
include/configs/t4qds.h |1 -
2
From: Shengzhou Liu
Removed unused declare serdes_get_prtcl() which was no longer needed.
Signed-off-by: Shengzhou Liu
---
arch/powerpc/include/asm/fsl_serdes.h |1 -
1 file changed, 1 deletion(-)
diff --git a/arch/powerpc/include/asm/fsl_serdes.h
b/arch/powerpc/include/asm/fsl_serdes.h
From: Roy Zang
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY
initialization can be reused in kernel without “usb start” command.
Signed-off-by: Roy Zang
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 22 ++
drivers/usb/host/ehci-fsl.c | 21
From: Shaohui Xie
The VSC8574 is a quad-port Gigabit Ethernet transceiver with four SerDes
interfaces for quad-port dual media capability. This driver supports SGMII
and QSGMII MAC mode. For now SGMII mode is tested.
Signed-off-by: Roy Zang
Signed-off-by: Shaohui Xie
---
drivers/net/phy/vites
From: Shengzhou Liu
- set proper compatible property name for mEMAC.
- fixed ft_fixup_port for dual-role mEMAC, which will lead to
MAC node disabled incorrectly.
Signed-off-by: Shengzhou Liu
---
drivers/net/fm/fm.h |2 ++
drivers/net/fm/init.c | 25 +
2 files
From: Tang Yuantian
For T4/B4, the clockgen node compatible string is updated to version 2.
Add clock-frequency setting for this new version.
Signed-off-by: Tang Yuantian
---
arch/powerpc/cpu/mpc85xx/fdt.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
From: Mingkai Hu
Calculate reserved fields according to IFC bank count
1. Move csor_ext register behind csor register and fix res offset
2. move ifc bank count to config_mpc85xx.h to support 8 bank count
There's no IFC controller instead of eLBC controller on some platforms,
such as MPC8536, P2
From: Ed Swarthout
Even B4860 has chassis generation 2, but its PCIe registers are at
the same location as other corenet SoCs.
Signed-off-by: Ed Swarthout
---
arch/powerpc/include/asm/immap_85xx.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/include/asm/i
Print more detail information including core voltage, RCW source, switch
settings, etc. with bdinfo command.
Signed-off-by: York Sun
CC: Wolfgang Denk
CC: Tom Rini
---
board/freescale/t4qds/t4qds.c | 100 +
1 file changed, 100 insertions(+)
diff --git
Add board detail function to print more individual board information.
Signed-off-by: York Sun
CC: Wolfgang Denk
CC: Tom Rini
---
common/cmd_bdinfo.c |7 +++
1 file changed, 7 insertions(+)
diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c
index 85279d5..3bf8cf2 100644
--- a/comm
From: Roy ZANG
T4240 PCIe IP is version 3.0 and has some update comparing previous
QorIQ products.
1. Move Freescale specific register define
to
arch/powerpc/include/asm/fsl_pci.h
and update the register offset define for T4240.
2. add the status/control register define
use status/control regi
From: Shaohui Xie
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
include/configs/t4qds.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index fb8863b..c5110c2 100644
--- a/include/configs/t4qds.h
+++ b/in
From: Sandeep Singh
The bit positions for FMAN1 freq in RCW is different for B4860.
Also addded a case when FMAN1 frewuency is equal to systembus.
Signed-off-by: Sandeep Singh
Signed-off-by: Poonam Aggrwal
---
arch/powerpc/cpu/mpc85xx/speed.c |8
1 file changed, 8 insertions(+)
From: Shaohui Xie
When CONFIG_SYS_FSL_QORIQ_CHASSIS2 is not defined, QMAN frequency will not
be initialized, and QMAN will have a wrong frequency display.
Signed-off-by: Shaohui Xie
---
arch/powerpc/cpu/mpc85xx/speed.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/powerpc/cpu
T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.
Signed-off-by
T4160QDS shares the same platform as T4240QDS. T4160 is a low power
version of T4240, with eight e6500 cores, two DDR3 controllers, and
slightly different SerDes protocols.
Signed-off-by: York Sun
---
boards.cfg |3 +++
include/configs/t4qds.h | 15 ++-
2 files cha
Use decimal and hexadecimal for protocol numbers. It helps to match with
SoC user manual.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
b/arch/power
The PIR parsing algorithm we used is not only for E6500. It applies to all
SoCs with chassis 2.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/release.S |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/release.S
b/arch/powerpc/cpu/mpc85
Separate CONFIG_PPC_T4240 from board config file. Prepare to add more SoC
variants supported on the same board.
Signed-off-by: York Sun
---
boards.cfg |6 +++---
include/configs/T4240QDS.h |1 -
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/boards.cfg b/b
Protocols are constants. Fix arrays with const prefix.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/t4240_serdes.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index
From: Roy Zang
The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]
Signed-off-by: Roy Zang
---
board/freescale/t4qds/t4qds.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --gi
T4240 has voltage ID fuse. Read the fuse and configure the voltage
correctly. Core voltage has higher tolerance on over side than below.
Signed-off-by: York Sun
---
board/freescale/t4qds/t4qds.c | 229 +
include/configs/t4qds.h | 12 ++-
2 files c
Missing nodes of crypto, pme, etc in device tree is not a fatal error.
Setting up the qman portal should skip the missing node and continue
to finish the rest.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc85xx/portals.c | 36 ++--
1 file changed, 22 insertion
From: Roy Zang
T4240 internal UTMI phy is different comparing to previous UTMI PHY
in P3041.
This patch adds USB 2.0 UTMI Dual PHY new memory map and enable it for
T4240.
The phy timing is very sensitive and moving the phy enable code to
cpu_init.c will not work.
Signed-off-by: Roy Zang
---
ar
Should check if interleaving is enabled before using interleaving mode.
Signed-off-by: York Sun
---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c
b/arch/powerpc/cpu/mpc8xxx/ddr/m
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
Signed-off-by: York Sun
---
From: Shaohui Xie
1. fix 10G mac offset by plus 8;
2. add second 10G port info for FM1 & FM2 when init ethernet info;
3. fix 10G lanes name to match lane protocol table;
Signed-off-by: Shaohui Xie
Signed-off-by: Roy Zang
---
drivers/net/fm/eth.c |2 ++
drivers/net/fm/init.c |6
From: Andy Fleming
The L1 D-cache on e6500 is write-through. This means that it's not
considered a good idea to have the L1 up and running if the L2 is
disabled. We don't actually *use* the L1 until after the L2 is
brought up on e6500, so go ahead and move the L1 enablement after
that code is don
From: Roy Zang
Lane H on SerDes4 should be SATA2 instead of SATA1
Signed-off-by: Jerry Huang
Signed-off-by: Roy Zang
---
arch/powerpc/cpu/mpc85xx/t4240_serdes.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
b/arch/powerpc/c
From: Shaohui Xie
T4240QDS uses a SST instead of SPANSION SPI flash.
Signed-off-by: Shaohui Xie
---
include/configs/t4qds.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
index 2c665b8..fb8863b 100644
--- a/include/confi
From: Andy Fleming
Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.
Signed-off-by: Andy Fleming
---
arch/powerpc/cpu/mpc85xx/release.S |8
arch/powerpc/cpu/mpc85xx/start.S
From: Roy Zang
Reverse the bit sequence to display serdes clock frequency correctly.
The correct bit maps in BRDCFG2 are
0 1 2 3 4 5 6 7
S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0]
Signed-off-by: Roy Zang
---
board/freescale/t4qds/t4qds
Fix ccsr_gur for corenet platform. Remove non-exist registers. Add fuse
status register.
Signed-off-by: York Sun
---
arch/powerpc/include/asm/immap_85xx.h | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/p
From: Cristian Sovaiala
Extending LIODN offset range from 1-5 to 1-10
While using a qman portal with a higher index the LIODN offset
is incorrectly set, thus extending the range of offsets covers
all 10 qman portals
Signed-off-by: Cristian Sovaiala
Acked-by: Haiying Wang
---
arch/powerpc/cpu/
Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040.
Signed-off-by: York Sun
---
arch/powerpc/include/asm/config_mpc85xx.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index d57c1
From: Shaohui Xie
The Hydra and Superhydra (P3041DS, P5020DS, and P5040DS) boards have a
second USB port that can be configured in either host, peripheral (aka
device), or OTG (on-the-go) mode. When configured in host mode, if
the port is connected to another USB host, damage to the board can
oc
From: Xu Jiucheng
When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR
From: Kumar Gala
SRIO doesn't exist on the P5040DS board and we'll reuse the common
corenet_ds.h for it. So move the SRIO defines into the board specific
headers.
Signed-off-by: Kumar Gala
---
include/configs/P3041DS.h |3 +++
include/configs/P4080DS.h |3 +++
include/configs/P5020DS.
From: Shengzhou Liu
Signed-off-by: Shengzhou Liu
---
doc/README.p1010rdb | 199 +++
1 file changed, 199 insertions(+)
create mode 100644 doc/README.p1010rdb
diff --git a/doc/README.p1010rdb b/doc/README.p1010rdb
new file mode 100644
index 0
From: Timur Tabi
Only some chips have four SerDes banks, so don't define lanes for a bank
that doesn't exist.
This fixes warning message "excess elements in array initializer" for
array lanes[], because that array is defined with a size of SRDS_MAX_LANES,
and the value of SRDS_MAX_LANES depends
From: Zhicheng Fan
Resolve P1020 second USB controller multiplexing with eLBC
- mandatory to mention USB2 in hwconfig string to select it
over eLBC, otherwise USB2 node is removed
- works only for SPI and SD boot
Signed-off-by: Ramneek Mehresh
Signed-off-by: Kumar G
From: Shengzhou Liu
Change flexcan compatible string from "fsl,flexcan-v1.0"
to "fsl,p1010-flexcan" to match the device tree.
Signed-off-by: Shengzhou Liu
---
board/freescale/p1010rdb/p1010rdb.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/p1010rdb/p10
From: Poonam Aggrwal
There could be scenarios where the user would like to manually(via JTAG)
configure the DDR/L2SRAM and load the bootloader binary onto DDR/L2SRAM.
This document explains thse usecases and the detailed explanation of what needs
to be done to use it.
Most of the code from CONFI
Hi,
I start a project on a freescale imx27 using the dm9000a for network.
I learned that the tftp , nfs and other network related working more less very
unstable. I start compare the dm9000.c code with the upstream kernel v3.8.4 and
fix some issues.
issues
tftp
with many bad checksums and
On Monday 25 March 2013 09:31 PM, Nishanth Menon wrote:
> On 13:54-20130323, Sricharan R wrote:
>> With the kernel moving all towards device tree, this series
>> adds support to make the device tree boot as the default
>> for OMAP4/5 platforms.
>>
>> Sricharan R (5):
>> ARM: OMAP5: Rename omap5_e
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