Hi Rajeshwari,
On Mon, 16 Dec 2013 13:12:30 +0530, Rajeshwari Birje
wrote:
> Hi Albert,
>
> Please refer the following patch:
>
> "SPL: EXYNOS: Prepare for variable size SPL support"
>
> http://patchwork.ozlabs.org/patch/298965/
>
> I don't think after this patch is applied, the above patch
Hi Andre,
On Wed, 18 Dec 2013 15:06:04 +0100, Andre Przywara
wrote:
> On 12/17/2013 04:57 PM, Tom Rini wrote:
> > -BEGIN PGP SIGNED MESSAGE-
> > Hash: SHA1
> >
> > On 12/17/2013 10:47 AM, Andre Przywara wrote:
> >> (CCing Inderpal, Chander and Minkyu)
> >>
> >> On 12/17/2013 04:30 PM, To
Hi Fabio,
On Friday, December 20, 2013 9:46:37 PM, Fabio Estevam wrote:
> From: Fabio Estevam
>
> When using the fuse API in U-boot user must calculate the 'bank' and 'word'
> values.
>
> Provide a real example on how to calculate such values for the mx6q.
>
> Signed-off-by: Fabio Estevam
> -
commit f9095aac793aa8917ab9b915c5d449e6dc8d3d30, "mtd: nand:
omap: add CONFIG_NAND_OMAP_ECCSCHEME for selection of ecc-scheme"
removed CONFIG_SPL_NAND_SOFTECC from the tam3517 common config,
causing the spl nand boot to fail. Add it back, so derived
boards boot again.
Cc: Pekon Gupta
Cc: Scott Wo
Commit f33b9bd3984fb11e1d8566a866adc5957b1e1c9d breaks boards
which do not explicitly enable the gpio clocks. This causes
the twister spl to hang, since it uses the no longer enabled
gpio 55. Add CONFIG_OMAP3_GPIO_2 to unbrick the board.
Cc: Stefano Babic
Cc: Tapani Utriainen
Signed-off-by: Jero
On 12/21/2013 11:46 AM, Albert ARIBAUD wrote:
Hi Andre,
On Wed, 18 Dec 2013 15:06:04 +0100, Andre Przywara
wrote:
On 12/17/2013 04:57 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/17/2013 10:47 AM, Andre Przywara wrote:
(CCing Inderpal, Chander and Minkyu)
On 12/
On 12/21/2013 09:57 PM, Andre Przywara wrote:
On 12/21/2013 11:46 AM, Albert ARIBAUD wrote:
Hi Andre,
On Wed, 18 Dec 2013 15:06:04 +0100, Andre Przywara
wrote:
On 12/17/2013 04:57 PM, Tom Rini wrote:
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 12/17/2013 10:47 AM, Andre Przywara wrote
The structures ipu_cm and ipu_idmac contain some reserved arrays as
placeholders to make sure the trailing entries may point to the relevant
IPU registers. This patch corrects the size of the reserved arrays.
Changes in v2:
Added Robin Gong's ack.
Liu Ying (2):
video: ipu reg: Correct reserve
The array reserved as a placeholder in the structure ipu_idmac
should contain 44 32bit unsigned integer entries instead of 45
ones, because the placeholder is located bewteen the register
IDMAC_SC_CORD1 and the register IDMAC_CH_BUSY_1 with the address
offsets of 0x804c and 0x8100 respectively.
Re
The array reserved1 as a placeholder in the structure ipu_cm
should contain 4 32bit unsigned integer entries instead of 16
ones, because the placeholder is located bewteen the register
IPU_CH_DB_MODE_SEL_1 and the register IPU_ALT_CH_DB_MODE_SEL_0
with the address offsets of 0x154 and 0x168 respect
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