From: Kuo-Jung Su dant...@faraday-tech.com
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v11:
- Nothing updates
Changes for v10:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTTMR010 is a simple APB device which supports
generic timer functions.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v11:
- Directly specify the timer object in
From: Kuo-Jung Su dant...@faraday-tech.com
The A369 is an ARM CPU-based SoC with rich SoC features and
convenient FPGA link for building fast system prototyping
and mass production.
More information about this hardware can be found at:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(i.e., IPL, SPL development).
Please check the link bellow for details:
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A369 Virtual SoC platform support.
Here are some public documents for your reference.
http://www.faraday-tech.com/html/Product/SoCPlatform/SoCreativeIII.htm
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday FTPWMTMR010 is a simple APB device which supports
both timer and pwm functions.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Albert Aribaud albert.u.b...@aribaud.net
---
Changes for v11:
- Directly specify the timer object in
From: Kuo-Jung Su dant...@faraday-tech.com
For the Faraday FTSDC021 (SDHCI) controller driver source is
sent out before the patches for Faraday Virtual Machine (FVM)
which actually uses this chip.
The header file (ftsdc021.h) has been accidentally removed
by commit: 3b98b57fa - include: delete
2014-03-25 20:41 GMT+08:00 Albert ARIBAUD albert.u.b...@aribaud.net:
Hi Kuo-Jung,
On Thu, 20 Feb 2014 11:40:32 +0800, Kuo-Jung Su dant...@gmail.com
wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
These patches introduce Faraday A369 Virtual SoC platform support.
Except for patches 4/6
Dear Kuo-Jung Su,
In message 1395813799-3672-2-git-send-email-dant...@gmail.com you wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
...
diff --git a/include/configs/faraday-common.h
Dear Kuo-Jung Su,
In message 1395813799-3672-7-git-send-email-dant...@gmail.com you wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software development
(i.e., IPL, SPL development).
...
+ulong
Hi,
I'm playing with fdt booting on beaglebone board. I'm using latest
u-boot git HEAD (2c072c958bb544c72f0e848375803dbd6971f022) + I've
added to am335x_evm confing :
#ifndef CONFIG_SPL_BUILD
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
#endif
I took beaglebone devicetree from kernel.
2014-03-26 14:47 GMT+08:00 Wolfgang Denk w...@denx.de:
Dear Kuo-Jung Su,
In message 1395813799-3672-2-git-send-email-dant...@gmail.com you wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Here is the list of verified cores:
1. FA606TE (ARMv5TE, no mmu)
2. FA626TE (ARMv5TE)
...
diff
2014-03-26 14:52 GMT+08:00 Wolfgang Denk w...@denx.de:
Dear Kuo-Jung Su,
In message 1395813799-3672-7-git-send-email-dant...@gmail.com you wrote:
From: Kuo-Jung Su dant...@faraday-tech.com
Faraday Virtual Machine (FVM) is a QEMU based emulator
which is designed for early stage software
From: Tang Yuantian yuantian.t...@freescale.com
The supplement configuration unit (SCFG) provides chip-specific
configuration and status registers for the device. It is the chip
defined module for extending the device configuration unit (DCFG)
module. It provides a set of CCSR registers in
From: Tang Yuantian yuantian.t...@freescale.com
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.
On Mon, 2014-03-24 at 23:42 +0100, Olliver Schinagl wrote:
[...]
I've got a local cleanup patch set where I fixed this already to
clrsetbits_le32
[...]
Same here, got that in my local tree too
Could you post what you've got please?
+#ifdef CONFIG_SPL_BUILD
+#define PLL1_CFG(N, K, M, P)
On Mon, 2014-03-24 at 21:52 +0100, Marek Vasut wrote:
On Friday, March 21, 2014 at 10:54:18 PM, Ian Campbell wrote:
This has been stripped back for mainlining and supports only sun7i. These
changes are not useful by themselves but are split out to make the patch
sizes more manageable.
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+ cfg = readl(pio-cfg[0] + index);
+ cfg = ~(0xf offset);
+ cfg |= val offset;
+
+ writel(cfg, pio-cfg[0] + index);
clrsetbits_le32() here.
I looked at this transform in a few different contexts and one concern I
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgpin(u32 pin);
+int sunxi_gpio_set_drv(u32 pin, u32 val);
+int sunxi_gpio_set_pull(u32 pin, u32 val);
+int name_to_gpio(const char *name);
+#define name_to_gpio
On Wednesday, March 26, 2014 at 09:30:38 AM, Ian Campbell wrote:
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+ cfg = readl(pio-cfg[0] + index);
+ cfg = ~(0xf offset);
+ cfg |= val offset;
+
+ writel(cfg, pio-cfg[0] + index);
clrsetbits_le32() here.
On Wednesday, March 26, 2014 at 09:33:01 AM, Ian Campbell wrote:
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgpin(u32 pin);
+int sunxi_gpio_set_drv(u32 pin, u32 val);
+int sunxi_gpio_set_pull(u32 pin, u32
Dear Ian,
[Cc: list truncated / changed]
In message 1395822638.29683.9.ca...@dagon.hellion.org.uk you wrote:
I looked at this transform in a few different contexts and one concern I
had was that readl and writel have barriers in them (after the read and
before the write respectively) while
Dear Ian Campbell,
In message 1395822781.29683.12.ca...@dagon.hellion.org.uk you wrote:
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgpin(u32 pin);
+int sunxi_gpio_set_drv(u32 pin, u32 val);
+int
Hi, experts:
in 32bit ARM SOC platform:
u-boot use unsigned long long as a uint64 data type.
So, if with 74bit ARM SOC:
Long type : means a 64bit data type.
So how to map unsigned long long to a long data type if compiling a
64bit u-boot?
Best wishes,
Can the command be used to load raw data from a partition (GPT) in SATA
SSD? Can you show example using the command? Thanks.
On Mon, Mar 24, 2014 at 9:09 AM, tiger...@via-alliance.com wrote:
Hi,
Is there a command to read raw data from a disk partition to memory?
Nand / mmc command is ok.
On Wed, 2014-03-26 at 10:03 +0100, Wolfgang Denk wrote:
Dear Ian Campbell,
In message 1395822781.29683.12.ca...@dagon.hellion.org.uk you wrote:
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+int sunxi_gpio_set_cfgpin(u32 pin, u32 val);
+int sunxi_gpio_get_cfgpin(u32 pin);
On Wednesday, March 26, 2014 at 10:39:16 AM, Ian Campbell wrote:
On Wed, 2014-03-26 at 10:03 +0100, Wolfgang Denk wrote:
Dear Ian Campbell,
In message 1395822781.29683.12.ca...@dagon.hellion.org.uk you wrote:
On Mon, 2014-03-24 at 21:54 +0100, Marek Vasut wrote:
+int
Hello,
Recently I've found a problem with I2C bus 2 on AM335X based devices.
Executing the command i2c dev 2 in the u-boot CLI causes CPU reset.
The issue is found on v2013.10, v2014.01 and v2014.04-rc1 and appears
on BeagleBone and CM-T335 devices.
Please see the log taken from BeagleBone:
Hello Stephen,
Thanks for review again:)
On 03/25/2014 08:12 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Changes in lib/uuid.c to:
- uuid_str_to_bin()
- uuid_bin_to_str()
New parameter is added to specify input/output string format in listed functions
This
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 03/26/2014 07:10 AM, Ilya Ledvich wrote:
Hello, Recently I've found a problem with I2C bus 2 on AM335X based
devices. Executing the command i2c dev 2 in the u-boot CLI causes
CPU reset. The issue is found on v2013.10, v2014.01 and
v2014.04-rc1
Hello Stephen,
On 03/25/2014 08:37 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Those commands basis on implementation of random UUID generator version 4
which is described in RFC4122. The same algorithm is used for generation
both ids but string representation
Hello Stephen,
On 03/25/2014 08:51 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Changes:
- randomly generate partition uuid if any is undefined and CONFIG_RAND_UUID
is defined
- print debug info about set/unset/generated uuid
- update doc/README.gpt
Update
Hello Stephen,
On 03/25/2014 08:28 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
Source: https://www.ietf.org/rfc/rfc4122.txt
Some nits in
Hello Stephen,
On 03/25/2014 08:51 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Signed-off-by: Przemyslaw Marczak p.marc...@samsung.com
Patch description? Why are these function useful on these platforms?
For completeness (I have no real ack power of Samsung
From: Shaohui Xie shaohui@freescale.com
Also, remove workaround of rev1.0.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
board/freescale/t4qds/t4_pbi.cfg | 14 --
board/freescale/t4qds/t4_rcw.cfg | 6 +++---
2 files changed, 3 insertions(+), 17 deletions(-)
diff
Hi,
I see in u-boot sources that the L2 cache is enabled and invalidated on
OMAP3 using secure monitor calls. Where can I find the documentation for
these calls? I see that the corresponding information is available for
instance for DM8148 in its TRM, but not in OMAP3530 TRM. I am interested
I am trying to do console init before dram init so that I can give inputs
from serial port and then initialize dram and bring up uboot.
But there seems to be some linnking problem. I used serial_init and checked
the makefiles. They seem to be fine. But still when I call serial_init
before dram
Hi
I am currently trying to configure either Altera Soc and Xilinx Zynq to boot
Linux in nonsecure-mode.
This mail focusses on the Altera SOC.
As soon as the u-boot switched to normal mode it seems there is a problem with
code alignment handling?
At least it seems the code which is running
hello,
I try to load from JFFS2 filesystem , the kernel,rootfs and DTB. and I
have bad data CRC error on my file.
Have you any idea of the reason ?
I try to copy several kernel image in the filesystem i've got the same
error, also with rootfs.
I've no problem with raw file and using nand
Dear Ian Campbell,
In message 1395826756.22808.13.ca...@kazak.uk.xensource.com you wrote:
Please add a comment to explain that.
Unless you object I think I'll do as Marek suggested name the function
sunxi_name_to_gpio and make the #define to that, it seems more
consistent that way.
More information : when I compare the file download in ram with fsload and
nand read I have a word of difference ...
If someone have an idea ...
thanks
sophie
fsload 100 uImage
### JFFS2 loading 'uImage' to 0x100
### JFFS2 load complete: 3287019 bytes loaded to 0x100
One9x nand read
T1040RDB and T1040QDS boards have an integrated l2 switch.
The switch needs a MAC address for Layer 2 protocols
(MSTP, LLDP, LACP, etc). Setting a MAC address on l2switchaddr will add
a MAC in device-tree, under node l2switch.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Cc:
In the current Datasheet for VSC8514 there is a mistake, saying that
the PHY id is 0x70570. The real value in the identifier registers is
0x70670. Linux PHY driver uses 0x70670 also.
Signed-off-by: Codrin Ciubotariu codrin.ciubota...@freescale.com
Cc: York Sun york...@freescale.com
---
Ok, I've found my error
I don't used FTP in binary mode when I download file in filesystem.
Sorry, for the disruption.
Sophie
--
View this message in context:
http://u-boot.10912.n7.nabble.com/Load-kernel-from-JFFS2-Bad-Data-CRC-tp176605p176610.html
Sent from the U-Boot mailing list
This series adds a driver for TPS65090 and plumbs it in to get the LCD
working correctly on snow.
The display driver is already present, but needs information about the
display to be provided in the device tree.
The backlight also needs to be enabled - it is controlled by a FET on
the TPS65090.
At present the GPIO numbering patch has not been applied, so exynos GPIO
numbering is inconsistent (there are large gaps). Disable interrupts to
avoid a crash on boot.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5250-snow.dts | 12 ++--
1 file changed, 10
Commit be3b51aa did this mostly, but several have been added since. Do the
job again.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/power/power_fsl.c | 6 +++---
include/configs/arndale.h | 4 ++--
include/configs/exynos5250-dt.h | 2 +-
include/configs/mx25pdk.h
From: Aaron Durbin adur...@chromium.org
The TSP65090 is a PMIC on some exynos5 boards. The init function is
called for the TPS65090 pmic. If that device is not a part of the device
tree (returns -ENODEV) then continue. Otherwise return a failure.
Signed-off-by: Aaron Durbin adur...@chromium.org
Enable LCD for snow. This is a 1366 x 768 panel.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/arm/dts/exynos5250-snow.dts | 44
1 file changed, 44 insertions(+)
diff --git a/arch/arm/dts/exynos5250-snow.dts b/arch/arm/dts/exynos5250-snow.dts
There is quite a tight deadline in enabling PSHOLD, less than a second.
In some cases (e.g. with USB download), U-Boot takes longer than that
to load, so the board powers off before U-Boot starts.
Add a call in SPL to enable PSHOLD.
Signed-off-by: Simon Glass s...@chromium.org
---
The backlight uses FETs on the TPS65090. Enable this so that the display
is visible.
Signed-off-by: Simon Glass s...@chromium.org
---
board/samsung/smdk5250/exynos5-dt.c | 90 +
1 file changed, 90 insertions(+)
diff --git
From: Tom Wai-Hong Tam waih...@chromium.org
This adds driver support for the TPS65090 PMU. Support includes
hooking into the pmic infrastructure so that the pmic commands
can be used on the console. The TPS65090 supports the following
functionality:
- fet enable/disable/querying
- getting and
Add the ability to display the code offset of an initcall even after it
is relocated. This makes it much easier to relate initcalls back to the
U-Boot System.map file.
Signed-off-by: Simon Glass s...@chromium.org
---
include/initcall.h | 2 +-
lib/initcall.c | 17 -
2 files
From: Aaron Durbin adur...@chromium.org
The TPS65090 pmic chip can be on exynos5250 boards. Therefore,
select the appropriate config option for TPS65090 devices.
This commit should really use exynos5-dt.c, when it is available.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Simon
From: Aaron Durbin adur...@chromium.org
The current pmic i2c code assumes the current i2c bus is
the same as the pmic device's bus. There is nothing ensuring
that to be true. Therefore, select the proper bus before performing
a transaction.
Signed-off-by: Aaron Durbin adur...@chromium.org
On 03/26/2014 06:01 AM, Przemyslaw Marczak wrote:
Hello Stephen,
On 03/25/2014 08:37 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Those commands basis on implementation of random UUID generator
version 4
which is described in RFC4122. The same algorithm is
this board is produced by Embest/Element 14 and is based on i.MX6 Dual
The following features are tested :
- UART2 (console)
- eMMC
- uSDCard
- Ethernet
- USB Host (through 2 ports hub)
- HDMI output
- I2C 1/2
- SPI NOR Flash
Boot on SPI NOR and through USB loader are tested.
For more
On 03/26/2014 06:01 AM, Przemyslaw Marczak wrote:
On 03/25/2014 08:51 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Changes:
- randomly generate partition uuid if any is undefined and
CONFIG_RAND_UUID
is defined
- print debug info about set/unset/generated
On 03/26/2014 06:00 AM, Przemyslaw Marczak wrote:
Hello Stephen,
Thanks for review again:)
On 03/25/2014 08:12 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
Changes in lib/uuid.c to:
- uuid_str_to_bin()
- uuid_bin_to_str()
New parameter is added to specify
On 03/26/2014 06:00 AM, Przemyslaw Marczak wrote:
On 03/25/2014 08:28 PM, Stephen Warren wrote:
On 03/19/2014 11:58 AM, Przemyslaw Marczak wrote:
This patch adds support to generate UUID (Universally Unique Identifier)
in version 4 based on RFC4122, which is randomly.
Source:
this board is produced by Embest/Element 14 and is based on i.MX6 Solo
The following features are tested :
- UART2 (console)
- eMMC
- SDCard
- uSDCard
- Ethernet
- USB Host (through 4 ports hub)
- HDMI output
- I2C 1/2/3
Boot on eMMC and through USB loader are tested.
For more informations on
Dear Eric,
In message 1395858363-21054-2-git-send-email-e...@eukrea.com you wrote:
this board is produced by Embest/Element 14 and is based on i.MX6 Dual
Comparing this patch agains the earlier one for the RiOTboard, it
turns out that the differences between these two boards are really
Hi Wolfgang,
Le Wed, 26 Mar 2014 20:02:57 +0100,
Wolfgang Denk w...@denx.de a écrit :
In message 1395858363-21054-2-git-send-email-e...@eukrea.com you wrote:
this board is produced by Embest/Element 14 and is based on i.MX6 Dual
Comparing this patch agains the earlier one for the
-Original Message-
From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
Sent: Sunday, March 23, 2014 7:07 AM
To: Karicheri, Muralidharan
Cc: Rini, Tom; u-boot@lists.denx.de; Chang, Rex
Subject: Re: [U-Boot] [PATCH v3 8/9] spi: davinci: add support for multiple
bus and chip
select
Hi,
On
On 03/21/2014 03:27 PM, Tom Warren wrote:
I've updated u-boot-tegra/next with this patch, rebased it against ARM
master, and pushed it to Denx. All tegra boards build OK.
Albert - if you want, you can use u-boot-tegra/next to bring in this patch,
or apply it to ARM master yourself, or I
On 03/21/2014 01:21 AM, Zhao Qiang wrote:
Add u-qe support for t1040qds
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Changes for v2:
- modify CONFIG_SYS_QE_FMAN_FW_ADDR to CONFIG_SYS_FMAN_FW_ADDR and
CONFIG_SYS_QE_FW_ADDR
Changes for v3:
- use CONFIG_U_QE instead of
On 03/26/2014 02:59 PM, Tom Warren wrote:
I'll fix it on application. Pinmux changes and this patch should be in/tested
late today, and if it looks good to you I'll issue a PR to Albert.
Aren't you only sending ARM: tegra: make all I2C ports open-drain for
2014.04? I was assuming the other
this board is produced by Embest/Element 14 and is based on i.MX6 Dual
The following features are tested :
- UART2 (console)
- eMMC
- uSDCard
- Ethernet
- USB Host (through 2 ports hub)
- HDMI output
- I2C 1/2
- SPI NOR Flash
Boot on SPI NOR and through USB loader are tested.
For more
this board is produced by Embest/Element 14 and is based on i.MX6 Solo
The following features are tested :
- UART2 (console)
- eMMC
- SDCard
- uSDCard
- Ethernet
- USB Host (through 4 ports hub)
- HDMI output
- I2C 1/2/3
Boot on eMMC and through USB loader are tested.
For more informations on
Albert,
Please pull u-boot-tegra/master into ARM/master. Thanks!
./MAKEALL -s tegra AOK, checkpatch.pl is clean, and ./MAKEALL -a arm only
shows failures that were already present in ARM/master.
The following changes since commit ab6423cae0323e8db2c8fdd0a99138d93fde2137:
Merge branch
Hi Tom,
Stephen Warren (1):
ARM: tegra: make all I2C ports open-drain
board/nvidia/dalmore/pinmux-config-dalmore.h | 16
board/nvidia/venice2/pinmux-config-venice2.h | 16
2 files changed, 16 insertions(+), 16 deletions(-)
Is there something
The value written to L2CSR1 didn't match the value written to the
device tree.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/cpu/mpc85xx/fdt.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c
On Wed, Mar 26, 2014 at 6:31 PM, Eric Bénard e...@eukrea.com wrote:
this board is produced by Embest/Element 14 and is based on i.MX6 Dual
The following features are tested :
- UART2 (console)
- eMMC
- uSDCard
- Ethernet
- USB Host (through 2 ports hub)
- HDMI output
- I2C 1/2
- SPI NOR
Dear Otavio,
In message CAP9ODKrj9as+R7gb-STCnqpoSGFdKg_diJ=p+vg6htoka5d...@mail.gmail.com
you wrote:
I understand both boards share a lot of code but I think the set of
ifdef makes harder for people to understand the board code. Personally
I prefer v1.
Duplication of so much code is really
Dear Fabio Estevam,
In message caomzo5d2n1zvo5ogeam1_ewt-0kkamzgvrfpeekh5zymqkl...@mail.gmail.com
you wrote:
Me too. I also think the ifdefs may easily cause confusion.
So you suggest we remove all conditional code and use duplication
everywhere? You must be joking...
For example: if
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