Am 2014-07-31 23:55, schrieb Simon Glass:
Hi Stefan,
On 31 July 2014 19:00, Stefan Agner ste...@agner.ch wrote:
Hi Simon,
Am 2014-07-31 19:41, schrieb Simon Glass:
Hi Stefan,
On 31 July 2014 18:36, Stefan Agner ste...@agner.ch wrote:
This adds board support for the Toradex Colibri T30
Am 2014-07-31 20:21, schrieb Stephen Warren:
On 07/31/2014 11:36 AM, Stefan Agner wrote:
This adds board support for the Toradex Colibri T30 module.
Working functions:
- SD card boot
- eMMC environment and boot
- USB host/USB client (on the dual role port)
- Network (via ASIX USB)
This adds a fixed mode hdmi driver (lcd to be added in future) for the
sunxi platform. Current config is such that 8MB is shaved off at the top
of the RAM. Simplefb support is available for kernels that know how to
use it.
Signed-off-by: Luc Verhaegen l...@skynet.be
---
Enable Android Fastboot support on am335x_evm board
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
include/configs/am335x_evm.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 35ae0e6..3999405
Flash command uses DFU, and Fastboot command initialization is modified to add
DFU and partition initialization
Added oem format functionality for GPT table creation
partitioning code is added as disk/part_fastboot.c for better usability
Fastboot flash command code is enabled and being tested on
Hello Dileep,
On 02-08-14 20:30, Dileep Katta wrote:
Flash command uses DFU, and Fastboot command initialization is modified to add
DFU and partition initialization
Added oem format functionality for GPT table creation
partitioning code is added as disk/part_fastboot.c for better usability
Am 01.08.2014 14:08, schrieb Wolfgang Denk:
Dear Alexander Holler,
In message 1405352998-7707-2-git-send-email-hol...@ahsoftware.de you wrote:
When this option is enabled, CRLF is treated like LF when importing environments
from text files, which means CRs ('\r') in front of LFs ('\n') are
Hello Dileep,
On 02-08-14 21:10, Jeroen Hofstee wrote:
Hello Dileep,
On 02-08-14 20:30, Dileep Katta wrote:
Flash command uses DFU, and Fastboot command initialization is
modified to add DFU and partition initialization
Added oem format functionality for GPT table creation
partitioning code
Hi Jeroen,
On 3 August 2014 02:43, Jeroen Hofstee dasub...@myspectrum.nl wrote:
Hello Dileep,
On 02-08-14 21:10, Jeroen Hofstee wrote:
Hello Dileep,
On 02-08-14 20:30, Dileep Katta wrote:
Flash command uses DFU, and Fastboot command initialization is modified
to add DFU and partition
This is version 2 of
http://lists.denx.de/pipermail/u-boot/2014-July/183981.html
Rebased on git://git.denx.de/u-boot-sunxi.git master branch (commit
3340eab26d89176dd0bf543e6d2590665c577423 sun7i: Add bananapi board)
Siarhei Siamashka (16):
sunxi: dram: Remove useless
We can safely remove it, because none of the currently supported
boards uses these features.
The existing implementation had multiple problems:
- unnecessary code duplication between sun4i/sun5i/sun7i
- ZQ calibration was never initiated explicitly, and could be
only triggered by
The RESET pin needs to be kept low for at least 200 us according
to the DDR3 spec. So just do it the right way.
This issue did not cause any visible major problems earlier, because
the DRAM RESET pin is usually already low after the board reset. And
the time gap before reaching the sunxi u-boot
If the dram-ppwrsctl (SDR_DPCR) register has the lowest bit set to 1,
this means that DRAM is currently in self-refresh mode and retaining the
old data. Since we have no idea what to do in this situation yet, just
set this register to 0 and initialize DRAM in the same way as on any
normal reboot
The attempt to do DRAM parameters calibration in 'dramc_scan_dll_para()'
function by trying different DLL adjustments and using the hardware
DQS gate training result as a feedback is a great source of inspiration,
but it just can't work properly the way it is implemented now. The fatal
problem of
The old 'await_completion' function is not sufficient, because
in some cases we want to wait for bits to be cleared, and in the
other cases we want to wait for bits to be set. So split the
'await_completion' into two new 'await_bits_clear' and
'await_bits_set' functions.
Signed-off-by: Siarhei
The stale error status should be cleared for all sun4i/sun5i/sun7i
hardware and not just for sun7i. Also there are two types of DQS
gate training errors (found no result and found more than one
possible result). Both are handled now.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
This configures the PLL5P clock frequency to something in the ballpark
of 1GHz and allows more choices for MBUS and G2D clock frequency
selection (using their own divisors). In particular, it enables the use
of 2/3 clock speed ratio between MBUS and DRAM.
Signed-off-by: Siarhei Siamashka
The DRAM controller allows to configure impedance either by using the
calibration against an external high precision 240 ohm resistor, or
by skipping the calibration and loading pre-defined data. The DRAM
controller register guide is available here:
The sun5i hardware (Allwinner A13) introduced configurable MBUS clock
speed. Allwinner A13 uses only 16-bit data bus width to connect the
external DRAM, which is halved compared to the 32-bit data bus of sun4i
(Allwinner A10), so it does not make much sense to clock a wider
internal bus at a very
The older differences were likely justified by the need to mitigate
the CKE delay timing violations on sun4i/sun5i. The CKE problem is
already resolved, so now we can use the sun7i variant of this code
everywhere.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
Before driving the CKE pin (Clock Enable) high, the DDR3 spec requires
to wait for additional 500 us after the RESET pin is de-asserted.
The DRAM controller takes care of this delay by itself, using a
configurable counter in the SDR_IDCR register. This works in the same
way on sun4i/sun5i/sun7i
It is going to be useful in more than one place.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Changes for v2:
- remove DRAM_DCR_NR_DLLCR_32BIT/DRAM_DCR_NR_DLLCR_16BIT/
DRAM_DCR_NR_DLLCR_8BIT macros
- handle only 4 and 2 lanes (32-bit and 16-bit bus width), just like
All the known Allwinner A10/A13/A20 devices are using just single rank
DDR3 memory. So don't pretend that we support DDR2 or more than one
rank, because nobody could ever test these configurations for real and
they are likely broken. Support for these features can be added back
in the case if such
The write recovery time is 15ns for all JEDEC DDR3 speed bins. And
instead of hardcoding it to 10 cycles, it is possible to set tighter
timings based on accurate calculations. For example, DRAM clock
frequencies up to 533MHz need only 8 cycles for write recovery.
Signed-off-by: Siarhei Siamashka
The hardware DQS gate training is a bit unreliable and does not
always find the best delay settings.
So we introduce a 32-bit 'dqs_gating_delay' variable, where each
byte encodes the DQS gating delay for each byte lane. The delay
granularity is 1/4 cycle.
Also we allow to enable the active DQS
In the case if the 'dram_para' struct does not specify the exact bus
width or chip density, just use a trial and error method to find a
usable configuration.
Because all the major bugs in the DRAM initialization sequence are
now hopefully fixed, it should be safe to re-initialize the DRAM
Unlike 9d195a546179bc732aba9eacccf0a9a3db591288, which had removed
the MIDR check against the white list of supported CPUs earlier,
now we introduce the black list of unsupported CPUs.
The current PSCI code is not compatible with the Cortex-A8 CPU used
in Allwinner A10/A13 SoCs because of making
This patchset introduces the initial rudimentary support for having
just a single u-boot binary for certain subsets of Allwinner A10/A13/A20
devices.
== Example 1: All Allwinner A10/A13/A20 devices
We are restricted to only a very basic common subset of peripherals
(anything that is supported by
This is a purely mechanical conversion, replacing the ifdefs and
preparing the code for the use of runtime Allwinner SoC type
detection (within Allwinner A10/A13/A20 family).
Similar 'board_is_xxx()' calls are used for TI hardware.
Signed-off-by: Siarhei Siamashka siarhei.siamas...@gmail.com
---
Two new defconfigs ('sunxi-generic-a10-a13-a20_defconfig' and
'sunxi-generic-a10-a13-a20_FEL_defconfig') can be used to build
universal u-boot binaries, suitable for all Allwinner
A10/A13/A20 devices. The supported peripherals are just UART
and MMC (the lowest common denominator approach).
MMC
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