Define USB configs for LS1021XA such as CONFIG_SYS_FSL_USB1_ADDR,
CONFIG_USB_MAX_CONTROLLER_COUNT
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 4
include/usb/ehci-fsl.h | 3 +++
2 files changed, 7 insertions(+)
Enable USB EHCI Host on LS1021AQDS
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
include/configs/ls1021aqds.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index bb47813..fd43a3e 100644
---
SCFG_SCFGREVCR is SCFG bit reverse register. This register
must be written with 0x before writing to any other
SCFG register. Then other SCFG register could be written in
big-endian mode.
Address: 157_h base + 200h offset = 157_0200h
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15|16 17
From: Jason Jin jason@freescale.com
Disable the snoop for slave interface 0, 1 and 2
to avoid the interleaving on the CCI400 BUS.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
Change log:
v2: Add tag arm: ls102xa: in the
From: Yuan Yao yao.y...@freescale.com
Add define CONFIG_SYS_WRITE_SWAPPED_DATA.
For LS1021AQDS and LS1021QTWR nor flash write should swap the
bytes when handle unaligned tail bytes.
Because of the ending, if the date bus width is 16-bits and the
number of bytes is odd, we should swap the byte
EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or
SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1
as other functionality except RGMII. The workaround is to select
ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR.
Signed-off-by: Alison Wang
SystemID information could be read through I2C1 from EEPROM
on LS1021ATWR board.
As LS1 is a little-endian processor, getting the version ID by
be32_to_cpu() is wrong. Fix it by using e.version directly.
This change will be compatible for both ARM and PowerPC.
As there is an errata that I2C1
This series contain SD boot support for LS1021AQDS/TWR board
and NAND boot support for LS1021AQDS board.SPL framework is
used. PBL initialize the internal RAM and copy SPL to it,
then SPL initialize DDR using SPD and copy u-boot from SD
card or NAND flash to DDR, finally SPL transfer control to
This patch adds SD boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Alison Wang alison.w...@freescale.com
In SD boot, the magic number of u-boot image will be checked.
For LS102xA, u-boot.bin doesn't have the magic number. So use
u-boot.img which includes the magic number instead of u-boot.bin
when producing u-boot-with-spl-pbl.bin.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
On LS1, DDR is initialized by reading SPD through I2C interface
in SPL code. For I2C, ll_entry_count() is called, and it returns
the number of elements of a linker-generated array placed into
subsection of .u_boot_list section specified by _list argument.
So add I2C linker list in the generic .lds
For LS102xA, the size of spl/u-boot-spl.bin is variable.
This patch adds the support to deal with the variable
u-boot size in pblimage tool. It will be padded to 64
byte boundary.
Use pblimage_check_params() to add the specific operations
for ARM, such as PBI CRC and END command and the
Through adding CONFIG_QIXIS_I2C_ACCESS macro,
QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used
for both i2c and ifc access to QIXIS FPGA. This is
more convenient for coding.
Signed-off-by: Jason Jin jason@freescale.com
Signed-off-by: Alison Wang alison.w...@freescale.com
---
Change log:
To support interactive DDR debugger, cli_simple.o, cli.o, cli_readline.o,
command.o, s_record.o, xyzModem.o and cmd_disk.o are all needed for
drivers/ddr/fsl/interactive.c.
In current common/Makefile, the above .o files are only produced when
CONFIG_SPL_BUILD is disabled.
For LS102xA,
This patch adds SD boot support for LS1021ATWR board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from SD card to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Chen Lu chen...@freescale.com
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
include/configs/P1023RDB.h | 43 +++
1 files changed, 43 insertions(+), 0 deletions(-)
diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h
index ba3da06..6b29add 100644
---
Hi, Suriyan.
This patch can be separated.
On 10/02/2014 10:45 PM, Suriyan Ramasami wrote:
This change adds support for enabling the USB host features of the board.
This includes the USB3503A hub and the SMC LAN9730 ethernet controller
as well.
Credit goes to Tushar Behera (Linaro) for the
Hi,
does anyone has tried eMMC boot on Arndale board?
I copied BL1, SPL and u-boot to eMMC, like I do on SD card but it does not boot
at all.
Note that once booted on SD card, I get some errors while accessing eMMC.
mmc dev 0 returns:
dwmci_send_cmd: DATA ERROR!
switch to
On Fri, 2014-10-17 at 12:20 +0200, Guillaume Gardet wrote:
Hi,
does anyone has tried eMMC boot on Arndale board?
Other than the image which was in mine when it arrived, no, I've only
booted from the removable SD/MMC device.
Note that once booted on SD card, I get some errors while accessing
Hi
On Fri, Oct 17, 2014 at 1:11 PM, Ian Campbell i...@hellion.org.uk wrote:
On Fri, 2014-10-17 at 12:20 +0200, Guillaume Gardet wrote:
Hi,
does anyone has tried eMMC boot on Arndale board?
Other than the image which was in mine when it arrived, no, I've only
booted from the removable
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
board/freescale/t208xqds/README | 243
1 file changed, 243 insertions(+)
create mode 100755 board/freescale/t208xqds/README
diff --git a/board/freescale/t208xqds/README
On Fri, 17 Oct 2014 12:20:44 +0200
Guillaume Gardet guillaume.gar...@free.fr wrote:
Hi,
does anyone has tried eMMC boot on Arndale board?
I copied BL1, SPL and u-boot to eMMC, like I do on SD card but it does not
boot at all.
Note that once booted on SD card, I get some errors while
On Friday, October 17, 2014 at 01:27:10 AM, Fabio Estevam wrote:
On Thu, Oct 16, 2014 at 8:02 PM, Marek Vasut ma...@denx.de wrote:
So this discussion is related to a different thread ? I see ...
We are talking about the need for the delay in the Ethernet PHY.
Nikolay sent a patch adding
Hi Ian,
On Mon, Oct 13, 2014 at 8:57 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell i...@hellion.org.uk wrote:
On Tue, 2014-10-07 at 15:11 +0800, Chen-Yu Tsai wrote:
From:
Hi,
it was a pleasure for me to meet so many of you this Monday in
Düsseldorf at the ELCE. As many as 17 current custodians and 2
prospective new custodians were present at the event:
Hans de Goede - Sunxi
Alexey Brodkin - ARC
Marek Vasut - USB
Scott Wood - NAND
Joe Hershberger -
Hello,
On Thu, Oct 16, 2014 at 7:17 PM, Marek Vasut ma...@denx.de wrote:
On Thursday, October 16, 2014 at 08:24:21 PM, Otavio Salvador wrote:
Hello,
On Wed, Sep 3, 2014 at 6:25 AM, Marek Vasut ma...@denx.de wrote:
On Wednesday, September 03, 2014 at 03:44:35 AM, Otavio Salvador wrote:
On
On Friday, October 17, 2014 at 05:35:58 PM, Otavio Salvador wrote:
Hello,
[...]
I have looked at this and I am unsure I still think removing it is a
good idea. I think the way to go is to change CONFIG_MXS to
CONFIG_MXSIMAGE and enable this in sandbox defconfig. What you think?
We would
On 10/17/2014 01:24 AM, Chunhe Lan wrote:
Signed-off-by: Chunhe Lan chunhe@freescale.com
---
A little bit more information in commit message will help us search for this
patch later.
York
___
U-Boot mailing list
U-Boot@lists.denx.de
Hi Rob:
THANKS!
On 14-10-15 08:19 PM, Rob Herring wrote:
From: Rob Herring r...@kernel.org
CHUNK_TYPE_DONT_CARE should skip over the specified number of blocks, but
currently fails to increment the device block address. This results in
filesystem images getting written incorrectly. Add the
Add soc specific drivers directory like in the Linux kernel.
It is going to be used by keysotone soc specific drivers.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/Makefile | 2 ++
drivers/soc/Makefile | 3 +++
2 files changed, 5 insertions(+)
create mode 100644
This patch split the Keystone II SGMII SerDes related code from
Ethernet driver and create a separate SGMII SerDes driver.
The SerDes driver can be used by others keystone subsystems
like PCI, sRIO, so move it to driver/soc/keystone directory.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by:
From: Hao Zhang hzh...@ti.com
SerDes driver is used by other sub systems like PCI, sRIO etc.
So modify it to be more general. The SerDes driver provides common
API's that can also be extended for other peripherals SerDes
configurations.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan
This patch series adds serdes driver, taking out it from
keystone_net driver.
v3..v1:
- just rebase.
Hao Zhang (2):
soc: keystone_serdes: enhance to use cmu/comlane/lane specific
configurations
soc: keystone_serdes: generalize to be used by other sub systems
Ivan Khoronzhuk (3):
From: Hao Zhang hzh...@ti.com
Enhance the driver to use cmu/comlane/lane specific configurations
instead of 1 big array of configuration.
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2hk.h | 3 +
The cmu, comlane, lane configuration mechanism are similar for sub
systems as well such as PCI or sRIO, but they have different values
based on input clock and output bus rate. According to this compact
driver to simplify adding different configuration settings based
on clock and rate.
This patch series optimize keystone_net driver to use MDIO bus and
eht PHY frameworks.
Based on
[U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver
https://www.mail-archive.com/u-boot@lists.denx.de/msg148694.html
v2..v1
net: keystone_net: register eth PHYs on MDIO bus
- add
Don't use mdio_enable twice while eth open. Also rename it to
keystone2_mdio_reset as more appropriate name.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/keystone_net.c | 16 ++--
1 file changed, 2 insertions(+), 14
In case when several Ethernet ports are supported it's
convenient to see the number of phy that is not found.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
drivers/net/phy/phy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
The phy framework has function to get link, so use it
instead of own implementation.
There is no reason to check SGMII link while sending each
packet, phy link is enough. Check SGMII link only while
ethernet open.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk
As MDIO bus has been added we can register PHYs with it.
After registration, the PHY driver will be probed according to the
hardware on board.
Startup PHY at the ethernet open.
Use phy_startup() instead of keystone_get_link_status() when eth open,
as it verifies PHY link inside and SGMII link is
Currently MDIO framework is not used to configure Ethernet PHY.
As result some of already implemented functions are duplicated.
So register MDIO bus in order to use it. On that stage it's just
registered, it'll be used as we start to use PHY framework.
Use mdio bus read/write/reset functions in
Hi Akshay,
On 15 October 2014 18:38, Akshay Saraswat aksha...@samsung.com wrote:
Now we are adding a new Peach-Pi board which is a variant of Peach-Pit
and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420,
hence, most of the hardware config and settings are reused for this
On 16 October 2014 16:58, Bin Meng bmeng...@gmail.com wrote:
When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking
On 16 October 2014 16:58, Bin Meng bmeng...@gmail.com wrote:
GDT limit should be one less than an integral multiple of eight.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing list
These patches add network support for Keystne2 Edison SoC boards.
Based on
[U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks
http://patchwork.ozlabs.org/patch/322289/
v2..v1
ARM: keystone: clock: add support for K2E SoCs
- firstly added
Hao Zhang (1):
board:
Keystone2 Edison SoC uses the same keystone navigator, but
uses different NETCP PktDMA definitions. This patch adds
required definitions.
Acked-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
The new Marvel PHY (88E1514) used on K2L/K2E EVM requires longer time
to auto negotiate with SoC's SGMII port.
It can take about 3 sec to up the PHY after reset, so add code to
expose sgmii auto negotiation waiting process.
Acked-by: Vitaly Andrianov vita...@ti.com
Signed-off-by: Ivan Khoronzhuk
The Keystone2 Edison SoC uses the same keystone net driver.
This patch adds opportunity to use it by K2E SoCs.
Acked-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
For K2E and K2L SoCs clock output from PASS PLL has to be enabled
after NETCP domain and PA module are enabled. So create new function
for that and call it after PA module is enabled.
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/cpu/armv7/keystone/clock.c| 17
From: Hao Zhang hzh...@ti.com
This patch adds network support code and enables keystone_net
driver usage for k2e_evm evaluation board.
Acked-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Hao Zhang hzh...@ti.com
Signed-off-by: Ivan Khoronzhuk
Keystone2 Edison SoC uses the same keystone SerDes driver.
This patch adds support for K2E SoCs.
Acked-by: Vitaly Andrianov vita...@ti.com
Acked-by: Murali Karicheri m-kariche...@ti.com
Signed-off-by: Ivan Khoronzhuk ivan.khoronz...@ti.com
---
arch/arm/include/asm/arch-keystone/hardware-k2e.h |
On 10/17/2014 08:38 PM, Ivan Khoronzhuk wrote:
This patch series adds serdes driver, taking out it from
keystone_net driver.
v3..v1:
- just rebase.
is based on [U-boot] [Patch v2 0/5] keystone2: generalize keystone_net
driver usage
On 10/17/2014 10:00 PM, Ivan Khoronzhuk wrote:
On 10/17/2014 08:38 PM, Ivan Khoronzhuk wrote:
This patch series adds serdes driver, taking out it from
keystone_net driver.
v3..v1:
- just rebase.
is based on [U-boot] [Patch v2 0/5] keystone2: generalize
keystone_net driver usage
On 10/17/2014 08:44 PM, Ivan Khoronzhuk wrote:
This patch series optimize keystone_net driver to use MDIO bus and
eht PHY frameworks.
Based on
[U-boot] [Patch v3 0/5] keystone2: serdes: add seredes driver
https://www.mail-archive.com/u-boot@lists.denx.de/msg148694.html
link update
Hello Jaehoon,
On Fri, Oct 17, 2014 at 1:52 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi, Suriyan.
This patch can be separated.
OK, I shall separate out the power.c/power.h changes for enabling and
disabling the usbhost phy.
On 10/02/2014 10:45 PM, Suriyan Ramasami wrote:
This
On 10/17/2014 09:01 PM, Ivan Khoronzhuk wrote:
These patches add network support for Keystne2 Edison SoC boards.
Based on
[U-boot] [Patch v2 0/5] keystone_net: use MDIO bus and eth PHY frameworks
http://patchwork.ozlabs.org/patch/322289/
link update
On 10/17/2014 01:52 AM, Ivan Khoronzhuk wrote:
This series adds the DDR3 ECC support to enable ECC in the DDR3
EMIF controller for Keystone II devices.
Based on
[U-boot] [Patch 0/5] keystone2: add network support for K2E SoC and EVM
Hello Simon,
On Thu, Oct 9, 2014 at 8:42 AM, Simon Glass s...@chromium.org wrote:
+Tom for the question below re return values
Hi,
On 8 October 2014 15:54, Suriyan Ramasami suriya...@gmail.com wrote:
On Wed, Oct 8, 2014 at 1:44 PM, Simon Glass s...@chromium.org wrote:
Hi Suriyan,
On
Hi Suriyan,
On 17 October 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
Hello Simon,
On Thu, Oct 9, 2014 at 8:42 AM, Simon Glass s...@chromium.org wrote:
+Tom for the question below re return values
Hi,
On 8 October 2014 15:54, Suriyan Ramasami suriya...@gmail.com wrote:
On
Hi Alban,
On 15 October 2014 03:42, Alban Bedel alban.be...@avionic-design.de wrote:
On Tue, 14 Oct 2014 21:18:37 +0200
Simon Glass s...@chromium.org wrote:
Hi Joe,
On 14 October 2014 21:14, Joe Hershberger joe.hershber...@gmail.com wrote:
On Tue, Oct 14, 2014 at 12:21 PM, Simon Glass
Hi,
On 16 October 2014 22:52, Ahmad Draidi ar200...@gmail.com wrote:
This patch makes the following changes:
- Set kernel entry point correctly
- Append bootargs from image to global bootargs instead
of replacing them
- Return end address instead of size from android_image_get_end()
Hi Simon,
some comments on return values and error reporting below:
On Wed, 15 Oct 2014 02:05:31 -0600
Simon Glass s...@chromium.org wrote:
...
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 53f9b34..afac3f9 100644
--- a/board/amcc/sequoia/sequoia.c
+++
Hi Simon,
On Wed, 15 Oct 2014 02:05:32 -0600
Simon Glass s...@chromium.org wrote:
...
+ else if (strncmp(argv[1], boa, 3) == 0) {
+ int err = ft_board_setup(working_fdt, gd-bd);
+
+ if (err) {
+ printf(Failed to add board information to FDT:
Commit 951860634fdb557bbb58e0f99215391bc0c29779 may have changed
the logic unintentially from if (!(swfw_sync (fwmask | swmask)))
to if ((swfw_sync swmask) !(swfw_sync fwmask)). This change
breaks some e1000 NIC with a message ERROR: Unable to read EEPROM!.
Signed-off-by: York Sun
Hi Simon,
On Wed, 15 Oct 2014 02:05:33 -0600
Simon Glass s...@chromium.org wrote:
...
diff --git a/common/fdt_support.c b/common/fdt_support.c
index 3f64156..dc41222 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -112,17 +112,7 @@ int fdt_find_and_setprop(void *fdt, const
On Wed, 15 Oct 2014 02:05:36 -0600
Simon Glass s...@chromium.org wrote:
Flash regions can optionally be compressed or hashed. Add the ability to
read this information from the flashmap.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 16
On Wed, 15 Oct 2014 02:05:35 -0600
Simon Glass s...@chromium.org wrote:
Use the correct FDT data types for this function. Also add more debugging.
Signed-off-by: Simon Glass s...@chromium.org
---
include/fdtdec.h | 10 +-
lib/fdtdec.c | 19 ---
2 files
On Wed, 15 Oct 2014 02:05:39 -0600
Simon Glass s...@chromium.org wrote:
This function is only called within this file so make it static. Also
fix its argument types to be consistent with its caller.
Signed-off-by: Simon Glass s...@chromium.org
---
common/fdt_support.c | 4 ++--
1 file
Hi Simon,
On Wed, 15 Oct 2014 02:05:38 -0600
Simon Glass s...@chromium.org wrote:
Add an additional function for adding information to the device tree before
booting. This permits additions which are not board-specific.
Signed-off-by: Simon Glass s...@chromium.org
---
README
On Friday, October 17, 2014 at 10:44:06 PM, York Sun wrote:
Commit 951860634fdb557bbb58e0f99215391bc0c29779 may have changed
the logic unintentially from if (!(swfw_sync (fwmask | swmask)))
to if ((swfw_sync swmask) !(swfw_sync fwmask)). This change
breaks some e1000 NIC with a message
On 09/30/2014 07:41 PM, Stephen Warren wrote:
On 09/22/2014 05:30 PM, Simon Glass wrote:
This series adds driver model support to the GPIO and serial drivers used
by Raspberry Pi, and moves Raspberry Pi over to driver model.
This requires adding driver model support to the pl01x serial
Hi Akshay,
On 17 October 2014 11:52, Simon Glass s...@chromium.org wrote:
Hi Akshay,
On 15 October 2014 18:38, Akshay Saraswat aksha...@samsung.com wrote:
Now we are adding a new Peach-Pi board which is a variant of Peach-Pit
and is based on Exynos5800. Exynos5800 itself is a variant of
Hello Mr. Glass
On Fri, Oct 17, 2014 at 11:19 PM, Simon Glass s...@chromium.org wrote:
Hi,
On 16 October 2014 22:52, Ahmad Draidi ar200...@gmail.com wrote:
This patch makes the following changes:
- Set kernel entry point correctly
- Append bootargs from image to global bootargs instead
74 matches
Mail list logo
