Now that we have inttypes.h, use it in a few more places to avoid compiler
warnings on sandbox when building on 64-bit machines.
Signed-off-by: Simon Glass s...@chromium.org
---
common/cmd_mem.c | 6 --
common/fdt_support.c | 15 +++
disk/part_efi.c | 21
On Tue, Nov 11, 2014 at 11:22:43AM +0100, Michal Simek wrote:
Hi Tom, [cc: Albert]
please pull these 4 patches to your tree.
It adds support for Zybo board and add support for new ps7_init_gpl file.
Thanks,
Michal
The following changes since commit
On Wed, Nov 12, 2014 at 12:46:21AM +0900, Masahiro YAMADA wrote:
Hi Tom,
The following changes since commit 9906090f527153afddc5aa64d37cb5f89c6ee129:
Prepare v2015.01-rc1 (2014-11-10 16:25:29 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-uniphier.git
On Tue, Nov 11, 2014 at 03:45:36PM +0100, Michal Simek wrote:
This reverts commit 1e96220a5687efae2aed45ce56e143336c40d0a7.
Remove duplicated vxworks.h header.
The same change was done by
ARM: prevent compiler warnings from bootm.c
(sha1: 8d196e52b58d1e50a80c2f5067b201cda521c75c)
This is long lasting work that I did last few months back,
I'm sure it's where much need now.
- spi driver: drivers/spi/fsl_qspi.c
- flash attributes in spi_slave {} and
- etc ...
making spi subsystem becomes more flash specific rather operating
as a generic spi bus. So SF-NOR divides normal spi
From: Dinh Nguyen dingu...@opensource.altera.com
Set the PHY skew settings for the ethernet phy on the SOCFPGA devkit.
Signed-off-by: Dinh Nguyen dingu...@opensource.altera.com
Cc: Vince Bridgers vbrid...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Marek Vasut ma...@denx.de
Cc: Tom
On Tuesday, November 11, 2014 at 09:50:35 PM, Jagannadha Sutradharudu Teki
wrote:
This is long lasting work that I did last few months back,
I'm sure it's where much need now.
- spi driver: drivers/spi/fsl_qspi.c
- flash attributes in spi_slave {} and
- etc ...
making spi subsystem
On 12 November 2014 02:52, Marek Vasut ma...@denx.de wrote:
On Tuesday, November 11, 2014 at 09:50:35 PM, Jagannadha Sutradharudu Teki
wrote:
This is long lasting work that I did last few months back,
I'm sure it's where much need now.
- spi driver: drivers/spi/fsl_qspi.c
- flash attributes
On Mon, Nov 10, 2014 at 03:13:44PM -0700, Simon Glass wrote:
+Albert
Hi Tom,
On 16 September 2014 18:47, Tom Rini tr...@ti.com wrote:
On Tue, Sep 16, 2014 at 08:27:23PM -0400, Tom Rini wrote:
At the high level, the problem is that we set gd multiple times (and
still do, even
When saving binary files we likely want to keep any .img files that have
been generated as well.
Signed-off-by: Tom Rini tr...@ti.com
---
tools/buildman/builderthread.py |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/buildman/builderthread.py
add a build configuration file for mx6sabresd with spl support
Signed-off-by: John Tobias john.tobias...@gmail.com
---
configs/mx6sabresd_spl_defconfig | 5 +
1 file changed, 5 insertions(+)
create mode 100644 configs/mx6sabresd_spl_defconfig
diff --git a/configs/mx6sabresd_spl_defconfig
add SUPPORT_SPL feature for iMX6 SabreSD. It need to use
mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..ab0d284 100644
---
This patch is for SPL support for iMX6 SabreSD. The said
patches has been tested to work on SD2 and SD3 port of the
said board.
After applying the following patches, it will produces
SPL and u-boot.img binary images. You should run the
two commands below to store it in your SD or eMMC.
sudo dd
add the spl info in the header file.
It includes the stack address of iMX6Q which is 0x0093FFB8
Signed-off-by: John Tobias john.tobias...@gmail.com
---
include/configs/mx6sabresd.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/configs/mx6sabresd.h
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed
the related settings for DDR
Signed-off-by: John Tobias john.tobias...@gmail.com
---
board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 +++
1 file changed, 58 insertions(+)
create mode 100644
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
It uses mx6dq_dram_iocfg and mx6_dram_cfg for ddr configuration.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
board/freescale/mx6sabresd/mx6sabresd.c | 187 +++-
When the spl_mmc_load_image function being called, it will call
mmc_initialize function. By default, it will call board_mmc_init.
The main purpose of board_mmc_init (in practice) is to initialize
all the mmc ports defined by CONFIG_SYS_FSL_USDHC_NUM.
While, in spl_board_mmc_init, it read the
iMX6 SabreSD has a different stack address (0x0093FFB8) compare
to the default stack address defined in the file.
The CONFIG_SYS_TEXT_BASE is defined in mx6sabre_common.h.
It is better to add the #ifndef to avoid compilation
warnings.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
On Tuesday, November 11, 2014 at 10:37:33 PM, Jagan Teki wrote:
On 12 November 2014 02:52, Marek Vasut ma...@denx.de wrote:
On Tuesday, November 11, 2014 at 09:50:35 PM, Jagannadha Sutradharudu
Teki
wrote:
This is long lasting work that I did last few months back,
I'm sure it's where
On Tue, Nov 11, 2014 at 8:50 PM, John Tobias john.tobias...@gmail.com wrote:
iMX6 SabreSD has a different stack address (0x0093FFB8) compare
to the default stack address defined in the file.
Why you are using a different stack?
--
Otavio Salvador O.S. Systems
Hi Otavio,
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383).
While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
Regards,
john
On Tue, Nov 11, 2014 at 3:58 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
On Tue, Nov 11, 2014 at 8:50 PM, John Tobias
We have an ALIGN() macro - add a comment as to what this does. Also add a
new ALIGN_DOWN() macro, which aligns a value to the next smallest multiple.
Signed-off-by: Simon Glass s...@chromium.org
---
include/common.h | 15 +++
1 file changed, 15 insertions(+)
diff --git
This is not needed on x86 and creates a 4GB file due to the addressing used
on x86.
This needs to be investigated.
Signed-off-by: Simon Glass s...@chromium.org
---
Makefile | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index fb72c29..c54a2f1 100644
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/u-boot.lds | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
This series adds full support for the LPC (Low Pin Count) bridge, the
PCH (Platform Controller Hub), PCI devices like USB and SATA and more
CPU init support (turbo mode, etc.)
With this series, chromebook_link can use SATA and USB at the command
line.
Simon Glass (33):
Add build date values
At present there is a string for the build date and time. In the case of an
Real Time Clock which needs to be reset, it is useful to reset it to the
build date, since it can't be earlier than that.
Signed-off-by: Simon Glass s...@chromium.org
---
Makefile | 7 ++-
1 file changed, 6
Add simple init for the ISA DMA settings.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/isa_dma.h | 14 +++
arch/x86/lib/Makefile | 1 +
arch/x86/lib/isa_dma.c | 56 ++
3 files changed, 71 insertions(+)
Define the reset base in config.mk so that it does not need to be calculated
twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values
to fit with this new approach.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/config.mk | 5 +++--
arch/x86/cpu/u-boot.lds |
Device trees must be aligned to a 4-byte boundary. This was dropped in the
Kbuild conversion. Bring it back, and use 16-byte alignment for good
measure.
Signed-off-by: Simon Glass s...@chromium.org
---
scripts/Makefile.lib | 2 ++
1 file changed, 2 insertions(+)
diff --git
Some boards will want to do some setup before and after a PCI hose
is scanned.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/pci.c | 14 +-
arch/x86/include/asm/pci.h | 3 +++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/pci.c
This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/lib/relocate.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
Add code to set up the Local Advanced Peripheral Interrupt Controller.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/Makefile| 1 +
arch/x86/cpu/lapic.c | 68
arch/x86/include/asm/lapic.h | 123
Add definitions for the I/O Advanced Peripheral Interrupt Controller.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/ioapic.h | 38 ++
1 file changed, 38 insertions(+)
create mode 100644 arch/x86/include/asm/ioapic.h
diff --git
Enable this option so that we can configure the available PCI devices. Also
make sure that PCI is available early after relocation as we use it for
several other subsystems.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/chromebook_link.h | 3 +++
1 file changed, 3
Some PCI functions cannot be auto-configured. Add a function to set up a
fixed BAR which can be used in these situations. Also add a function to read
the current address of a BAR.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/pci/pci.c | 24 +---
include/pci.h
Add init for the northbridge, another part of the platform controller hub.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/bd82x6x.c | 2 +
arch/x86/cpu/ivybridge/northbridge.c |
Add init for XHCI so that high-speed USB can be used.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/usb_xhci.c | 32 +++
arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 1 +
3
The i8259 is a basic interrupt controller from the 1970s which is still
present in modern Intel hardware. Add some code to set it up.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/i8259.h | 3 +
arch/x86/lib/Makefile| 1 +
arch/x86/lib/i8259.c | 134
Add required init for the Intel Platform Controller Hub in ivybridge.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/pch.c | 123 ++
arch/x86/include/asm/arch-ivybridge/pch.h |
This was taken from Linux 3.18 with some additional IDs from Chrome OS
Coreboot commit 688ef385.
Signed-off-by: Simon Glass s...@chromium.org
---
include/pci_ids.h | 187 --
1 file changed, 181 insertions(+), 6 deletions(-)
diff --git
Add some settings required to set up the LPC correctly.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/dts/link.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
index 4520db5..28cef07 100644
--- a/arch/x86/dts/link.dts
+++
These peripherals should not be at the top level, since they exist inside
the PCI bus. We don't have a full device tree node for pci yet, but we
should at least put it at the right level.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/dts/link.dts | 28 +++-
1
We don't use many features yet, so this only has a few declarations.
It will be expanded as needed.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/acpi.h | 24
1 file changed, 24 insertions(+)
create mode 100644 arch/x86/include/asm/acpi.h
diff
Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/Makefile| 1 +
arch/x86/cpu/turbo.c | 98
Add code to set up the SATA interfaces on boot.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/bd82x6x.c | 20 +++
arch/x86/cpu/ivybridge/sata.c | 243 ++
Add init for EHCI so that USB can be used.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++
arch/x86/cpu/ivybridge/usb_ehci.c | 29 +++
Add the setup code for the CPU so that it can be used at full speed.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/bd82x6x.c | 6 +
arch/x86/cpu/ivybridge/model_206ax.c | 514
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/bd82x6x.c| 6 +
arch/x86/cpu/ivybridge/lpc.c| 529 +++-
These are not available in U-Boot as yet, so drop them.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/include/asm/msr.h | 11 ---
1 file changed, 11 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index df43983..1955a75 100644
---
Enable SPI so that the SPI flash can be used.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/chromebook_link.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index 86429cf..6b57b28 100644
---
Enable USB support on link - there are two EHCI ports available.
Signed-off-by: Simon Glass s...@chromium.org
---
include/configs/chromebook_link.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include/configs/chromebook_link.h
b/include/configs/chromebook_link.h
index e9efd7c..86429cf
Add the requires settings to enable SATA on link.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/dts/link.dts | 7 +++
include/configs/chromebook_link.h | 1 -
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/link.dts b/arch/x86/dts/link.dts
On 12 November 2014 04:26, Marek Vasut ma...@denx.de wrote:
On Tuesday, November 11, 2014 at 10:37:33 PM, Jagan Teki wrote:
On 12 November 2014 02:52, Marek Vasut ma...@denx.de wrote:
On Tuesday, November 11, 2014 at 09:50:35 PM, Jagannadha Sutradharudu
Teki
wrote:
This is long lasting
Add basic setup for the PCH.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/ivybridge/Makefile | 1 +
arch/x86/cpu/ivybridge/bd82x6x.c | 99 +++
arch/x86/cpu/ivybridge/pci.c | 40 +++
If the RTC needs to be cleared, write the U-Boot build date to it. In any
case make sure the settings are correct.
Signed-off-by: Simon Glass s...@chromium.org
---
drivers/rtc/mc146818.c | 49 +
include/rtc.h | 7 +++
2 files
This function is not needed. Remove it to improve the generic init sequence
slightly.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/coreboot/coreboot.c| 11 ---
board/google/chromebook_link/link.c | 5 -
common/board_r.c| 3 ---
Hi,
On 10 November 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
Change the internal fat functions to use loff_t for offsets.
Signed-off-by: Suriyan Ramasami suriya...@gmail.com
---
Changes in v7:
* Split it so that its bisectable.
A few bits below but with these fixed:
On 10 November 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
Change the internal ext4 functions to use loff_t for offsets.
Signed-off-by: Suriyan Ramasami suriya...@gmail.com
---
Changes in v7:
* Split it so that its bisectable.
Acked-by: Simon Glass s...@chromium.org
I'll see
On 10 November 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
Change the internal ext4 functions to use loff_t for offsets.
Signed-off-by: Suriyan Ramasami suriya...@gmail.com
Acked-by: Simon Glass s...@chromium.org
(BTW you could be more consistent with size, sz, file_size - choose
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias...@gmail.com wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383).
While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
I am worrying how Compulab and Gateworks are using SPL if it is wrong.
--
Otavio Salvador
On 10 November 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
The sandbox/ext4/fat/generic fs commands do not gracefully deal with file
greater than 2GB. Negative values are returned in such cases.
To handle this, the fs functions have been modified to take an additional
parameter of
On 10 November 2014 13:17, Suriyan Ramasami suriya...@gmail.com wrote:
Test size/read/write commands in a sandbox environment.
Signed-off-by: Suriyan Ramasami suriya...@gmail.com
---
Changes in v7:
* Simon
- take care of fat/vfat in mkfs
- fs/nonfs test code repeats, put it in
Hi Tom,
On 11 November 2014 14:57, Tom Rini tr...@ti.com wrote:
On Mon, Nov 10, 2014 at 03:13:44PM -0700, Simon Glass wrote:
+Albert
Hi Tom,
On 16 September 2014 18:47, Tom Rini tr...@ti.com wrote:
On Tue, Sep 16, 2014 at 08:27:23PM -0400, Tom Rini wrote:
At the high level, the
I think Gateworks is based on iMX6SDL.
On Tue, Nov 11, 2014 at 4:52 PM, Otavio Salvador
ota...@ossystems.com.br wrote:
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias...@gmail.com
wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383).
While, in iMX6SDL datasheet
On 11/11/2014 5:52 PM, Otavio Salvador wrote:
On Tue, Nov 11, 2014 at 10:15 PM, John Tobias john.tobias...@gmail.com
wrote:
In iMX6DQ data sheet the stack address is 0x0093FFB8 (page 383).
While, in iMX6SDL datasheet (page 393) is 0x0091FFB8.
I am worrying how Compulab and Gateworks are
Hi Bin,
On 11 November 2014 07:14, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will
On Tue, Nov 11, 2014 at 10:59 PM, Troy Kisky
troy.ki...@boundarydevices.com wrote:
iMX6SDL has 128KB OCRAM, 0x0090 - 0x0091
iMX6DQ has 256KB OCRAM, 0x0090 - 0x0093
So, if we want 1 image to support both, we should choose 0x0091FFB8.
Agreed.
John,
Can't you just use the
Dear Minkyu Kang,
On Tue, 11 Nov 2014 21:53:35 +0900
Minkyu Kang proms...@gmail.com wrote:
On 10 November 2014 10:41, Hyungwon Hwang human.hw...@samsung.com wrote:
This is v6 of the patchset adding support Odroud XU3 board.
link to the previous version:
v2:
This fixes this cppcheck report:
[drivers/misc/cros_ec.c:704]: (error) Uninitialized variable: req
Signed-off-by: Simon Glass s...@chromium.org
Reported-by: Wolfgang Denk w...@denx.de
---
drivers/misc/cros_ec.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/misc/cros_ec.c
I'll go ahead and use the same address.
Regards,
john
On Tue, Nov 11, 2014 at 5:02 PM, Fabio Estevam feste...@gmail.com wrote:
On Tue, Nov 11, 2014 at 10:59 PM, Troy Kisky
troy.ki...@boundarydevices.com wrote:
iMX6SDL has 128KB OCRAM, 0x0090 - 0x0091
iMX6DQ has 256KB OCRAM,
Hi Simon,
On Wed, Nov 12, 2014 at 12:10 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 01:25, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 2:54 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 9 November 2014 07:19, Bin Meng
Hi Simon,
On Wed, Nov 12, 2014 at 12:11 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 01:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
[snip]
+
Hi Simon,
On Wed, Nov 12, 2014 at 12:12 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 03:05, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We can use an MSR to obtain the time base. Add this back in
Hi Simon,
On Wed, Nov 12, 2014 at 12:15 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass s...@chromium.org wrote:
Many PCH devices are hard-coded to a particular PCI address.
Hi Simon,
On Wed, Nov 12, 2014 at 12:18 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
I am not sure if there is anything I missed but when I look at the
u-boot-x86/working, the repo content does not match the patch
Hi Simon,
On Wed, Nov 12, 2014 at 9:02 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:14, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass s...@chromium.org wrote:
We want access PCI earlier in the init sequence, so refactor
add SUPPORT_SPL feature for iMX6 SabreSD. It need to use
mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
arch/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 22eb2d5..ab0d284 100644
---
add the spl info in the header file.
Also, added the macro statement in m6sabre_common.h to avoid compiler
warning.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
include/configs/mx6sabre_common.h | 2 ++
include/configs/mx6sabresd.h | 6 ++
2 files changed, 8 insertions(+)
This patch is for SPL support for iMX6 SabreSD. The said
patches has been tested to work on SD2 and SD3 port of the
said board.
After applying the following patches, it will produces
SPL and u-boot.img binary images. You should run the
two commands below to store it in your SD or eMMC.
sudo dd
When the spl_mmc_load_image function being called, it will call
mmc_initialize function. By default, it will call board_mmc_init.
The main purpose of board_mmc_init (in practice) is to initialize
all the mmc ports defined by CONFIG_SYS_FSL_USDHC_NUM.
While, in spl_board_mmc_init, it will read
This patch will enable the support for SPL on iMX6 SabreSD.
It tested on SD2 and SD3 mmc port.
It uses mx6dq_dram_iocfg and mx6_dram_cfg for ddr configuration.
Signed-off-by: John Tobias john.tobias...@gmail.com
---
board/freescale/mx6sabresd/mx6sabresd.c | 187 +++-
add a build configuration file for mx6sabresd with spl support
Signed-off-by: John Tobias john.tobias...@gmail.com
---
configs/mx6sabresd_spl_defconfig | 5 +
1 file changed, 5 insertions(+)
create mode 100644 configs/mx6sabresd_spl_defconfig
diff --git a/configs/mx6sabresd_spl_defconfig
Hi Jagan,
On Wed, Nov 5, 2014 at 10:56 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Wed, Nov 5, 2014 at 5:21 AM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 1 November 2014 14:23, Bin Meng bmeng...@gmail.com wrote:
This series fix several bugs in current ICH SPI driver as well as
On Tue, 2014-11-11 at 22:05 +0900, Masahiro Yamada wrote:
+ /*
+ * If CONFIG_SYS_NAND_SELF_INIT is defined, each driver is responsible
+ * for instantiating struct nand_chip, while drivers/mtd/nand/nand.c
+ * still provides a struct mtd_info nand_info instance.
+ */
+
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote:
This function is not needed. Remove it to improve the generic init sequence
slightly.
Signed-off-by: Simon Glass s...@chromium.org
---
arch/x86/cpu/coreboot/coreboot.c| 11 ---
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote:
This normally indicates a problem which will prevent relocation from
functioning, resulting in a hang. Panic in this case to make it easier
to debug.
Signed-off-by: Simon Glass s...@chromium.org
---
Hi ,
From: s...@google.com s...@google.com on behalf of Simon Glass
s...@chromium.org
Sent: Monday, November 10, 2014 9:23 PM
To: Srinivasan S
Cc: Jagan Teki; U-Boot Mailing List
Subject: Re: [U-Boot] verified boot of beaglebone black
Hi,
On 9 November
This adds Renesas rmobile ARM SoC's SD/MMC host support.
This drivers tested with Gose board and Koelsch board.
Signed-off-by: Yoshiyuki Ito yoshiyuki.ito...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/include/asm/arch-rmobile/r8a7790.h | 6 +
Hi Bin,
On 11 November 2014 18:33, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Nov 12, 2014 at 12:15 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:52, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Fri, Nov 7, 2014 at 4:20 AM, Simon Glass
Hi Bin,
On 11 November 2014 18:43, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Nov 12, 2014 at 12:18 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
I am not sure if there is anything I missed but when I
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote:
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
boot.
Signed-off-by: Simon Glass s...@chromium.org
---
Hi Bin,
On 11 November 2014 18:17, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Nov 12, 2014 at 12:11 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 01:37, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 8:28 AM, Simon Glass
Dear Simon,
In message 1415751501-23407-2-git-send-email-...@chromium.org you wrote:
At present there is a string for the build date and time. In the case of an
Real Time Clock which needs to be reset, it is useful to reset it to the
build date, since it can't be earlier than that.
I can't
Hi Bin,
On 11 November 2014 18:50, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Nov 12, 2014 at 9:02 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 07:14, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Nov 11, 2014 at 9:00 AM, Simon Glass
Hi Wolfgang,
On 11 November 2014 22:22, Wolfgang Denk w...@denx.de wrote:
Dear Simon,
In message 1415751501-23407-2-git-send-email-...@chromium.org you wrote:
At present there is a string for the build date and time. In the case of an
Real Time Clock which needs to be reset, it is useful to
Hi Bin,
On 11 November 2014 22:21, Bin Meng bmeng...@gmail.com wrote:
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote:
Some toolchains put the relocation data into separate sections. Adjust the
linker script to catch this case. Without relocation data, U-Boot will not
Hi Simon,
On Wed, Nov 12, 2014 at 1:28 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 11 November 2014 22:21, Bin Meng bmeng...@gmail.com wrote:
On Wed, Nov 12, 2014 at 8:17 AM, Simon Glass s...@chromium.org wrote:
Some toolchains put the relocation data into separate sections. Adjust
T2080 v1.1 requires different MEM_PLL_RAT from previous v1.0,
and also update core frequency to 1.8GHz for v1.1.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
board/freescale/t208xqds/t2080_rcw.cfg | 9 +
board/freescale/t208xrdb/t2080_rcw.cfg | 13 +++--
2 files
Set the CONFIG_ENV_OFFSET from 384KB to 512KB offset, so we will have larger
space
for u-boot image.
When enabling NAND flash support feature, the u-boot image size has exceeded the
384KB, which causes overlay to the environment variables storage.
Signed-off-by: Ye.Li b37...@freescale.com
The i.MX6Q/DL sabreauto board has one NAND socket, set the
CONFIG_NAND_MXS and relevant NAND configurations to enable the
MXS NAND flash driver.
Add board level codes to set IOMUX and clock for GPMI-NAND and
BCH module.
Signed-off-by: Ye.Li b37...@freescale.com
---
Changes since v1:
- Use static
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