Hi, GUillaume
On 12/04/2014 09:18 AM, Minkyu Kang wrote:
+ Jaehoon Chung
On 04/12/14 00:23, Guillaume Gardet wrote:
Hi,
while trying latest u-boot GIT on snow (Google Chromebook ARM), I
encountered some problems with external SD card.
I cannot access to external SD card ('mmc dev 1'
Hi All,
Apologies for the delayed response, I’ve been on vacation.
Since this was working for you (Duxiaoqiang) previously it suggests that you
are using the default public exponent. If this is still the case you could, as
a temporary workaround, remove the public exponent from your public
Hello all:
I just downloaded the latest u-boot source code,then compiled with:
make qemu_mips_defconfig
make CROSS_COMPILE=mips-linux-uclibc-
then create image:
# dd of=flash bs=1k count=4k if=/dev/zero
# dd of=flash bs=1k conv=notrunc if=u-boot.bin
run with:
qemu-system-mips -M mips -pflash
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
include/configs/ot1200.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 9512b1e..0d0873d 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -197,6
Signed-off-by: Christian Gmeiner christian.gmei...@gmail.com
---
include/configs/ot1200.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 0d0873d..255c933 100644
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -85,6
Le 04/12/2014 09:00, Jaehoon Chung a écrit :
Hi, GUillaume
On 12/04/2014 09:18 AM, Minkyu Kang wrote:
+ Jaehoon Chung
On 04/12/14 00:23, Guillaume Gardet wrote:
Hi,
while trying latest u-boot GIT on snow (Google Chromebook ARM), I encountered
some problems with external SD card.
I cannot
On 03.12.2014 19:16, Suriyan Ramasami wrote:
Just a gentle ping to see if this can be commented on/Acked/Merged ?
Acked-by: Stefan Roese s...@denx.de
Thanks,
Stefan
___
U-Boot mailing list
U-Boot@lists.denx.de
Hi Fabio, Hi Tim,
On 14.11.2014 12:37, Fabio Estevam wrote:
From: Fabio Estevam fabio.este...@freescale.com
mx6sabresd_spl.cfg configures CCM registers, GPR registers and CCM_CCOSR.
Move the configuration to the spl code.
CCM_CCOSR setting is no longer required to get audio functionality in
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f (gw_ventana: Move the DCD settings to spl code)
Signed-off-by: Stefan Roese s...@denx.de
Cc: Fabio Estevam
Hi Masahiro,
On 4 December 2014 at 00:24, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Wed, 3 Dec 2014 19:32:18 -0700
Simon Glass s...@chromium.org wrote:
BTW, I implemented an i2c driver for my Panasonic board base on this
series,
and I am playing around with
Hi Masahiro,
On 4 December 2014 at 00:27, Masahiro Yamada yamad...@jp.panasonic.com wrote:
Hi Simon,
On Wed, 3 Dec 2014 19:36:15 -0700
Simon Glass s...@chromium.org wrote:
Hi Masahiro,
On 3 December 2014 at 19:01, Masahiro Yamada yamad...@jp.panasonic.com
wrote:
Hi Simon,
More
Hi Stefan,
On Thu, Dec 4, 2014 at 10:04 AM, Stefan Roese s...@denx.de wrote:
Otherwise NAND booting is likely to fail. Since this disables the NAND related
clocks and SPL can't load the main U-Boot from NAND.
This problem was introduced with this patch:
e25fbe3f (gw_ventana: Move the DCD
Hi Albert,
On 1 December 2014 at 11:01, Stephen Warren swar...@wwwdotorg.org wrote:
On 11/29/2014 08:56 PM, Simon Glass wrote:
Hi,
On 24 November 2014 at 08:52, Simon Glass s...@chromium.org wrote:
On 19 November 2014 at 20:41, Stephen Warren swar...@wwwdotorg.org
wrote:
The U-Boot port
+Tom
Hi Jagan,
On 2 December 2014 at 19:33, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Sun, Nov 23, 2014 at 9:43 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Wed, Nov 12, 2014 at 3:04 PM, Jagan Teki jagannadh.t...@gmail.com wrote:
On 12 November 2014 07:57, Bin Meng
Change CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS value to 2 for LS102XAQDS
and LS102XATWR. The XHCI controller has 2 ports; one for 2.0 and
the other for 3.0 USB transactions
Signed-off-by: Nikhil Badola nikhil.bad...@freescale.com
---
Depends on patch https://patchwork.ozlabs.org/patch/401448/
+Masahiro
Hi Tom,
On 17 November 2014 at 00:26, Simon Glass s...@chromium.org wrote:
On 16 November 2014 19:30, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
get_maintainer.pl always fails with following message:
./scripts/get_maintainer.pl: The current directory does not appear to
Sync this up with Linux v3.18-rc5. Exclude features that are unlikely to
supported in U-Boot soon (regulators, pinmux). Also the addresses are
updated to 32-bit. Otherwise it is the same. Also bring in the dt-bindings
for pinctrl.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Stephen
This will be used by nyan-big, but bring it in in a separate patch since it
will be common to other boards.
Signed-off-by: Simon Glass s...@chromium.org
---
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add patch to bring in cros-ec-keyboard.dtsi
Changes in v2: None
From: Allen Martin amar...@nvidia.com
Nyan-big is a Tegra124 clamshell board that is very similar to venice2, but
it has a different panel, the sdcard cd and wp sense are flipped, and it has
a different revision of the AS3722 PMIC.
This is the Acer Chromebook 13 CB5-311-T7NN (13.3-inch HD,
Hi Simon,
On 4 December 2014 at 18:34, Simon Glass s...@chromium.org wrote:
+Tom
Hi Jagan,
On 2 December 2014 at 19:33, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Sun, Nov 23, 2014 at 9:43 PM, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Wed, Nov 12, 2014 at 3:04 PM, Jagan Teki
On Fri, Nov 28, 2014 at 10:48:37PM +0100, Jeroen Hofstee wrote:
Hi all,
On 11-11-14 22:57, Tom Rini wrote:
On Mon, Nov 10, 2014 at 03:13:44PM -0700, Simon Glass wrote:
+Albert
Hi Tom,
On 16 September 2014 18:47, Tom Rini tr...@ti.com wrote:
On Tue, Sep 16, 2014 at 08:27:23PM -0400,
On Mon, Dec 01, 2014 at 03:31:17PM -0700, Simon Glass wrote:
Hi Tom,
A random collection of thnigs. Note the branch is 'sandbox'.
The following changes since commit 85bafb6da4dddfffa78479aa49a72ae48578a4ce:
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
(2014-11-26
This patch series add the Intel Queensbay platform support. The Queensbay
platform includes an Atom E6xx processor (codename Tunnel Creek) and a
Platform Controller Hub EG20T (codename Topcliff). The support depends
on Intel Firmware Support Package (FSP) to initialize the processor and
chipset
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.
Signed-off-by: Bin Meng bmeng...@gmail.com
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
tools/ifdtool.c | 29 ++---
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Makefile
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/start.S | 3 ++-
arch/x86/lib/asm-offsets.c | 2 +-
Define a weak verion of setup_pch_gpios() in the ich6-gpio driver and
move the actual setup codes into the board support codes, so that the
driver does not need to know any platform specific stuff (ie: include
the platform specifc chipset header file).
Signed-off-by: Bin Meng bmeng...@gmail.com
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/include/asm/pnp_def.h | 83
Signed-off-by: Bin Meng bmeng...@gmail.com
---
include/pci_ids.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h
index ee98bee..26f4748 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -2998,6 +2998,14 @@
#define
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/crownbay.dts | 53 +++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode 100644 arch/x86/dts/crownbay.dts
diff --git a/arch/x86/dts/Makefile
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/spi/ich.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c
index f5c6f3e..0e00edf 100644
---
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Also update FSP support codes license header to use SPDX ID.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/fsp_configs.c
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/include/asm/post.h | 2 ++
2 files changed, 3 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 60976db..969b07b 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check http://www.intel.com/fsp.
Note: in order to stay almost the same as the Intel release, no
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two
8
= hob
HOB list address: 0x3f42
No. | Address | Type | Length in Bytes
-|--|--|-
0 | 3f42 | Hand-off | 56
1 | 3f420038 | GUID Extension | 240
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/M0220661105.inc | 1288
1 file changed, 1288 insertions(+)
create mode 100644
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 13
arch/x86/cpu/queensbay/Kconfig | 75 ++
board/intel/crownbay/Kconfig | 20 +++
3 files changed, 108 insertions(+)
create mode 100644
Signed-off-by: Bin Meng bmeng...@gmail.com
---
configs/crownbay_defconfig | 6 ++
include/configs/crownbay.h | 52 ++
2 files changed, 58 insertions(+)
create mode 100644 configs/crownbay_defconfig
create mode 100644 include/configs/crownbay.h
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/Makefile | 9 +
arch/x86/cpu/queensbay/tnc.c | 48 +++
arch/x86/cpu/queensbay/tnc_car.S | 75
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile
index 7f09db5..5033d2b 100644
--- a/arch/x86/cpu/Makefile
+++ b/arch/x86/cpu/Makefile
@@ -15,6 +15,7 @@ obj-y += interrupts.o
Review delays and timeouts.
Get around 20 x faster access on Sheevaplug tests.
Changes in v2:
- increase number of loops
- remove initial delay
Changes in v1:
- review all loops, delays and timeouts
Signed-off-by: Gérald Kerma drea...@doukki.net
---
drivers/mmc/mvebu_mmc.c | 66
Signed-off-by: Bin Meng bmeng...@gmail.com
---
doc/README.x86 | 123 +
1 file changed, 123 insertions(+)
create mode 100644 doc/README.x86
diff --git a/doc/README.x86 b/doc/README.x86
new file mode 100644
index 000..a79f510
---
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Makefile | 8
1 file changed, 8 insertions(+)
diff --git a/Makefile b/Makefile
index c9ae77b..abfb74b 100644
--- a/Makefile
+++ b/Makefile
@@ -976,6 +976,14 @@ ifneq ($(CONFIG_HAVE_MRC),)
IFDTOOL_FLAGS += -w
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
board/intel/crownbay/crownbay.c | 6 ++
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/tnc.c | 26 +-
include/configs/crownbay.h | 2 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index c0d19aa..eea70c0
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/Makefile | 2 +-
arch/x86/cpu/queensbay/topcliff.c | 44
On 2014-12-03 19:40, Bill Pringlemeir wrote:
The gfxRAM has no ECC, but it is 512KB in size. The other
ECC SRAM comes in two banks of 256K each. The HAB uses parts of the
2nd bank and it seems that loading from the SD card may not exceed
a bank size (256k-32k boot offset = 224k). U-boot
Hi Simon,
I'm trying to boot a Linux distribution of choice on the Acer
CB5-311-T9XM (nyan-big). I applied your patches from last Wednesday (v4,
without the display driver) and flashed the patched uboot to the
RW_LEGACY section after running this script with some objcopies
I defined u-boot parameters so I can get it running
now I get:
reading kernel..device 0 Start 1263, Count 8192
MMC read: dev # 0, block # 1263, count 8192 ... 8192 blocks read: OK
completed
reading RFS..device 0 Start 9455, Count 2048
MMC read: dev # 0, block # 9455, count 2048 ... 2048
Hi Simon,
On 4 December 2014 at 08:23, SimonH simon.hoin...@codethink.co.uk wrote:
Hi Simon,
I'm trying to boot a Linux distribution of choice on the Acer CB5-311-T9XM
(nyan-big). I applied your patches from last Wednesday (v4, without the
display driver) and flashed the patched uboot to the
Signed-off-by: Tom Rini tr...@ti.com
---
doc/git-mailrc |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index 98069e6..6c79a6d 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -75,7 +75,7 @@ alias avr32 uboot, abiessmann
alias
I have the need to hardware partition eMMC devices from U-Boot along
with setting enhanced and reliable write attributes.
This series of patches adds this support to U-Boot via a new mmc
API, a few new members of struct mmc and a new mmc sub-command. It
also features several fixes to the eMMC
There is currently no command that will provide an overview of the hardware
partitions present on an eMMC device, one has to switch to every partition
via mmc dev and run mmcinfo for each to get the partition's capacity.
This commit adds a few lines of output to mmcinfo with the sizes of the
This extends the mmcinfo command's output to show which eMMC partitions
have the enhanced attribute set. Note that the eMMC spec says that
if the enhanced attribute is supported then the boot and RPMB
partitions are of the enhanced type.
The output of mmcinfo becomes:
Device: OMAP SD/MMC
The eMMC spec numbers general purpose partitions starting at 1, but
the mmcinfo output follows the internal numbering which starts at 0.
Make the mmcinfo command output number partitions as in the eMMC
spec to avoid confusion.
---
common/cmd_mmc.c |2 +-
1 files changed, 1 insertions(+), 1
eMMC partitions are defined as of eMMC 4.41, but mmcinfo process
partition info for eMMC = 4.0, change it to do it for = 4.41
---
common/cmd_mmc.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index 414fac6..bc02273 100644
---
---
drivers/mmc/mmc.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c045f9e..b088fd7 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1023,6 +1023,7 @@ static int mmc_startup(struct mmc *mmc)
The eMMC spec mandates that the high-capacity group size definitions
should be enabled when the device is partitioned (by setting
ERASE_GROUP_DEF in EXT_CSD). The current test to determine when this is
required misses a few cases. In particular a device may have been
partitioned without setting
This modification reads the size of the eMMC enhanced user data area
upon initialization of an mmc device, it will be used later by
mmcinfo.
---
drivers/mmc/mmc.c | 15 +++
include/mmc.h |4
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git
This adds output to show the eMMC enhanced user data area size and offset
along with the partition sizes in mmcinfo's output.
---
common/cmd_mmc.c | 11 ---
1 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index bc02273..aa5ba0e 100644
The erase_grp_size in struct mmc is to be a size in 512-byte sectors
but the code used to compute it for eMMC when EXT_CSD_ERASE_GROUP_DEF is
enabled computed it as bytes, leading to erase sizes and alignment
much larger than what is actually required by the mmc device.
---
drivers/mmc/mmc.c |
The eMMC spec says that partitioning is only effective after the
PARTITION_SETTING_COMPLETED is set in EXT_CSD (and a power cycle was done,
but that we cannot know). Thus the partition sizes and attributes should
be ignored when that bit is not set, otherwise the various capacities
are not
This adds the erase group size and high-capacity WP group size to
mmcinfo's output. The erase group size is necessary to properly align
erase requests on eMMC. The high-capacity WP group size is necessary
to properly align partitions on eMMC.
---
common/cmd_mmc.c | 10 ++
1 files
The mmc_startup() function uses the ext_csd data even if reading it
from the mmc device failed. This bug was introduced in commit
bc897b1d4d86597311430dbe7b3e6c807c8c53e5. We now bail out if
reading it fails, this should not be a problem as ext_csd was
introduced in MMC 4.0 and this code is
Read the eMMC high capacity write protect group size at mmc device
initialization. This is useful to correctly partition an eMMC device,
as partitions need to be aligned to this size.
---
drivers/mmc/mmc.c |6 ++
include/mmc.h |1 +
2 files changed, 7 insertions(+), 0 deletions(-)
Adds the mmc hwpartition sub-command to perform eMMC hardware
partitioning on an mmc device. The number of arguments can be
large for a complex partitioning, but as the partitioning has
to be done in one go it is difficult to make it simpler.
---
common/cmd_mmc.c | 93
The eMMC partition write reliability settings are to be set while
partitioning a device, as per the eMMC spec, so changes to these
attributes needs to be done in the hardware partitioning API.
This commit adds such support.
---
drivers/mmc/mmc.c | 39 +++
This extends the mmcinfo hardware partition info output to show
partitions with write reliability enabled with the WRREL string.
If the partition does not have write reliability enabled the WRREL
string is omitted; this is analogous to the ehhanced attribute.
Example output:
Device: OMAP SD/MMC
This adds an API to do hardware partitioning on eMMC devices. The
new mmc_hwpart_config() function does the partitioning in one go.
As the different attributes and partitioning options on eMMC may
be interdependent validation has to be done based on the complete
partitioning configuration. The
This change extends the mmc hwpartition sub-command to change the
per-partition write reliability settings. It also changes the
syntax used for the enhanced user data area slightly to better
accomodate the write reliability option.
---
common/cmd_mmc.c | 116
* Add netargs and netboot option.
* This enables tftp and nfs booting
* This puts omap5 devices inline with other devices such as am335x and am437x
Signed-off-by: Franklin S Cooper Jr fcoo...@ti.com
---
include/configs/ti_omap5_common.h | 15 ++-
1 file changed, 14 insertions(+), 1
Hello Jaehoon Chung, Guillaume GARDET,
On Thu, Dec 4, 2014 at 1:11 AM, Guillaume Gardet
guillaume.gar...@free.fr wrote:
Le 04/12/2014 09:00, Jaehoon Chung a écrit :
Hi, GUillaume
On 12/04/2014 09:18 AM, Minkyu Kang wrote:
+ Jaehoon Chung
On 04/12/14 00:23, Guillaume Gardet wrote:
Hi,
Diego Santa Cruz diego.santac...@spinetix.com wrote on 2014/11/28
12:12:56:
Hi,
-Original Message-
From: Joakim Tjernlund [mailto:joakim.tjernl...@transmode.se]
Sent: Friday, November 28, 2014 11:05 AM
To: Diego Santa Cruz
Cc: pa...@antoniou-consulting.com;
On 4 December 2014 at 08:00, Bin Meng bmeng...@gmail.com wrote:
Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file
Hi Bin,
On 4 December 2014 at 08:00, Bin Meng bmeng...@gmail.com wrote:
Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.
Signed-off-by: Bin Meng
On 4 December 2014 at 08:00, Bin Meng bmeng...@gmail.com wrote:
Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc
On 4 December 2014 at 08:00, Bin Meng bmeng...@gmail.com wrote:
Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.
Signed-off-by: Bin Meng bmeng...@gmail.com
Acked-by: Simon
On Wed, 3 Dec 2014, Pavel Machek wrote:
Hi!
altr,pinmux-regs = 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF 0xF
reg = 0xffd07300 0x0048;
altr,pinmux-regs = 0x0 0x51010 0x51010 0x51010 0x40605
0x40605 0x00605 0x40605 0x40605 0x40605
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/crownbay.dts | 53
+++
2 files changed, 55 insertions(+), 1 deletion(-)
create mode
Hi Bin,
On 4 December 2014 at 08:00, Bin Meng bmeng...@gmail.com wrote:
Define a weak verion of setup_pch_gpios() in the ich6-gpio driver and
move the actual setup codes into the board support codes, so that the
driver does not need to know any platform specific stuff (ie: include
the
Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Signed-off-by: Steve Rae s...@broadcom.com
---
README | 7 +++
common/fb_mmc.c | 19 ---
2 files changed, 23
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.
Signed-off-by: Bin Meng
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
include/pci_ids.h | 8
1 file changed, 8 insertions(+)
Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing list
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.
Acked-by: Simon Glass s...@chromium.org
Signed-off-by: Bin Meng bmeng...@gmail.com
---
drivers/spi/ich.c | 3 ++-
1 file changed, 2
Hi Bin,
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.
Use u16 instead of
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.
Also update FSP support codes license header to use SPDX ID.
Acked-by: Simon Glass
Hi Bin,
On 4 December 2014 at 08:01, Bin Meng bmeng...@gmail.com wrote:
This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.
For more details, check
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/ivybridge/cpu.c | 1 +
arch/x86/include/asm/post.h | 2 ++
2 files changed, 3 insertions(+)
Acked-by: Simon Glass s...@chromium.org
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Can we have a short commit message about what HOB is and why you want
to list it?
8
= hob
HOB list address: 0x3f42
No. | Address | Type |
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/M0220661105.inc | 1288
1
Hi Bin,
On 4 December 2014 at 08:02, Bin Meng bmeng...@gmail.com wrote:
Implement minimum required functions for the basic support to
queensbay platform and crownbay board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/Makefile | 9 +
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 13
arch/x86/cpu/queensbay/Kconfig | 75
++
board/intel/crownbay/Kconfig | 20
On 4 December 2014 at 08:03, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/Makefile | 1 +
1 file changed, 1 insertion(+)
Acked-by: Simon Glass s...@chromium.org
___
U-Boot mailing list
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
configs/crownbay_defconfig | 6 ++
include/configs/crownbay.h | 52
++
2 files changed, 58 insertions(+)
create mode
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
Makefile | 8
1 file changed, 8 insertions(+)
diff --git a/Makefile b/Makefile
index c9ae77b..abfb74b 100644
--- a/Makefile
+++ b/Makefile
@@ -976,6 +976,14
Hi Bin,
On 4 December 2014 at 08:03, Bin Meng bmeng...@gmail.com wrote:
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/queensbay/tnc.c | 26 +-
include/configs/crownbay.h | 2 ++
2 files changed, 27 insertions(+), 1 deletion(-)
diff --git
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