Currently only normal hashing is supported using hardware acceleration.
Added support for progressinve hashing using h/w.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
CC: Simon Glass s...@chromium.org
---
This patch is dependent on
Hi Przemyslaw,
On 28.01.2015 13:55, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled(ARM).
For tested Trats2 device, this was done in three steps.
First was enable the arch memcpy and memset.
The second step was
Hi Przemyslaw,
On Jan 28, 2015, at 16:10 , Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello Stefan,
On 01/28/2015 02:12 PM, Stefan Roese wrote:
Hi Przemyslaw,
On 28.01.2015 13:55, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards,
Hi Przemyslaw,
On Jan 28, 2015, at 16:30 , Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello,
On 01/28/2015 03:18 PM, Pantelis Antoniou wrote:
Hi Przemyslaw,
On Jan 28, 2015, at 16:10 , Przemyslaw Marczak p.marc...@samsung.com
wrote:
Hello Stefan,
On 01/28/2015 02:12 PM,
Hello Lubomir,
Am 28.01.2015 10:00, schrieb Lubomir Popov:
Hi Heiko,
Hello Lubomir,
Am 28.01.2015 09:32, schrieb Lubomir Popov:
Hi Heiko,
Hello Lubomir,
Am 24.11.2014 17:00, schrieb Lubomir Popov:
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus
Hello Stefan,
On 01/28/2015 02:12 PM, Stefan Roese wrote:
Hi Przemyslaw,
On 28.01.2015 13:55, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled(ARM).
For tested Trats2 device, this was done in three steps.
First
From: Enric Balletbo i Serra enric.balle...@collabora.com
Use the STATUS_LED APIs for indicating a boot progress instead of
show_boot_progress.
This patch also fixes a problem introduced with commit b3f4ca1135 (dm: omap3:
Move to driver model for GPIO and serial). After that commit the board
On Wed, Jan 21, 2015 at 10:32:43AM +0100, Michal Simek wrote:
Hi Tom,
please pull these 3 patches to your tree. On patch is fixing gem.
One is fixing ll_temac which you have reported and the last one is for MMC.
I have created special branch just with these changes.
Thanks,
Michal
Hello,
On 01/28/2015 03:18 PM, Pantelis Antoniou wrote:
Hi Przemyslaw,
On Jan 28, 2015, at 16:10 , Przemyslaw Marczak p.marc...@samsung.com wrote:
Hello Stefan,
On 01/28/2015 02:12 PM, Stefan Roese wrote:
Hi Przemyslaw,
On 28.01.2015 13:55, Przemyslaw Marczak wrote:
This patchset reduces
Hi Heiko,
Hello Lubomir,
Am 24.11.2014 17:00, schrieb Lubomir Popov:
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus transaction (aka atomic transfer), otherwise either the write
does not come into effect at all, or normal operation of internal
On Tue, 2015-01-27 at 11:27 +0100, Hans de Goede wrote:
Add support for the A80 to the rsb code.
Signed-off-by: Hans de Goede hdego...@redhat.com
@@ -129,6 +133,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr))
#define SUNXI_GPL(_nr)
On Tue, 2015-01-27 at 11:27 +0100, Hans de Goede wrote:
It turns out that the device_mode_data is rsn specific, rather then slave
specific, so integrate the rsb_set_device_mode() call into rsb_init().
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Hi,
On 28-01-15 10:18, Ian Campbell wrote:
On Tue, 2015-01-27 at 11:27 +0100, Hans de Goede wrote:
Add support for the A80 to the rsb code.
Signed-off-by: Hans de Goede hdego...@redhat.com
@@ -129,6 +133,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPI(_nr)(SUNXI_GPIO_I_START +
Hi,
On 28-01-15 10:13, Ian Campbell wrote:
On Sun, 2015-01-25 at 15:35 +0100, Hans de Goede wrote:
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used, so when an external vga dac
is used force v and hsync active high
On Tue, Jan 27, 2015 at 8:33 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
The current implementation exposes the eth_device struct to code that
needs to access the MAC address. Add a wrapper function for this
On Wed, 2015-01-28 at 10:25 +0100, Hans de Goede wrote:
Hi,
On 28-01-15 10:18, Ian Campbell wrote:
On Tue, 2015-01-27 at 11:27 +0100, Hans de Goede wrote:
Add support for the A80 to the rsb code.
Signed-off-by: Hans de Goede hdego...@redhat.com
@@ -129,6 +133,7 @@ enum
On Tue, Jan 27, 2015 at 8:34 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
First just add support for MAC drivers.
I don't fully understand this partly because my knowledge of the
network stack is limited. So
On Tue, Jan 27, 2015 at 9:24 PM, Sonic Zhang sonic@gmail.com wrote:
Hi Joe,
On Wed, Jan 28, 2015 at 4:43 AM, Joe Hershberger
joe.hershber...@gmail.com wrote:
On Mon, Jan 26, 2015 at 8:54 PM, sonic@gmail.com wrote:
From: Sonic Zhang sonic.zh...@analog.com
Board can define its
On Tue, Jan 27, 2015 at 8:34 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
Add basic network support to sandbox which includes a network driver.
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
Hi Heiko,
Hello Lubomir,
Am 28.01.2015 09:32, schrieb Lubomir Popov:
Hi Heiko,
Hello Lubomir,
Am 24.11.2014 17:00, schrieb Lubomir Popov:
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus transaction (aka atomic transfer), otherwise either the
On Sun, 2015-01-25 at 15:35 +0100, Hans de Goede wrote:
CONFIG_TARGET_FOO was only used in board/sunxi/Makefile to select the
dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some
special handling of the bananapi/bananapro (both sun7i), all sun5i and sun7i
boards have been
On Sun, 2015-01-25 at 15:35 +0100, Hans de Goede wrote:
And use this to set the GMAC Transmit Clock Delay Chain value on Banana
boards, rather then keying of CONFIG_TARGET_FOO.
Signed-off-by: Hans de Goede hdego...@redhat.com
Acked-by: Ian Campbell i...@hellion.org.uk
Although:
@@ -24,20
On Sun, 2015-01-25 at 15:35 +0100, Hans de Goede wrote:
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used, so when an external vga dac
is used force v and hsync active high independent of what the modeline says.
Does
Hi,
On 26-01-15 23:35, Adam Sampson wrote:
This is a low-cost Allwinner A20 board with Arduino-style GPIO headers;
it features 1G RAM, 4G NAND flash, 1 micro-SD, 2 USB sockets, 1 micro
USB socket for OTG and another for power in, HDMI, SATA, 5V power for
SATA devices, gigabit Ethernet, an IR
Hi,
On 27-01-15 19:58, Paul Kocialkowski wrote:
Signed-off-by: Paul Kocialkowski cont...@paulk.fr
Thanks, I've merged this with a number of changes:
- Fixed op the CONFIG_VIDEO_LCD_MODE to also properly define left/right
and top/bottom margins. See: http://linux-sunxi.org/LCD
- Added a
Hello Lubomir,
Am 28.01.2015 09:32, schrieb Lubomir Popov:
Hi Heiko,
Hello Lubomir,
Am 24.11.2014 17:00, schrieb Lubomir Popov:
I2C chips do exist that require a write of some multi-byte data to occur in
a single bus transaction (aka atomic transfer), otherwise either the write
does not
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.
The problem seems to be specific to the OLinuxIno A13 (normal micro)
boards. I've just looked up the schematics and they use an opendrain driver
for the vga sync lines,
On Wed, 2015-01-28 at 11:47 +0100, Hans de Goede wrote:
On both my A13-OLinuxIno and my A13-OLinuxIno-Micro, the vga output gives an
unstable image when active low v or hsync is used.
The problem seems to be specific to the OLinuxIno A13 (normal micro)
boards. I've just looked up the
On Sun, 2015-01-25 at 15:35 +0100, Hans de Goede wrote:
Currently we've separate detailed dram settings for all sun5i boards, this
moves them over to using auto dram configuration so that we can get rid of
all the per board dram_foo.c files.
This has been tested on a A10s-Olinuxino,
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled(ARM).
For tested Trats2 device, this was done in three steps.
First was enable the arch memcpy and memset.
The second step was enable memset for .bss clear.
The third step for reduce this
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot time.
This was tested on Trats2.
A quick test with trace. Boot time from start to main_loop() entry:
- ~1527ms - before this
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performance. This is able
thanks to the ARM multiple register instructions.
Unfortunatelly the relocation is done without the cache enabled,
so it takes some time, but zeroing the BSS memory
For writing files, DFU implementation requires the file buffer
with the len at least of file size. For big files it requires
the same big buffer.
Previously the file buffer was allocated as a static variable,
so it was a part of U-Boot .bss section. For 32MiB len of buffer
we have 32MiB of
Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/Kconfig | 17 +
arch/x86/cpu/Makefile | 1 +
2 files changed, 18
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/include/asm/arch-quark/device.h | 28
arch/x86/include/asm/arch-quark/quark.h | 57
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
to this network are accomplished by populating the message control
register (MCR), Message Control Register eXtension (MCRX) and the
message data register
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd-ram_size is assigned.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/quark/Kconfig | 63 ++
arch/x86/cpu/quark/Makefile| 8
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM (CAR) before system memory is available.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/cpu/quark/car.S | 105
On Wed, Jan 28, 2015 at 09:57:30PM +0100, Daniel Schwierzeck wrote:
Am 26.01.2015 um 16:03 schrieb Paul Burton:
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it
Hi Paul,
Am 26.01.2015 um 16:02 schrieb Paul Burton:
This series cleans up the MIPS cache code somewhat, and unifies the
mips32 mips64 implementations of it. This is largely in preparation
for further patches adding L2 cache support. The final patch of this
series fixes a bug encountered
Thanks, I've merged this with a number of changes:
- Fixed op the CONFIG_VIDEO_LCD_MODE to also properly define left/right
and top/bottom margins. See: http://linux-sunxi.org/LCD
Wow, that's great, this is exactly what I was looking for. I guess I
hadn't been looking hard enough for it!
-
On 26 January 2015 at 15:22, Simon Glass s...@chromium.org wrote:
From: Martin Dorwig dor...@tetronik.com
this is an atempt to make the export of functions typesafe.
I replaced the jumptable void ** by a struct (jt_funcs) with function
pointers.
The EXPORT_FUNC macro now has 3 fixed
Am 26.01.2015 um 16:02 schrieb Paul Burton:
As a step towards unifying the cache maintenance code for mips32
mips64 CPUs, stop using .set ISA directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When
From 42512a3fe6f2434cfc9381328d2a4755ebe6d051 Mon Sep 17 00:00:00 2001
From: Kim Phillips kim.phill...@freescale.com
Date: Wed, 28 Jan 2015 13:15:01 -0600
Subject: [PATCH] scripts/checkstack.pl: update to get AArch64 port from Linux
Bring checkstack.pl up to date from its upstream Linux
Am 26.01.2015 um 16:03 schrieb Paul Burton:
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0
On Wed, Jan 28, 2015 at 09:31:25PM +0100, Daniel Schwierzeck wrote:
Hi Paul,
Am 26.01.2015 um 16:02 schrieb Paul Burton:
This series cleans up the MIPS cache code somewhat, and unifies the
mips32 mips64 implementations of it. This is largely in preparation
for further patches adding L2
On Wed, Jan 28, 2015 at 09:43:25PM +0100, Daniel Schwierzeck wrote:
Am 26.01.2015 um 16:02 schrieb Paul Burton:
As a step towards unifying the cache maintenance code for mips32
mips64 CPUs, stop using .set ISA directives in the more developed
mips32 version of the code. Instead, when
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
This board includes a few IDs we have not seen before.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
include/pci_ids.h | 5 +
1 file changed, 5
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
This board uses a new PCI ID.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
drivers/video/vesa_fb.c | 1 +
1 file changed, 1 insertion(+)
Applied to
On 27 January 2015 at 22:30, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
There is an existing function prototype in the header file but it is not
implemented. Implement something similar.
Signed-off-by: Simon Glass
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Sometimes microcode is delivered as a header file. Allow the tool to
support this as well as collecting multiple microcode blocks into a
single update.
Signed-off-by: Simon Glass s...@chromium.org
Tested-by: Bin Meng
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Add a driver which locates the available XHCI controllers on the PCI bus
and makes them available.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Use the new utility function instead of local code.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
drivers/usb/host/ehci-pci.c | 53
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Allow measuring of boot time using bootstage.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
Tested-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
Tested-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
Applied to u-boot-x86.
___
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage
to two API functions which use that convention. UPD_TERMINATOR is common
so move it into a common file.
Signed-off-by: Simon Glass s...@chromium.org
On 27 January 2015 at 21:56, Bin Meng bmeng...@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
Since these board functions seem to be the same for all boards which use
FSP, move them into a common file. We can adjust this later if future FSPs
need more
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
While queensbay is the first chip with these settings, others will want to
use them too. Make them common.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
For now this code seems to be the same for all FSP platforms. Make it
common until we see what differences are required.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
Tested-by: Bin Meng
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Tidy up the FSP support code a little.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
arch/x86/lib/fsp/fsp_support.c | 10 +-
1 file changed, 5
On 27 January 2015 at 22:13, Bin Meng bmeng...@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
On some hardware this time can be significant. Add bootstage support for
measuring this. The result can be obtained using 'bootstage report' or
passed on to the Linux via the device tree.
Signed-off-by: Simon Glass
Hi,
On 27 January 2015 at 08:38, Simon Glass s...@chromium.org wrote:
+Minkyu
Hi Przemyslaw,
On 27 January 2015 at 05:36, Przemyslaw Marczak p.marc...@samsung.com wrote:
This patchset adds support to driver model i2c api for Exynos i2c driver.
Few boards are using this driver, but the
On 24 January 2015 at 06:34, Simon Glass s...@chromium.org wrote:
On 24 January 2015 at 02:17, Bin Meng bmeng...@gmail.com wrote:
CONFIG_SATA_INTEL is not referenced anywhere, so remove it.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
include/configs/x86-common.h | 1 -
1 file changed,
Am 28.01.2015 um 22:08 schrieb Paul Burton:
On Wed, Jan 28, 2015 at 09:43:25PM +0100, Daniel Schwierzeck wrote:
Am 26.01.2015 um 16:02 schrieb Paul Burton:
As a step towards unifying the cache maintenance code for mips32
mips64 CPUs, stop using .set ISA directives in the more developed
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
If the BIOS emulator is not available, allow use of native execution if
available, and vice versa. This can be controlled by the caller.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
On 27 January 2015 at 22:36, Bin Meng bmeng...@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
This setting will be used by more than just ivybridge so make it common.
Also rename it to PCIE_ECAM_BASE which is a more descriptive name.
Signed-off-by:
On 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Since we must run a PCI BIOS ROM, and this can take a calamitous amount of
time, measure it using bootstage.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng bmeng...@gmail.com
---
Changes in v2: None
On 27 January 2015 at 21:32, Bin Meng bmeng...@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
Rather than requiring the Makefile to be modified, provide a build option to
enable the ROM to be built.
We cannot do this by default since it requires binary
uOn 27 January 2015 at 21:13, Simon Glass s...@chromium.org wrote:
Some information has been gleaned on tools and procedures for porting
U-Boot to different x86 platforms. Add a few notes to start things off.
Signed-off-by: Simon Glass s...@chromium.org
Reviewed-by: Bin Meng
Hi Bin,
On 27 January 2015 at 23:02, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Wed, Jan 28, 2015 at 1:17 PM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 27 January 2015 at 07:00, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Jan 27, 2015 at 9:23 AM, Simon Glass
On 27 January 2015 at 21:57, Bin Meng bmeng...@gmail.com wrote:
On Wed, Jan 28, 2015 at 1:13 PM, Simon Glass s...@chromium.org wrote:
Since the FSP is a black box it helps to have some sort of debugging
available to check its inputs. If the debug UART is in use, set it up
after CAR is
On Wed, 2015-01-28 at 15:42 +0100, Hans de Goede wrote:
Although I might have been tempted to adjust mode-sync in the caller or
the place which populates it in the first place, just due to a general
dislike of boolean params to functions (which are opaque at the caller)
and to keep mode in
New board/intel/galileo board directory with minimum codes, plus
board dts, defconfig and configuration files.
Signed-off-by: Bin Meng bmeng...@gmail.com
---
arch/x86/dts/Makefile | 3 ++-
arch/x86/dts/galileo.dts| 43 +
On Wed, Jan 28, 2015 at 10:27:47PM +0100, Daniel Schwierzeck wrote:
Am 28.01.2015 um 22:05 schrieb Paul Burton:
On Wed, Jan 28, 2015 at 09:31:25PM +0100, Daniel Schwierzeck wrote:
Hi Paul,
Am 26.01.2015 um 16:02 schrieb Paul Burton:
This series cleans up the MIPS cache code somewhat,
On Mon, Jan 19, 2015 at 11:33:38AM +0100, Stefan Roese wrote:
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the
While the Freescale ARMv8 board LS2085A will enter U-Boot both
on a master and a secondary (slave) CPU, this is not the common
behaviour on ARMv8 platforms. The norm is that U-Boot is entered
from the master CPU only, while the other CPUs are kept in
WFI (wait for interrupt) state.
The code
Current MIPS systems do not require that loads be performed to force the
parity of cache lines, a simple invalidate by clearing the tag for each
line will suffice. Thus this patch makes the loads subsequent second
invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
option, and
Reduce duplication by performing loops through cache tags using an
assembler macro.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck daniel.schwierz...@gmail.com
---
Changes in v2:
- None (rebase atop change to patch 1).
---
arch/mips/lib/cache_init.S | 30
Reduce duplication between reading the configuration of the L1 dcache
icache by performing both using a macro which calculates the appropriate
line cache sizes from the coprocessor 0 Config1 register.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 2.
Signed-off-by: Paul Burton
The mips_init_[id]cache functions are small only called once from a
single callsite. Inlining them allows mips_cache_reset to avoid having
to bother moving arguments around leaves it a leaf function which is
thus able to simply keep the return address live in the ra register
throughout,
Hi Joe,
On 28 January 2015 at 03:36, Joe Hershberger joe.hershber...@gmail.com wrote:
On Tue, Jan 27, 2015 at 8:34 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
The sandbox driver will now generate response
Hi Simon,
On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
device.h for integrated pci devices' bdf on Quark SoC and quark.h for
various memory-mapped and i/o-mapped base addresses within SoC.
On 28/01/15 00:38, Simon Glass wrote:
+Minkyu
Hi Przemyslaw,
On 27 January 2015 at 05:36, Przemyslaw Marczak p.marc...@samsung.com wrote:
This patchset adds support to driver model i2c api for Exynos i2c driver.
Few boards are using this driver, but the board peripherals are not ported
Hi Simon,
On Thu, Jan 29, 2015 at 2:05 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:20, Bin Meng bmeng...@gmail.com wrote:
Add minimum codes to support Intel Quark SoC. DRAM initialization
is not ready yet so a hardcoded gd-ram_size is assigned.
Signed-off-by:
The mips32 mips64 cache initialization code differs only in that the
mips32 code supports reading the cache size from coprocessor 0 registers
at runtime. Move the more developed mips32 version to a common
arch/mips/lib/cache_init.S remove the now-redundant mips64 version in
order to reduce
Hi Joe,
On 28 January 2015 at 03:22, Joe Hershberger joe.hershber...@gmail.com wrote:
On Tue, Jan 27, 2015 at 8:34 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
First just add support for MAC drivers.
I
Hi Minkyu,
On 28 January 2015 at 18:58, Minkyu Kang mk7.k...@samsung.com wrote:
On 28/01/15 00:38, Simon Glass wrote:
+Minkyu
Hi Przemyslaw,
On 27 January 2015 at 05:36, Przemyslaw Marczak p.marc...@samsung.com
wrote:
This patchset adds support to driver model i2c api for Exynos i2c
Hi Simon,
On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
In the Quark SoC, some chipset commands are accomplished by utilizing
the internal message network within the host bridge (D0:F0). Accesses
Hi Simon,
On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is
initialized by hardware. eSRAM is the ideal place to be used
for Cache-As-RAM
This series cleans up the MIPS cache code somewhat, and unifies the
mips32 mips64 implementations of it. This is largely in preparation
for further patches adding L2 cache support. The final patch of this
series fixes a bug encountered with recent cores on Malta boards.
Paul Burton (8):
MIPS:
As a step towards unifying the cache maintenance code for mips32
mips64 CPUs, stop using .set ISA directives in the more developed
mips32 version of the code. Instead, when present make use of the GCC
builtin for emitting a cache instruction. When not present, simply don't
bother with the .set
Move the more developed mips32 version of the cache maintenance
functions to a common arch/mips/lib/cache.c, in order to reduce
duplication between mips32 mips64.
Signed-off-by: Paul Burton paul.bur...@imgtec.com
Cc: Daniel Schwierzeck daniel.schwierz...@gmail.com
---
Changes in v2:
- None
Hi Joe,
On 28 January 2015 at 02:45, Joe Hershberger joe.hershber...@gmail.com wrote:
On Tue, Jan 27, 2015 at 8:33 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 27 January 2015 at 16:27, Joe Hershberger joe.hershber...@ni.com
wrote:
The current implementation exposes the eth_device
Hi Bin,
On 28 January 2015 at 18:58, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 29, 2015 at 2:04 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
device.h for integrated pci devices' bdf on Quark SoC and quark.h
Hi Bin,
On 28 January 2015 at 19:27, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 29, 2015 at 2:05 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
This series adds the first step of bare support for the Intel
Hi Bin,
On 28 January 2015 at 19:17, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Thu, Jan 29, 2015 at 2:05 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:20, Bin Meng bmeng...@gmail.com wrote:
Add minimum codes to support Intel Quark SoC. DRAM initialization
Hi Simon,
On Thu, Jan 29, 2015 at 2:05 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 28 January 2015 at 07:19, Bin Meng bmeng...@gmail.com wrote:
This series adds the first step of bare support for the Intel Quark
SoC support which can be validated on Intel Galileo board.
Intel Quark
Hi Joe,
On Wed, Jan 28, 2015 at 5:42 PM, Joe Hershberger
joe.hershber...@gmail.com wrote:
On Tue, Jan 27, 2015 at 9:24 PM, Sonic Zhang sonic@gmail.com wrote:
Hi Joe,
On Wed, Jan 28, 2015 at 4:43 AM, Joe Hershberger
joe.hershber...@gmail.com wrote:
On Mon, Jan 26, 2015 at 8:54 PM,
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