Hi Heiko,
sorry for the late reply!
This patch does not cleanly apply ... and some comments below follow.
On 06/15/2015 02:21 PM, Heiko Schocher wrote:
add extensions for the axm board:
- power on LED on power up
- press both recovery buttons on power up to enter
recovery mode
- detect
Hi Heiko,
again sorry for the late reply!
On 06/15/2015 02:25 PM, Heiko Schocher wrote:
add support for DFU on the corvus board.
Signed-off-by: Heiko Schocher h...@denx.de
---
board/siemens/corvus/board.c | 21 +
include/configs/corvus.h | 29
From: Hou Zhiqiang b48...@freescale.com
The clear flag status register operation was required by Micron
SPI flash chips, which support FSR. And if an error bit of FSR
have been set, it must be cleared by the clear FSR operation.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Signed-off-by:
On 18 August 2015 at 09:05, Zhiqiang Hou b48...@freescale.com wrote:
From: Hou Zhiqiang b48...@freescale.com
It doesn't make sense to compare a 'u8' element with Zero.
Signed-off-by: Hou Zhiqiang b48...@freescale.com
Reviewed-by: Jagan Teki jt...@openedev.com
---
drivers/mtd/spi/sf_ops.c
On 08/13/2015 03:43 PM, Erik van Luijk wrote:
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 2).
Signed-off-by: Erik van Luijk evanlu...@interact.nl
Reviewed-by: Andreas Bießmann andreas.de...@gmail.com
---
On Mon, 2015-08-17 at 18:08 +0200, Hans de Goede wrote:
common/dlmalloc.c is quite big, both in .text and .data usage. E.g.
for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94
bytes, and
.data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede
On 18 August 2015 at 13:16, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Mon, Aug 17, 2015 at 6:32 PM, Jagan Teki jt...@openedev.com wrote:
Add spi_flash_read_bar function for reading bar and discovering
bar commands at probe time.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Michal
On 18 August 2015 at 14:31, Zhiqiang Hou b48...@freescale.com wrote:
From: Hou Zhiqiang b48...@freescale.com
The clear flag status register operation was required by Micron
SPI flash chips, which support FSR. And if an error bit of FSR
have been set, it must be cleared by the clear FSR
Hi Heiko,
sorry for the late reply!
No real objections with this patch, it just will not apply without the
AXM patch (patchwork #484257). Could you please rebase and re-send both?
Andreas
On 06/15/2015 02:40 PM, Heiko Schocher wrote:
taurus changes:
- rename at91_spl_board_init to
Hi Erik,
On 08/13/2015 03:43 PM, Erik van Luijk wrote:
On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.
from the specs this seems correct. Could I please get a Tested-by, since
I do not own one of these boards.
Best regards
Andreas
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT SSDT
ACPI table entries.
Use a Kconfig option GENERATE_ACPI_TABLE to tell
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by: Saket Sinha saket.sinh...@gmail.com
---
arch/x86/cpu/qemu/Makefile | 2 +-
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
This patch mainly adds ACPI support to QEMU.
Verified by booting Linux kernel on QEMU i440FX and Q35.
Signed-off-by: Saket Sinha saket.sinh...@gmail.com
---
arch/x86/cpu/qemu/Makefile | 1 +
On Tue, Aug 18, 2015 at 7:18 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Mingkai,
On Mon, Aug 17, 2015 at 2:49 PM, Mingkai Hu mingkai...@freescale.com wrote:
Please add a commit message on this change.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
drivers/net/e1000.c | 8
On 18-08-15, 09:27, Stefan Roese wrote:
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.
Tested on the SPEAr600 EVB.
Signed-off-by:
Hi Tom,
Please pull this PR.
thanks!
Jagan.
The following changes since commit 632093b566569329bc6e5b0893bdca01de905314:
Merge git://git.denx.de/u-boot-x86 (2015-08-14 16:27:16 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-spi.git master
for you to fetch
On Mon, 2015-08-17 at 16:14 -0600, Simon Glass wrote:
The nice thing about sorting things in groups is that you can see at
a
glance what is missing. It doesn't make sense to have:
asm/aaa.h
bbb.c
asm/ccc.h
since the asm/ includes are quite a different category.
But that's not at all
Hi Saket,
On Tue, Aug 18, 2015 at 9:25 AM, Bin Meng bmeng...@gmail.com wrote:
Hi Saket,
On Tue, Aug 18, 2015 at 3:29 AM, Saket Sinha saket.sinh...@gmail.com wrote:
ACPI(Advanced Configuration and Power Interface), is a Power Management and
configuration standard allowing the operating
On Mon, 2015-08-17 at 18:08 +0200, Hans de Goede wrote:
Move some #define-s around from one #ifdef block to another to
reduce the number of #ifdef blocks (note this causes no functional
changes even though the conditions are not always exactly the same)
and move generic #include statements to
On Tue, Aug 18, 2015 at 3:53 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Aug 17, 2015 at 09:28:44AM -0600, Simon Glass wrote:
This causes widespread breakage due to the operation of the low-level code
in crt0.S and cro0_64.S for ARM at least.
The fix is not complicated but it seems safer
The SPL implementation for SPEAr600 is older than the common SPL
infrastructure. This patch now moves the SPEAr600 SPL over to the
common SPL code.
Tested on the only SPEAr board that currently uses SPL in mainline
U-Boot, the x600.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Viresh Kumar
This patch brings the following changes to the x600 board support:
- Add USB EHCI support
- Add VFAT support for USB key file access
- Increase malloc size (for UBI / UBIFS usage)
- Enable Thumb mode to save some image space
- Remove unreferenced CONFIG_STACKSIZE
- Remove unreferenced
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Viresh Kumar viresh.ku...@linaro.org
Cc: Vipin Kumar vk.vi...@gmail.com
Cc: Marek
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.
Tested on the SPEAr600 EVB.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Viresh Kumar
The designware ethernet driver supports d-cache now. So there is nothing
stopping us now to enable the caches completely on SPEAr.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese s...@denx.de
Cc: Viresh Kumar viresh.ku...@linaro.org
Cc: Vipin Kumar vk.vi...@gmail.com
---
Hi Jagan,
On Mon, Aug 17, 2015 at 6:32 PM, Jagan Teki jt...@openedev.com wrote:
Add spi_flash_read_bar function for reading bar and discovering
bar commands at probe time.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Michal Simek michal.si...@xilinx.com
Cc: Siva Durga Prasad Paladugu
Hi Bin,
On 18 August 2015 at 13:23, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Mon, Aug 17, 2015 at 6:32 PM, Jagan Teki jt...@openedev.com wrote:
Use the flash-flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
Signed-off-by: Jagan Teki
Hi Jagan,
On Tue, Aug 18, 2015 at 1:22 PM, Jagan Teki jt...@openedev.com wrote:
On 18 August 2015 at 10:12, Bin Meng bmeng...@gmail.com wrote:
Hi Jagan,
On Mon, Aug 17, 2015 at 6:32 PM, Jagan Teki jt...@openedev.com wrote:
BAR and spi_flash_cmd_wait_ready are updated to make more
module to
Hi Jagan,
On Mon, Aug 17, 2015 at 6:32 PM, Jagan Teki jt...@openedev.com wrote:
Use the flash-flags for generic usage, not only for dm-spi-flash,
this will be used for future flag additions.
Signed-off-by: Jagan Teki jt...@openedev.com
Cc: Bin Meng bmeng...@gmail.com
---
On Mon, 2015-08-17 at 20:55 +, Tom Warren wrote:
I have no problem with this sort order. Let me know if you want me to
take this in to Tegra or if it should go into u-boot-mmc tree via
Panto.
I would be OK either way but as Panto has not responded I would be more
than grateful if you
Hi Andreas,
I tested this commit on my picosam9g45, the design of the primary DDR
controller is equal to the at91sam9m10g45ek board.
0x2000 is the memory at CS1 (not initialized/available)
0x7000 is the memory at the primary DDR controller (should work)
On the picosam9g45 there is no
Hi,
I have verified that I can reproduce a workign build of U-Boot as
x86-64bit EFI payload for Qemu: I can boot it, interact with various
filesystems of both real and emulated disks, etc.
Now I would like to build and boot it for a real board, still as EFI payload.
The docs/README.efi file
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.
100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets.
Dear Wu, Josh,
Josh Wu josh...@atmel.com writes:
From: Bo Shen voice.s...@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache
for sama5d3 SoC, the OHCI can not work properly. So, switch to
EHCI, then the USB can work well.
Signed-off-by: Bo Shen voice.s...@atmel.com
Hello Andreas,
Am 18.08.2015 um 13:46 schrieb Andreas Bießmann:
Dear Heiko Schocher,
Heiko Schocher h...@denx.de writes:
rename at91_spl_board_init into spl_board_init
Signed-off-by: Heiko Schocher h...@denx.de
---
board/siemens/corvus/board.c | 2 +-
1 file changed, 1 insertion(+), 1
This commit adds basic Cavium ThunderX 88xx board definitions and support.
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
Changes in v4:
- Moved CONFIG_SYS_PROMPT to configs/thunderx_88xx_defconfig
- Add proper
This commit adds functions issuing calls to the product-specific ATF
services
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
This commit adds the psci.h header file from Linux kernel
which contains definitions related to the PSCI interface provided
by firmware
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
Changes in v4: None
Changes in
On some systems, UART initialization is performed before running U-Boot.
This commit allows to skip UART re-initializaion on those systems
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
Changes in v4:
- Fixed build
Change the dram_init() function on ThunderX to query ATF services for
the real installed DRAM size
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
On 18 August 2015 at 17:56, Sergey Temerkhanov s.temerkha...@gmail.com wrote:
Change the dram_init() function on ThunderX to query ATF services for
the real installed DRAM size
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla
hi Przemyslaw/Lukasz,
I would like to know if the support for OdroidXU4 be added in u-boot.
Odroid-XU4 is similar to Odroid-XU3 SOC wise.
But Odroid -XU4 is having Realtek r8152 1000 giga byte Ethernet card.
So how about added the support for this board in u-boot.
-Anand Moon
From: Marcel Ziswiler marcel.ziswi...@toradex.com
Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range -
Hi Bin,
On 17 August 2015 at 20:25, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Aug 18, 2015 at 10:00 AM, Simon Glass s...@chromium.org wrote:
Hi Bin,
On 17 August 2015 at 18:20, Bin Meng bmeng...@gmail.com wrote:
Hi Simon,
On Tue, Aug 18, 2015 at 6:14 AM, Simon Glass
Hi Hans,
On 18 August 2015 at 03:29, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 18-08-15 00:14, Simon Glass wrote:
Hi Hans,
On 6 August 2015 at 12:13, Hans de Goede hdego...@redhat.com wrote:
sun6i and later have a couple of io-blocks which are shared between the
main CPU core and
Hi Hans,
On 18 August 2015 at 03:23, Hans de Goede hdego...@redhat.com wrote:
Hi,
On 18-08-15 03:59, Simon Glass wrote:
Hi Hans,
On 17 August 2015 at 10:08, Hans de Goede hdego...@redhat.com wrote:
Before this patch malloc_simple would always allocate a chunk of RAM from
the stack.
Dear Heiko Schocher,
Heiko Schocher h...@denx.de writes:
rename at91_spl_board_init into spl_board_init
Signed-off-by: Heiko Schocher h...@denx.de
---
board/siemens/corvus/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
applied to u-boot-atmel/master, thanks!
Best regards,
On Sun, Aug 16, 2015 at 7:55 PM, Marek Vasut ma...@denx.de wrote:
On Saturday, August 15, 2015 at 12:28:10 AM, Sergei Temerkhanov wrote:
On Fri, Aug 14, 2015 at 11:46 PM, Marek Vasut ma...@denx.de wrote:
On Friday, August 14, 2015 at 05:14:09 PM, Sergey Temerkhanov wrote:
This patch fixes a
This patch adds the read_mpidr() function which returns the
MPIDR_EL1 register value
Signed-off-by: Sergey Temerkhanov s.temerkha...@gmail.com
Signed-off-by: Radha Mohan Chintakuntla rchintakun...@cavium.com
Reviewed-by: Simon Glass s...@chromium.org
---
Changes in v4: None
Changes in v3: None
Hi Lukasz,
On 11 August 2015 at 02:45, Lukasz Majewski l.majew...@samsung.com wrote:
Dear All,
Please assess if the following presentation is suitable for the 2015
U-boot Mini Summit held at ELCE2015.
__Title__
Automated Test System - build blocks
__Abstract__
Assuring software
Hi Marcel,
On 18 August 2015 at 02:11, Marcel Ziswiler mar...@ziswiler.com wrote:
On Mon, 2015-08-17 at 16:14 -0600, Simon Glass wrote:
The nice thing about sorting things in groups is that you can see at
a
glance what is missing. It doesn't make sense to have:
asm/aaa.h
bbb.c
asm/ccc.h
Hi Sergei,
On 18 August 2015 at 02:49, Sergei Temerkhanov s.temerkha...@gmail.com wrote:
On Tue, Aug 18, 2015 at 3:53 AM, Tom Rini tr...@konsulko.com wrote:
On Mon, Aug 17, 2015 at 09:28:44AM -0600, Simon Glass wrote:
This causes widespread breakage due to the operation of the low-level code
Hi Josh,
On 08/18/2015 01:46 PM, Andreas Bießmann wrote:
Dear Wu, Josh,
Josh Wu josh...@atmel.com writes:
From: Bo Shen voice.s...@atmel.com
As the cache coherence issue in OHCI HCD, when enable I/D cache
for sama5d3 SoC, the OHCI can not work properly. So, switch to
EHCI, then the USB
Hello Anand,
On 08/18/2015 12:26 PM, Anand Moon wrote:
hi Przemyslaw/Lukasz,
I would like to know if the support for OdroidXU4 be added in u-boot.
Odroid-XU4 is similar to Odroid-XU3 SOC wise.
But Odroid -XU4 is having Realtek r8152 1000 giga byte Ethernet card.
So how about added the support
Hi Stephen,
I want to add USB keyboard support to raspberry pi but I get the following
error when I do 'usb start' with a keyboard plugged-in:
unable to get device descriptor (error=-22)
Ethernet chip and mass storage devices are found.
I found this thread from February:
Hello Andreas,
Am 18.08.2015 um 11:10 schrieb Andreas Bießmann:
Hi Heiko,
sorry for the late reply!
This patch does not cleanly apply ... and some comments below follow.
I have rebased version against current head, so I can easy
repost this (and the taurus patch). I work in your comments
Hi Heiko,
On 08/18/2015 02:19 PM, Heiko Schocher wrote:
Hello Andreas,
Am 18.08.2015 um 13:46 schrieb Andreas Bießmann:
Dear Heiko Schocher,
Heiko Schocher h...@denx.de writes:
rename at91_spl_board_init into spl_board_init
Signed-off-by: Heiko Schocher h...@denx.de
---
Hi Lars,
On Tue, Aug 11, 2015 at 2:29 PM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Lars,
On Tue, Jul 28, 2015 at 11:01 AM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Lars,
On Tue, Jul 28, 2015 at 3:25 AM, Lars Poeschel poesc...@lemonage.de wrote:
Hi Joe,
On Wed, Jun
On Wed, Aug 12, 2015 at 07:31:44AM +0900, Masahiro Yamada wrote:
Just preparing for upcoming cleaning.
The board-specific linker script board/vpac270/u-boot-spl.lds
has been touched to avoid build error. It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.
On Mon, Aug 10, 2015 at 04:58:33PM +0530, Kishon Vijay Abraham I wrote:
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Cc: Roger Quadros rog...@ti.com
Cc: Tero Kristo t-kri...@ti.com
Cc: Nishanth Menon n...@ti.com
On Tue, Aug 11, 2015 at 07:57:09PM +0300, Vladimir Zapolskiy wrote:
A number of LPC32xx SLC NAND defines is dictated by controller
hardware limits and OOB layout is defined by operating system, the
definitions are common for all users. Since those macro are used
in out of NAND SLC driver code
On Wed, Aug 12, 2015 at 07:31:51AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Stefano Babic sba...@denx.de
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
On Wed, Aug 12, 2015 at 07:31:50AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital
On Wed, Aug 12, 2015 at 07:31:52AM +0900, Masahiro Yamada wrote:
We do not want to compile the DM remove code for SPL. Currently,
we undef it in include/config_uncmd_spl.h (for C files) and in
scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly.
This commit demonstrates how we
On Wed, Aug 12, 2015 at 07:31:47AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Stefano Babic sba...@denx.de
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
On Wed, Aug 12, 2015 at 07:31:49AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital
On 08/13/2015 11:54 PM, Yuan Yao wrote:
EDDRTQCFG Registers are Integration Strap values which controls
performance parameters for DDR Controller.
The bit 25 is used to disable priorities within DDR since DDR
are connected backwards on silicon Rev2.0.
Signed-off-by: Yuan Yao
On Tue, Aug 04, 2015 at 05:04:41PM -0400, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Updated the LPC32xx I2C driver to support
the OTG I2C that is part of the USB module.
Signed-off-by: Sylvain Lemieux slemi...@tycoint.com
Acked-by: Marek Vasut
On 08/13/2015 11:54 PM, Yuan Yao wrote:
For LS1021A Rev2.0 have already fixed the snoop silicon issue, So enable
snoop requests and DVM message requests for all the slave insterfaces.
Signed-off-by: Yuan Yao yao.y...@freescale.com
---
board/freescale/ls1021aqds/ls1021aqds.c | 8 +++-
On Tue, Aug 18, 2015 at 01:47:20PM -0500, Joe Hershberger wrote:
Hi Lars,
On Tue, Aug 11, 2015 at 2:29 PM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Lars,
On Tue, Jul 28, 2015 at 11:01 AM, Joe Hershberger
joe.hershber...@gmail.com wrote:
Hi Lars,
On Tue, Jul 28, 2015
On Wed, Aug 12, 2015 at 08:22:13PM +0300, Vladimir Zapolskiy wrote:
LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones
and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit
wide. This means that if HCLK is 104MHz, then minimal configurable I2C
clock speed is
On Wed, Aug 05, 2015 at 01:45:45AM +0200, Stefan Roese wrote:
On 04.08.2015 20:26, Scott Wood wrote:
On Tue, 2015-08-04 at 14:39 +0200, Stefan Roese wrote:
I've used these patches while porting the pxa3xx_nand driver for the
Marvell Armada XP / 38x SoC's to current U-Boot. And have found no
On Wed, Aug 12, 2015 at 08:32:08PM +0300, Vladimir Zapolskiy wrote:
The change adds a number of macro definitions used by USB OHCI driver,
if CONFIG_USB_OHCI_LPC32XX is selected from a board config file.
Signed-off-by: Vladimir Zapolskiy v...@mleia.com
Tested-by: Sylvain Lemieux
On Wed, Aug 12, 2015 at 07:31:54AM +0900, Masahiro Yamada wrote:
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
-
On Wed, Aug 12, 2015 at 07:31:53AM +0900, Masahiro Yamada wrote:
There is no case where defined(SPL_DISABLE_OF_CONTROL) is true.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Simon Glass s...@chromium.org
Applied to
-Original Message-
From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
Sent: Tuesday, August 18, 2015 5:44 AM
To: Marcel Ziswiler
Cc: U-Boot Mailing List; Tom Warren; Pantelis Antoniou; Tom Rini; Albert
Aribaud; Stephen Warren
Subject: Re: [PATCH 03/11] arm:
On 08/17/2015 02:42 AM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Freescale ARM-based Layerscape LS2085A contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on
On Mon, Aug 10, 2015 at 08:16:31AM -0400, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The
On Mon, Aug 10, 2015 at 10:45:14PM -0600, Stephen Warren wrote:
- Re-direct stderr into the log files, so any errors U-Boot emits are
visible in the logs. This is relevant if the reset shell command
attempts to report that it's not supported on the sandbox board.
- Fix test_fs_nonfs() to
On Wed, Aug 12, 2015 at 07:31:42AM +0900, Masahiro Yamada wrote:
Commit e02ee2548afe (kconfig: switch to single .config
configuration) made the configuration itself pretty simple,
instead, we lost the way to systematically enable/disable config
options for each image independently.
Our
On Thu, Aug 13, 2015 at 03:40:20PM -0400, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250
On Thu, Aug 13, 2015 at 03:40:21PM -0400, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)
This
On Wed, Aug 12, 2015 at 07:31:41AM +0900, Masahiro Yamada wrote:
If the target string matches CONFIG_, move the pointer p
forward. This saves several 7-chars adjustments.
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by:
On 08/17/2015 02:42 AM, yuantian.t...@freescale.com wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on
On Wed, Aug 12, 2015 at 07:31:48AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Aug 13, 2015 at 03:40:22PM -0400, slemieux.t...@gmail.com wrote:
From: Sylvain Lemieux slemi...@tycoint.com
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The
On Wed, Aug 12, 2015 at 07:31:45AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Aug 12, 2015 at 07:31:46AM +0900, Masahiro Yamada wrote:
Signed-off-by: Masahiro Yamada yamada.masah...@socionext.com
Reviewed-by: Tom Rini tr...@konsulko.com
Reviewed-by: Stefano Babic sba...@denx.de
Reviewed-by: Simon Glass s...@chromium.org
Applied to u-boot/master, thanks!
--
On Wed, Aug 12, 2015 at 07:31:43AM +0900, Masahiro Yamada wrote:
The previous commit introduced a useful macro used in makefiles,
in order to reference to different variables (CONFIG_... or
CONFIG_SPL_...) depending on the build context.
Per-image config option control is a PITA in C
On 8/10/15 6:03 PM, Marek Vasut wrote:
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested
On Tuesday, August 18, 2015 at 10:30:15 PM, Dinh Nguyen wrote:
On 8/10/15 6:02 PM, Marek Vasut wrote:
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
On Tuesday, August 18, 2015 at 10:27:29 PM, Dinh Nguyen wrote:
On 8/10/15 6:00 PM, Marek Vasut wrote:
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the
On Tuesday, August 18, 2015 at 10:44:24 PM, Dinh Nguyen wrote:
On 8/12/15 3:08 PM, Marek Vasut wrote:
On Tuesday, August 11, 2015 at 01:10:38 AM, Marek Vasut wrote:
This series cleans up the QTS-generated header files and cleans up
the SoCDK support such that they fit into the framework
From: Mingkai Hu mingkai...@freescale.com
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
Signed-off-by: York Sun york...@freescale.com
---
drivers/net/e1000.c |8
1 file changed,
Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS,
MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board
structure.
Signed-off-by: York Sun york...@freescale.com
---
include/configs/MPC8540ADS.h |3 +++
include/configs/MPC8541CDS.h |3 +++
On 8/10/15 5:59 PM, Marek Vasut wrote:
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be
used uninitialized in this function [-Wmaybe-uninitialized]
if
On 8/12/15 3:08 PM, Marek Vasut wrote:
On Tuesday, August 11, 2015 at 01:10:38 AM, Marek Vasut wrote:
This series cleans up the QTS-generated header files and cleans up
the SoCDK support such that they fit into the framework just like
any other SoCFPGA boards.
Marek Vasut (8):
arm:
Il 18/08/2015 15:33, Michael Trimarchi ha scritto:
Hi
On Tue, Aug 18, 2015 at 3:22 PM, r...@dave-tech.it wrote:
From: Andrea Scian andrea.sc...@dave.eu
MAX6373 is a simple WDT which is programmed its configuration pins
and reset via another pin, which is usually connected to a GPIO
On 8/10/15 6:00 PM, Marek Vasut wrote:
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.
Signed-off-by: Marek Vasut ma...@denx.de
---
On 8/10/15 6:02 PM, Marek Vasut wrote:
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.
Signed-off-by: Marek Vasut ma...@denx.de
---
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