Hello Simon,
I just noticed this while adding a Series-cc to my work address which
has parentheses: running patman (without -n) will result in
sh: 1: Syntax error: "(" unexpected
Which initially left me wondering what was happening until I realized
one of the Series-cc addresses had pare
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, January 27, 2016 1:05 PM
> To: Ramneek Mehresh
> Cc: Ramneek Mehresh ; u-
> b...@lists.denx.de; Simon Glass
> Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all
> fsl
> platforms
On Wednesday, January 27, 2016 at 09:26:08 AM, Ramneek Mehresh wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, January 27, 2016 1:05 PM
> > To: Ramneek Mehresh
> > Cc: Ramneek Mehresh ; u-
> > b...@lists.denx.de; Simon Glass
> > Subject: Re:
On the A83T and H3, the SID block is at a different address.
Furthurmore, the e-fuses are at an offset of 0x200 within the
hardware's address space.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/inc
Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.
The board also has an EEPROM on i2c0 whic
With recent changes spi node was moved to a place as a subnode under
pch, so update the alias to refer to its correct place as well.
Signed-off-by: Bin Meng
---
arch/x86/dts/bayleybay.dts | 4 ++--
arch/x86/dts/broadwell_som-6896.dts | 4 ++--
arch/x86/dts/chromebook_link.dts| 4 ++
Following changes have been made to enable secure boot:
1) Sec_init has been called in starting to initialize SEC Block (CAAM)
which will be used for Secure Boot validation later for both ls2080a qds
and rdb
2) 64Bit address in ESBC Header has been enabled as this SoC is based on
armv8
3) Secure Bo
When MMU is disabled, 64bit Write must be at a memory aligned at
64bit Boundary. So, this commit splits the 64bit write into 2 -32bit
writes as the memory location is not guaranteed to be 64bit aligned.
The alignment exception only occurs when MMU is disabled.
Signed-off-by: Aneesh Bansal
Signed-
For Secure Boot, a header is used to identify key table, signature
and image address. For LS-CH3, there is a new header structure being used.
The following changes are there in the new header:
1) Currently IE Table (Key extension) feature is not supported
2) Single Key feature is not supported. Ke
In case of fatal failure during secure boot execution (e.g. header not found)
it is needed that the execution stops.
Earlier, we were asserting reset request in case in case of failure. But if
the RESET_REQ is not tied off to HRESET, this allows the execution to continue.
This can either be taken
"fdt_high" env variable has been changed to 0xa000 for ls2080a
and ls2085a during Secure Boot. This env_varible is used to specify
the upper limit to be used for copying flat device tree.
This address must be visible to kernel.
The "fdt_high" value has been set during Secure Boot to same value
During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it is executed. This requires a header for bootscript.
When secure boot is enabled, default bootcmd is changed to first validate
bootscript using the header and
In LS2080/LS2085, SFP is LE and Ver is 3.4
The base address is 0x01e80200
SFP will be used in Secure Boot to read fuses.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 4
arch/arm/include/asm/arch-fsl-layerscape/immap_ls
To solve CAAM coherency issue on ls2080a and ls2085a.
When Caches are enabled and CAAM's DMA's AXI transcations are not
made cacheable, Core reads/write data from/to Caches and CAAM does from
Main Memory. This forces data flushes to synchronize various data structures
But even if any data in proxim
For secure boot, currently we were using fixed bootargs for
all SoCs. This is not needed and we can use the bootargs
which are used in non-secure boot.
Incase bootargs are not defined for non-secure boot of any
platform, we use default bootargs.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham
For ls2080, Added configs for various IPs used during secure boot
Added address and endianness for SEC and Security Monitor.
SRK - Fuses in SFP (Fused for public keys hash)
These are stored in LE format.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
arch/arm/include/asm/arch-fsl
Secure Boot ESBC has been enabled on FSL LS208x platforms.
This patchset is dependent on
http://patchwork.ozlabs.org/patch/571612/
Saksham Jain (14):
armv8: ls2080: Add SFP Configs for LS2080/LS2085
armv8: ls2080: Add Secure Boot configs: SEC, Security Monitor, SRK and
RCW
SECURE BOOT: A
During Secure Boot, a bootscript is validated using its header.
This patch copies both these images to DDR from NOR and then validates and
executed them from DDR. (If NOR is the boot source for LS2080 and LS2085).
This copy step is done to make this step common across booting sources.
Because in c
During secure boot, SMMU is enabled on POR by SP bootrom.
SMMU needs to be put in Bypass mode in uboot to
enable CAAM transcations to pass through.
During Nonsecure Boot, SP BootROM doesn't enable SMMU and
at reset SMMU is in bypass mode.
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
For validating images from uboot (Such as Kernel Image), either keys
from SoC fuses can be used or keys from a veriied table of public keys
can be used. The latter feature is called IE Key Extension Feature.
For earlier SoCs, BootROM used to verify IE Key Table and then write the
address of this t
The GUR (DCFG) registers in CCSR space are in LE format
for ls2080/ls2085. Defined a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: Aneesh Bansal
Signed-off-by: Saksham Jain
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 +++
1 f
Signed-off-by: Moritz Fischer
---
Hi Michal,
I was planning to use this in future to boot into recovery mode.
The change is small enough I feel that we could directly take it.
If you want to hold off until there's a user that's fine for me, too.
Cheers,
Moritz
---
arch/arm/mach-
On Wednesday, January 27, 2016 at 12:33:04 PM, Ramneek Mehresh wrote:
> > -Original Message-
> > From: Marek Vasut [mailto:ma...@denx.de]
> > Sent: Wednesday, January 27, 2016 1:57 PM
> > To: Ramneek Mehresh
> > Cc: Ramneek Mehresh ; u-
> > b...@lists.denx.de; Simon Glass
> > Subject: Re:
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Wednesday, January 27, 2016 1:57 PM
> To: Ramneek Mehresh
> Cc: Ramneek Mehresh ; u-
> b...@lists.denx.de; Simon Glass
> Subject: Re: [PATCH 2/2] include:configs: Add usb device-tree fixup for all
> fsl
> platforms
This patch series enables adds support for dma driver model and
to adopt driver model. This has been tested on am437x-sk evm
(logs [1]).
also pushed a branch for testing [2]
[1]: http://pastebin.ubuntu.com/14678498/
[2]: git://git.ti.com/~mugunthanvnm/ti-u-boot/mugunth-ti-u-boot.git dma-v3
change
Add TI_EDMA3 entry on Kconfig with help description.
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/dma/Kconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 58cb6e9..1b92c77 100644
--- a/drivers/dma/Kconfig
+++ b/d
Implement a DMA uclass so that the devices like ethernet, spi,
mmc etc can offload the data transfers from/to the device and
memory.
Signed-off-by: Mugunthan V N
---
drivers/dma/Kconfig | 15 +
drivers/dma/Makefile | 2 ++
drivers/dma/dma-uclass.c | 72 +
Add dma memcpy api to the default spi_flash_copy_mmap(), so that
dma will be used to copy data when CONFIG_DMA is defined for the
platform.
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/mtd/spi/spi_flash.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/
When CONFIG_DMA is defined the default spi_flash_copy_mmap() can
handle dma memory copy, so compile out spi_flash_copy_mmap() from
ti_qspi driver when CONFIG_DMA config is defined.
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/spi/ti_qspi.c | 2 +-
1 file changed, 1 insertio
enable dma driver model for am437x_sk_evm as ti-edma3 supports
driver model
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
configs/am437x_sk_evm_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/am437x_sk_evm_defconfig b/configs/am437x_sk_evm_defconfig
index 9eb41
adopt ti-edma3 driver to device driver model
Signed-off-by: Mugunthan V N
Reviewed-by: Simon Glass
---
drivers/dma/ti-edma3.c | 74 --
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/ti-edma3.c b/drivers/dma/ti-edma3.c
i
On 25.01.2016 07:06, Wenyou Yang wrote:
> From: Josh Wu
>
> Also align the open parenthesis.
>
> Signed-off-by: Josh Wu
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
> ---
>
> Changes in v2: None
>
> drivers/mtd/nand/atmel_nand.c |4 ++--
> 1 file changed, 2 insertions(+
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 5/7] enable chain of trust for ARM platforms
>
> C
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 1/7] include/configs: make secure boot header file
>
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 2/7] include/configs: move definition of
> CONFIG_C
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 7/7] SECURE_BOOT: change error handler for
> esbc_v
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 4/7] create function to determine boot mode
>
> A
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 3/7] SECURE_BOOT: split the secure boot functionali
> -Original Message-
> From: Aneesh Bansal [mailto:aneesh.ban...@nxp.com]
> Sent: Friday, January 22, 2016 4:37 PM
> To: u-boot@lists.denx.de
> Cc: york sun ; Ruchika Gupta
> ; Prabhakar Kushwaha
> ; Aneesh Bansal
>
> Subject: [PATCH v3 6/7] enable chain of trust for PowerPC platforms
>
* 829520: Code bounded by indirect conditional branch might corrupt
instruction stream,
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor
* 833471: VMSR FPSCR functional failure or deadlock
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush
Signed-
Dear Gregory CLEMENT,
Gregory CLEMENT writes:
>Timing issue occurs on eMMC not only when modifying the frequency but
>also for all the switch command(CMD6). According to the MMC spec waiting
>8 clocks after a switch command would be the thing to do.
>
>This patch allows fixing CPU hang observed w
Dear Gregory CLEMENT,
Gregory CLEMENT writes:
>During the initialization of PHY the gigabit bit capable is set if the
>controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
>configured to support only 10/100.
>
>Improperly setting the GBE capability leads to an unresponsive MAC
>contr
Dear Wenyou Yang,
Wenyou Yang writes:
>From: Josh Wu
>
>Since ecc_{strength,step}_ds is introduced in nand_chip structure for
>minimum ecc requirements. So we can use them directly and remove our
>own get_onfi_ecc_param function.
>
>Signed-off-by: Josh Wu
>Reviewed-by: Andreas Bießmann
>Signed
Dear Wenyou Yang,
Wenyou Yang writes:
>From: Josh Wu
>
>As atmel_nand_ecc.h is sync with v4.1 kernel, which adds the
>PMECC_OOB_RESERVED_BYTES. So use it in the driver.
>
>Signed-off-by: Josh Wu
>Reviewed-by: Andreas Bießmann
>Signed-off-by: Wenyou Yang
>---
>
>Changes in v2:
> - following An
Dear Wenyou Yang,
Wenyou Yang writes:
>From: Josh Wu
>
>Also align the open parenthesis.
>
>Signed-off-by: Josh Wu
>Signed-off-by: Wenyou Yang
>Reviewed-by: Andreas Bießmann
>---
>
>Changes in v2: None
>
> drivers/mtd/nand/atmel_nand.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletion
On Wed, 2016-01-27 at 00:01 +, Trent Piepho wrote:
> On Fri, 2015-11-27 at 15:22 +0800, Chin Liang See wrote:
> > Enable SDMMC calibration to determine the best setting for
> > drvsel and smplsel. Calibration will be triggered if the
> > drvsel and smplsel node are not available in DTS.
>
> We
On 27.1.2016 12:22, Moritz Fischer wrote:
> Signed-off-by: Moritz Fischer
> ---
> Hi Michal,
>
>I was planning to use this in future to boot into recovery mode.
>The change is small enough I feel that we could directly take it.
>If you want to hold off until there's a user that's fine
On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> On 01/21/2016 10:31 AM, Marek Vasut wrote:
> > On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård wrote:
> > > Tom Rini writes:
> > > > On Wed, Jan 20, 2016 at 08:31:30PM +, Måns Rullgård wrote:
> > > > > I'm having a problem wit
On 27.01.2016 03:04, Wenyou Yang wrote:
> Due to introducing the new PLLB clock handle functions,
> use these functions to clean up the PLLB enable/disable code.
>
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
> ---
>
> Changes in v2:
> - add return value for timeout checking at
Chin Liang See writes:
> On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>> On 01/21/2016 10:31 AM, Marek Vasut wrote:
>> > On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård wrote:
>> > > Tom Rini writes:
>> > > > On Wed, Jan 20, 2016 at 08:31:30PM +, Måns Rullgård wrote:
>>
Hi Michal,
On Wed, Jan 27, 2016 at 2:15 PM, Michal Simek wrote:
> On 27.1.2016 12:22, Moritz Fischer wrote:
>> Signed-off-by: Moritz Fischer
>> ---
>> Hi Michal,
>>
>>I was planning to use this in future to boot into recovery mode.
>>The change is small enough I feel that we could direct
On Wed, Jan 27, 2016 at 07:18:13AM +, Aneesh Bansal wrote:
> > -Original Message-
> > From: Tom Rini [mailto:tr...@konsulko.com]
> > Sent: Monday, January 25, 2016 9:06 PM
> > To: Aneesh Bansal
> > Cc: u-boot@lists.denx.de; Ruchika Gupta
> > Subject: Re: [U-Boot] [PATCH v3 0/7] Determ
On Wed, 2016-01-27 at 13:46 +, Måns Rullgård wrote:
> Chin Liang See writes:
>
> > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
> > > > On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård
> > > > wrote:
> > > > > Tom Rini writ
Chin Liang See writes:
> On Wed, 2016-01-27 at 13:46 +, Måns Rullgård wrote:
>> Chin Liang See writes:
>>
>> > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
>> > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
>> > > > On Thursday, January 21, 2016 at 05:20:33 PM, Måns Rullgård
>> > >
On Wed, 2016-01-27 at 14:18 +, Måns Rullgård wrote:
> Chin Liang See writes:
>
> > On Wed, 2016-01-27 at 13:46 +, Måns Rullgård wrote:
> > > Chin Liang See writes:
> > >
> > > > On Fri, 2016-01-22 at 10:35 -0600, Dinh Nguyen wrote:
> > > > > On 01/21/2016 10:31 AM, Marek Vasut wrote:
>
Hi Marek,
On Wed, 2016-01-27 at 03:14 +0100, Marek Vasut wrote:
> Some architectures, like MIPS, require remapping of the registers.
> Add the map_physmem() call to handle it.
>
> Signed-off-by: Marek Vasut
> Cc: Daniel Schwierzeck
> Cc: Hans de Goede
> Cc: Masahiro Yamada
> Cc: Alexey Brodki
Am 27.01.2016 um 03:13 schrieb Marek Vasut:
> This patch makes sure that the flush/invalidate_dcache_range() functions
> can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
> This call is valid and is happily produced by USB EHCI code for example.
> The expected behavior o
From: Matthias Michel
New features for smartweb:
* switch to hush command parser
* change autoboot stop to
* allow to write ethaddr
Signed-off-by: Matthias Michel
Reviewed-by: Samuel Egli
Cc: Roger Meier
Cc: Heiko Schocher
---
configs/smartweb_defconfig | 5 -
include/configs/smartweb
Hi Bin,
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
> ---
>
> board/freescale/bsc9132qds/bsc9132qds.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/board/fr
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> Clean up the tsec and fsl_mdio driver codes a little bit, by:
> - Fix misuse of tab and space here and there
> - Use correct multi-line comment format
> - Replace license identifier to GPL-2.0+
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershber
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> At present rx_idx and tx_idx are declared as static variables
> in the driver codes. To support multiple interfaces, move it to
> struct tsec_private.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
__
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> Adjust static functions in a proper order so that forward declaration
> of tsec_send() can be avoided.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> rxbd and txbd are declared static with 8 byte alignment requirement,
> but they can be put into struct tsec_private as well and are natually
> aligned to 8 byte.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
___
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> Adapted from the same file name in the kernel device tree bindings
> documentation, to use with U-Boot.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> This adds driver model support to Freescale TSEC ethernet driver.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
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On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver,
> it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we
> can get this from device tree. Update the bindings doc as well.
>
> Signed-off-by: Bin Meng
Acked-by: J
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> eth_get_dev_by_index() is an API which is not available in driver
> model. Use eth_get_dev_by_name() instead, which can also simplifly
> the code logic a little bit.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
___
Hi Bin,
On Mon, Jan 25, 2016 at 8:45 PM, Bin Meng wrote:
> On Wed, Jan 20, 2016 at 1:16 AM, york sun wrote:
>> On 01/17/2016 09:16 PM, Bin Meng wrote:
>>> Joe, York,
>>>
>>> On Tue, Jan 12, 2016 at 2:41 PM, Bin Meng wrote:
This series adds driver model ethernet support to the Freescale
>>>
On Tue, Jan 12, 2016 at 12:41 AM, Bin Meng wrote:
> For internal routines like redundant_init(), startup_tsec() and
> init_phy(), change to use tsec_private pointer as the parameter.
>
> Signed-off-by: Bin Meng
Acked-by: Joe Hershberger
___
U-Boot mai
Hello Moritz,
On Wed, 27 Jan 2016 14:53:30 +0100, Moritz Fischer
wrote:
> Hi Michal,
>
> On Wed, Jan 27, 2016 at 2:15 PM, Michal Simek wrote:
> > On 27.1.2016 12:22, Moritz Fischer wrote:
> >> Signed-off-by: Moritz Fischer
> >> ---
> >> Hi Michal,
> >>
> >>I was planning to use this in fut
On Tue, Jan 12, 2016 at 3:55 AM, wrote:
> From: Shaohui Xie
>
> Current driver always performs a phy soft reset when connecting the phy
> device, but soft reset is not always supported by a phy device, so
> introduce a quirk PHY_BROKEN_RESET to let such a phy device to skip soft
> reset. This co
On Tue, Jan 12, 2016 at 3:55 AM, wrote:
> From: Shaohui Xie
>
> Cortine phy cannot support soft reset, this commit implements probe
> for Cortina PHY to tell phylib to skip phy soft reset by setting
> PHY_BROKEN_RESET in flags.
>
> Signed-off-by: Shaohui Xie
Acked-by: Joe Hershberger
Hi Tom,
here is the branch with xilinx changes which are flying around.
It is targeting PowerPC, Microblaze, ARM and ARM64.
I can't see any build problem via buildman.
Thanks,
Michal
The following changes since commit 9e4de7fd4acc8f99b6d383c711d21c0159849629:
Merge branch 'master' of http://
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> From: Florian Fainelli
>
> When a Gigabit PHY device is connected to a 10/100Mbits capable Ethernet
> MAC, the driver will restrict the phydev->supported modes to mask off
> Gigabit. If the Gigabit PHY comes out of reset with the Gigabit fe
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> From: Sascha Hauer
>
> of_set_phy_supported allows overwiting hardware capabilities of
> a phy with values from the devicetree. This does not work with
> the genphy driver though because the genphys config_init function
> will overwrite all
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> From: Florian Fainelli
>
> Breakdown the PHY_*_FEATURES into per speed defines such that we can
> easily re-use them individually.
>
> Signed-off-by: Florian Fainelli
> Signed-off-by: Alexey Brodkin
> Cc: Joe Hershberger
Acked-by: Joe H
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> This will be used for getting max speed mode of Ethernet interface that
> a particular MAC supports from Device Tree blob and later being used for
> phy configuration.
>
> Signed-off-by: Alexey Brodkin
> Cc: Joe Hershberger
Acked-by: Joe
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> This new function will allow MAC drivers to override supported
> capabilities of the phy. It is required when MAC cannot handle all
> speeds supported by phy.
>
> For example phy supports up-to 1Gb connections while MAC may only work
> in mo
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> Current implementation only sets "port select" bit for non-1Gb mode.
> That works fine if GMAC has just exited reset state but we may as well
> change connection mode in runtime. Then we'll need to reprogram GMAC for
> that new mode of opera
On Wednesday, January 27, 2016 at 03:56:36 PM, Daniel Schwierzeck wrote:
> Am 27.01.2016 um 03:13 schrieb Marek Vasut:
> > This patch makes sure that the flush/invalidate_dcache_range() functions
> > can handle corner-case calls like this -- invalidate_dcache_range(0, 0,
> > 0); This call is valid
On Wednesday, January 27, 2016 at 03:21:17 PM, Alexey Brodkin wrote:
> Hi Marek,
Hi,
> On Wed, 2016-01-27 at 03:14 +0100, Marek Vasut wrote:
> > Some architectures, like MIPS, require remapping of the registers.
> > Add the map_physmem() call to handle it.
> >
> > Signed-off-by: Marek Vasut
> >
On Wed, Jan 13, 2016 at 7:59 AM, Alexey Brodkin
wrote:
> This property allows to specify fastest connection mode supported by
> the MAC (as opposed to features of the phy).
>
> There are situations when phy may handle faster modes than the
> MAC (or even it's particular implementation or even due
Hi Wenyou,
On 10.12.2015 03:20, Wenyou Yang wrote:
> To reduce the duplicated code, add a new file to accommodate
> the peripheral's and system's clock handle code, shared with
> the SoCs with different ARM core.
>
> Signed-off-by: Wenyou Yang
> ---
>
> Changes in v3:
> - fix incorrectly used
Hi Joe,
Thanks for the review. ACK to all comments. A few clarifications are
included below. I will submit a v3, including multichip addressing for
Albert's platform.
On 01/26/2016 06:11 PM, Joe Hershberger wrote:
>> + int reg, u16 data)
>> +{
>> + struct mii_dev *phys_bu
Hi Wenyou,
On 10.12.2015 03:20, Wenyou Yang wrote:
> Due to introducing the new peripheral clock handle functions,
> use these functions to clean up the duplicated code.
>
> Meanwhile, remove unneeded header file include, at91_pmc.h.
>
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
On 10.12.2015 03:20, Wenyou Yang wrote:
> Remove unnecessary #ifdef CPU_HAS_PCR.
>
> Signed-off-by: Wenyou Yang
Reviewed-by: Andreas Bießmann
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> arch/arm/mach-at91/include/mach/at91_pmc.h |8 ++--
> 1 file changed, 2 insertions(+)
Hi Joe,
On Tue, 2016-01-19 at 07:02 +, Alexey Brodkin wrote:
> Hi Joe,
>
> On Wed, 2016-01-13 at 16:59 +0300, Alexey Brodkin wrote:
> > In some cases Ethernet PHY and network itself might support speeds
> > which are not supported by Ethernet controller (MAC).
> >
> > To support that kind of
On 01/03/2016 07:12 PM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> This patch also exposes the complete DDR region(s) to Linux.
>
> Signed-off-by: Shaohui Xie
> ---
> board/freescale/ls1043aqds/ddr.c| 19 ---
> board/freescale/ls1043aqds/ls1043aqds.c | 10
On 12/31/2015 02:38 AM, Gong Qianyu wrote:
> From: Gong Qianyu
>
> Signed-off-by: Gong Qianyu
> ---
> V2:
> - No change.
>
> include/configs/ls1043aqds.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-fsl-qoriq master. Awaiting upstream.
Thanks.
York
__
On 12/31/2015 02:37 AM, Gong Qianyu wrote:
> From: Gong Qianyu
>
> 1.Use "qixis_reset sd" to boot from SD
> 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
> 3.Use "qixis_reset qspi" to boot from QSPI flash
>
> On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
> pin-m
On 12/24/2015 03:55 AM, Prabhakar Kushwaha wrote:
> SYSCLK frequency is dependent on on-board switch settings. It may
> vary as per requirement. boot-loader is aware of board switch
> configurations.
>
> So Fixup Linux device tree from boot-loader.
>
> Signed-off-by: Prabhakar Kushwaha
> CC: Min
On 12/31/2015 02:38 AM, Gong Qianyu wrote:
> From: Gong Qianyu
>
> Signed-off-by: Gong Qianyu
> ---
> V2:
> - No change.
>
> include/configs/ls1043aqds.h | 4
> 1 file changed, 4 insertions(+)
>
Applied to u-boot-fsl-qoriq master. Awaiting upstream.
Thanks.
York
___
On 12/16/2015 12:53 AM, Shengzhou Liu wrote:
> Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
> before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
> to the desired value after DDR initialization has completed.
>
> When DDR controller is configured to operate
On 01/05/2016 07:34 PM, Shengzhou Liu wrote:
> During the receive data training, the DDRC may complete on a
> non-optimal setting that could lead to data corruption or
> initialization failure.
>
> Workaround: before setting MEM_EN, set DEBUG_29 register with
> specific value for different data ra
On 12/15/2015 09:58 PM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Updated the default sata register values to enhance the
> performance and stability.
>
> Signed-off-by: Tang Yuantian
> ---
> arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c | 10 +-
> 1 file changed, 5 inse
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