Hi,
I'm trying to figure out how it is possible easily update u-boot in
nand on custom imx7 board. I can start u-boot using imx_usb tool. I
came from ti am33xx world where I simply get u-boot.img from tftp
server and store it to beginning of flash (after SPL offset).
According imx7 datasheet for
So, in a single day we independently submitted two almost identical
patches. The patch is pretty obvious, but two in a day is still a cool
coincidence.
--
Yaroslav
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Some arguments don't need to pass to sdhci_setup_cfg.
Generic variable can be used in sdhci_setup_cfg, and some arguments are
already included in sdhci_host struct.
It's enough that just pass the board specific things to sdhci_setup_cfg().
After removing the unnecessary arguments, it's more simple
buswidth isn't used anywhere in sdhci_setup_cfg.
Signed-off-by: Jaehoon Chung
Reviewed-by: Minkyu Kang
Reviewed-by: Simon Glass
---
Changes for V2:
- None
drivers/mmc/msm_sdhci.c | 4 ++--
drivers/mmc/sdhci.c | 4 ++--
drivers/mmc/zynq_sdhci.c | 2 +-
include/sdhci.h |
Simon, Stefan,
On Tue, Jul 26, 2016 at 8:13 PM, Stefan Roese wrote:
> Hi Simon,
>
> On 25.07.2016 04:07, Simon Glass wrote:
>>
>> On 28 June 2016 at 07:44, Stefan Roese wrote:
>>>
>>> This patch adds support for the SMBus block read/write functionality.
>>> Other protocols like the SMBus quick c
When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compiler error for -Wunused-but-set-variable
Signed-off-by: Jaehoon Chung
---
drivers/mmc/sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 6010
Sorry, discard this..
I will resend the patch with commit msg.
On 08/05/2016 02:07 PM, Jaehoon Chung wrote:
> When disabled CONFIG_MMC_SDMA, variable caps didn't use.
> This patch fixes the compl
>
> Signed-off-by: Jaehoon Chung
> ---
> drivers/mmc/sdhci.c | 2 +-
> 1 file changed, 1 insertion(
When disabled CONFIG_MMC_SDMA, variable caps didn't use.
This patch fixes the compl
Signed-off-by: Jaehoon Chung
---
drivers/mmc/sdhci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 60108fd..7ddb549 100644
--- a/drivers/mmc/s
On 07/28/2016 11:25 AM, Xu Ziyuan wrote:
> This patch fixes data starvation by host timeout(HTO) error interrupt
> which occurred under FIFO mode transfer on rk3036 board.
>
> The former implement, the actual bytes were transmitted may be less than
> should be. The size will still subtract value o
On 07/28/2016 11:25 AM, Xu Ziyuan wrote:
> The former implement, dw_mmc will push and pop the redundant data to
> FIFO, we should transfer it according to the real size.
>
> Signed-off-by: Ziyuan Xu
> Acked-by: Jaehoon Chung
> Reviewed-by: Simon Glass
> Reviewed-by: Shawn Lin
Applied on u-bo
On 07/28/2016 02:26 PM, Jaehoon Chung wrote:
> According to DesignWare TRM, FIFO_COUNT is bit[29:17].
> If get the correct fifo_count value, it has to use the FIFO_MASK
> as 0x1FFF, not 0x1FF.
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Ziyuan Xu
Applied on u-boot-mmc. Thanks!
Best Regar
On 07/19/2016 04:33 PM, Jaehoon Chung wrote:
> Use the generic error number instead of specific error number.
> If use the generic error number, it can debug more easier.
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Simon Glass
> Reviewed-by: Minkyu Kang
Applied on u-boot-mmc. Thanks!
Bes
On 07/23/2016 12:11 PM, Xu Ziyuan wrote:
> From: Xu Ziyuan
>
> It's nicer to see this:
>
> => mmc list
> dwmmc@ff0c: 0
> dwmmc@ff0f: 1 (eMMC)
>
> than this:
>
> => mmc list
> dwmmc@ff0c: 0dwmmc@ff0f: 1 (eMMC)
>
> With the former, it's much clearer which mmc devices are on.
>
On 07/26/2016 07:03 PM, Jaehoon Chung wrote:
> This "commit 429790026021d522d51617217d4b86218cca5750" is wrong.
> SDHCI_QUIRK_NO_HISPD_BIT is for skipping to set CTRL_HISPD bit.
>
> For example, Exynos didn't have CTRL_HISPD. But Highspeed mode
> is supported.
> (This quirks doesn't mean that dri
On 07/19/2016 04:33 PM, Jaehoon Chung wrote:
> is already included in .
> It can use instead of
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Simon Glass
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/dw_mmc.c| 1 -
> drivers/mmc/exynos_dw_mmc.c
On 07/19/2016 04:33 PM, Jaehoon Chung wrote:
> "mmc.h" is already included. It's duplicated.
>
> Signed-off-by: Jaehoon Chung
> Reviewed-by: Simon Glass
Applied on u-boot-mmc. Thanks!
Fixed the typo, when applied.
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/fsl_esdhc.c | 1 -
> 1 file
On 07/12/2016 09:18 PM, Jaehoon Chung wrote:
> Unset the SDHCI_QUIRK_BROKEN_R1B for exynos SoC.
> (Tested on Exynos4 Boards.)
Applied on u-boot-mmc. Thanks!
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Jaehoon Chung
> Acked-by: Lukasz Majewski
> Tested-by: Lukasz Majewski
> ---
> drivers/
On 07/12/2016 09:18 PM, Jaehoon Chung wrote:
> There is no data, it doesn't needs to wait for completing data transfer.
> (It seems that it can be removed.)
> Almost all timeout error is occured from stop command without data.
> After applied this patch, I hope that we don't need to increase timeou
Hi
On 07/10/2016 12:40 AM, Masahiro Yamada wrote:
> The current timeout detection logic is not very nice; it calls
> get_timer(start) in the while() loop, and then calls it again after
> the loop to check if a timeout error happened.
>
> Because of the time difference between the two calls of get
Hi
2016-08-05 9:36 GMT+08:00 Simon Glass :
> Hi Gregory,
>
> On 3 August 2016 at 21:21, Gregory Ray wrote:
>> Hello,
>>
>> Is SecureBoot from the manufacturers u-boot distribution operational? When I
>> try to sign the loader using the SBC it complains "Sign loader failed!"
>>
>> I did a standard
We can pass all the variables down to the functions that need them, and
then everything is on the stack. This is safer than using the data section.
At least on firefly-rk3288, the code size is the same and the data size is
12 bytes smaller:
before:
188652636 40 215415425 b/firefl
Recently I have seen mails not reaching mailing list many times. Not sure if it
was our email server issue.
York
Original Message
From: Simon Glass
Sent: Thursday, August 4, 2016 06:37 PM
To: Wenbin Song
Subject: Re: [PATCH] pxe: Fix pxe boot with FIT image
CC: Bin Meng ,Hei
+Tom
On 4 August 2016 at 01:44, Wenbin song wrote:
> From: York Sun
>
> When FIT image is used, a single image provides kernel, device
> tree and optionally ramdisk. Argc and argv need to be adjusted
> to support this.
>
> Signed-off-by: York Sun
> ---
> cmd/pxe.c | 9 +
> 1 file chang
Hi Stephen,
On 4 August 2016 at 12:52, Stephen Warren wrote:
> On 08/03/2016 07:16 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 1 August 2016 at 09:22, Stephen Warren wrote:
>>>
>>> On 07/31/2016 07:02 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:48, Ste
Hi Stephen,
On 1 August 2016 at 14:52, Stephen Warren wrote:
> From: Stephen Warren
>
> Some code may want to read reg values from DT, but from nodes that aren't
> associated with DM devices, so using dev_get_addr_index() isn't
> appropriate. In this case, fdtdec_get_addr_size_*() are the functi
On 3 August 2016 at 21:40, Kever Yang wrote:
> To compatible with distro boot, we need to add gpt and fs support,
> including gpt table and vfat, ext2, ext4 support.
>
> Signed-off-by: Kever Yang
> Reviewed-by: Simon Glass
> ---
>
> Changes in v2:
> - remove some re-defined MACRO, comments from
Hi Paul,
On 4 August 2016 at 04:24, Paul Burton wrote:
>
>
> On 04/08/16 10:54, Michal Simek wrote:
>>
>> On 1.8.2016 12:06, Paul Burton wrote:
>>>
>>> This patch adds a driver for the Xilinx AXI bridge for PCI express, an
>>> IP block which can be used on some generations of Xilinx FPGAs. This i
Hi Gregory,
On 3 August 2016 at 21:21, Gregory Ray wrote:
> Hello,
>
> Is SecureBoot from the manufacturers u-boot distribution operational? When I
> try to sign the loader using the SBC it complains "Sign loader failed!"
>
> I did a standard make:
>
> CROSS_COMPILE=/Developer/arm-eabi-4.8/bin/ar
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> The implementations of clk_get_by_index & clk_get_by_name are only
> available when CONFIG_CLK is enabled. Provide the dummies when this is
> not the case in order to avoid build failures.
Where are the dummies?
>
> Signed-off-by: Paul Bu
Hi Stephen,
On 1 August 2016 at 09:46, Stephen Warren wrote:
> On 07/31/2016 07:02 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 27 July 2016 at 15:24, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP
>>> (B
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> Previously ns16550 compatible UARTs probed via device tree have needed
> their device tree nodes to contain a clock-frequency property. An
> alternative to this commonly used with Linux is to reference a clock via
> a phandle. This patch al
Hi Stephen,
On 25 July 2016 at 13:57, Stephen Warren wrote:
> On 07/22/2016 08:08 PM, Simon Glass wrote:
>>
>> Hi Stephen,
>>
>> On 18 July 2016 at 12:17, Stephen Warren wrote:
>>>
>>> From: Stephen Warren
>>>
>>> IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter
>>> Processo
Hi Paul,
On 4 August 2016 at 04:29, Paul Burton wrote:
> Device model drivers have previously been matched to FDT nodes by virtue
> of being the first driver in the driver list to be compatible with the
> node. This ignores the fact that compatible strings in the device tree
> are listed in order
On 3 August 2016 at 23:41, Stefan Agner wrote:
> From: Stefan Agner
>
> The page table is maintained by the CPU, hence it is safe to always
> align cache flush to a whole cache line size. This allows to use
> mmu_page_table_flush for a single page table, e.g. when configure
> only small regions t
Hi Stefan,
On Thu, Aug 4, 2016 at 2:41 AM, Stefan Agner wrote:
> - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
> +
> + /*
> +* Make sure range is cache line aligned
> +* Only CPU maintains page tables, hence it is save to always
s/save/safe
Convert the driver to the driver model while retaining the existing
legacy code. This allows the driver to support boards that have
converted to driver model as well as those that have not.
Signed-off-by: Wenyou Yang
Reviewed-by: Simon Glass
Reviewed-by: Jaehoon Chung
Reviewed-by: Heiko Schoche
Add driver model support while retaining the existing legacy code.
This allows the driver to support boards that have converted to
driver model as well as those that have not.
Signed-off-by: Wenyou Yang
Acked-by: Simon Glass
---
Changes in v3:
- Change clk_client.h -> clk.h to adapt to clk API
> On 04 Aug 2016, at 20:11, Stephen Warren wrote:
>
> On 08/04/2016 01:11 AM, Alexander Graf wrote:
>> On the raspberry pi, you can disable the serial port to gain dynamic
>> frequency
>> scaling which can get handy at times.
>>
>> However, in such a configuration the serial controller gets it
On Thu, Aug 4, 2016 at 4:34 PM, Joe Hershberger
wrote:
> On Thu, Aug 4, 2016 at 4:22 PM, Joe Hershberger
> wrote:
>> Hi Stephen,
>>
>> On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren
>> wrote:
>>> On 08/01/2016 09:20 PM, Peter Chubb wrote:
Hi Folks,
Since patch 96350f729c
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Thursday, August 04, 2016 11:59 AM
> To: Simon Glass
> Cc: U-Boot Mailing List ; Tom Warren
> ; Stephen Warren ; Pantelis
> Antoniou
> Subject: Re: [PATCH 8/9] mmc: tegra: port to standard clock/r
On Thu, Aug 4, 2016 at 4:22 PM, Joe Hershberger
wrote:
> Hi Stephen,
>
> On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren wrote:
>> On 08/01/2016 09:20 PM, Peter Chubb wrote:
>>>
>>>
>>> Hi Folks,
>>>Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to
>>>driver model for Ethe
Hi Stephen,
On Tue, Aug 2, 2016 at 11:56 AM, Stephen Warren wrote:
> On 08/01/2016 09:20 PM, Peter Chubb wrote:
>>
>>
>> Hi Folks,
>>Since patch 96350f729c42 "dm: tegra: net: Convert tegra boards to
>>driver model for Ethernet" booting via dhcp has been broken on the
>>Jetson TK1.
>
>
On Thu, Aug 04, 2016 at 10:58:30PM +0300, Siarhei Siamashka wrote:
> On Thu, 4 Aug 2016 11:40:25 -0400
> Tom Rini wrote:
>
> > On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> > > On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > > > Hi,
> > > >
> > > > On 04/08/16
Hi Max,
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Implement MDIO bus read/write functions, initialize the bus and scan for
> the PHY when phylib is enabled. Limit PHY speeds to 10/100 Mbps.
>
> Cc: Michal Simek
> Signed-off-by: Max Filippov
> ---
> drivers/net/ethoc.c | 152
>
On 04/08/16 20:58, Siarhei Siamashka wrote:
> On Thu, 4 Aug 2016 11:40:25 -0400
> Tom Rini wrote:
Hi,
thanks Siarhei for the answer and the explanation!
>
>> On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
>>> On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
>>
On Thu, 4 Aug 2016 11:40:25 -0400
Tom Rini wrote:
> On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> > On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > > Hi,
> > >
> > > On 04/08/16 16:01, Tom Rini wrote:
> > > > Hey guys,
> > > >
> > > > I just started trying
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> The ethoc device can be configured to have a private memory region
> instead of having access to the main memory. In that case egress packets
> must be copied into that memory for transmission and pointers to that
> memory need to be passed to
On 08/04/2016 01:11 AM, Alexander Graf wrote:
On the raspberry pi, you can disable the serial port to gain dynamic frequency
scaling which can get handy at times.
However, in such a configuration the serial controller gets its rx queue filled
up with zero bytes which then happily get transmitted
On 08/03/2016 07:16 PM, Simon Glass wrote:
Hi Stephen,
On 1 August 2016 at 09:50, Stephen Warren wrote:
On 07/31/2016 08:20 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:24, Stephen Warren wrote:
From: Stephen Warren
Tegra186 supports the new standard clock and reset APIs. O
On 08/03/2016 07:16 PM, Simon Glass wrote:
Hi Stephen,
On 1 August 2016 at 09:22, Stephen Warren wrote:
On 07/31/2016 07:02 PM, Simon Glass wrote:
Hi Stephen,
On 27 July 2016 at 15:48, Stephen Warren wrote:
From: Stephen Warren
Tegra186 supports the new standard clock, reset, and power
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Addresses used in buffer descriptors and passed in platform data or
> device tree are physical. Addresses used by CPU to access packet data
> and registers are virtual. Don't mix these addresses and use virt_to_phys
> for translation.
>
> Signe
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Add .of_match table and .ofdata_to_platdata callback to allow for ethoc
> device configuration from the device tree.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
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U-Boot mailing lis
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Extract reusable parts from ethoc_init, ethoc_set_mac_address,
> ethoc_send and ethoc_receive, move the rest under #ifdef CONFIG_DM_ETH.
> Add U_BOOT_DRIVER, eth_ops structure and implement required methods.
>
> Signed-off-by: Max Filippov
A
On Wed, Aug 03, 2016 at 07:43:24PM -0700, Stefan Agner wrote:
> On 2016-08-03 16:18, Joe Hershberger wrote:
> > On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
> >> From: Stefan Agner
> >>
> >> Flush loaded data cacheline aligned. This avoids warnings such as
> >> CACHE: Misaligned operation
On Thu, Aug 04, 2016 at 12:10:33PM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> > Hello,
> >
> > this series does the following improvements to the OpenCores 10/100 Mbps
> > driver:
> > - add Kconfig symbol for the driver;
> > - add DM_ETH supp
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Don't use physical base address of registers directly, ioremap it first.
> Save pointer in private struct ethoc and use that struct in all internal
> functions.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
__
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Add Kconfig entry for the driver, remove #define CONFIG_ETHOC from the
> only board configuration that uses it and put it into that board's
> defconfig.
>
> Cc: Stefan Kristiansson
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
___
Hi Tom,
On Tue, Aug 2, 2016 at 6:31 AM, Max Filippov wrote:
> Hello,
>
> this series does the following improvements to the OpenCores 10/100 Mbps
> driver:
> - add Kconfig symbol for the driver;
> - add DM_ETH support;
> - add device tree support;
> - add optional phylib support;
> - add support
On 2016-08-04 09:14, Joe Hershberger wrote:
> Hi Simon,
>
> On Wed, Aug 3, 2016 at 8:17 PM, Simon Glass wrote:
>> Hi Joe,
>>
>> On 3 August 2016 at 17:18, Joe Hershberger wrote:
>>> On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
From: Stefan Agner
Flush loaded data cachelin
On Tue, May 17, 2016 at 12:11 AM, Wenyou Yang wrote:
> Use the right phy_connect() prototype for CONFIGF_DM_ETH.
> Support to get the phy interface from dt and set GMAC_UR.
>
> Signed-off-by: Wenyou Yang
> ---
> This patch is based on the patch set,
> [PATCH 00/18] at91: Convert Ethernet and LCD
On Wed, Jul 27, 2016 at 7:57 PM, Max Filippov wrote:
> print_eth_ip_addr outputs eth configurations for up to 6 interfaces and
> configured IP address.
>
> Signed-off-by: Max Filippov
Acked-by: Joe Hershberger
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On Tue, Aug 2, 2016 at 10:04 PM, Gong Qianyu wrote:
> The current code would always use the speed and mode set by
> CONFIG_ENV_SPI_MAX_HZ and CONFIG_ENV_SPI_MODE. But if using
> SPI driver model it should get the values from DT.
>
> Signed-off-by: Gong Qianyu
> Reviewed-by: Jagan Teki
Reviewed-
On Tue, Aug 2, 2016 at 9:42 PM, Yaroslav K. wrote:
> Fix compile errors when enabling CONFIG_DM_ETH,
> CONFIG_CMD_E1000 and CONFIG_E1000_SPI.
>
> Signed-off-by: Yaroslav K.
In the future please Cc me when sending network patches.
scripts/patman/patman can help you with this.
Also, please do not
On Wed, Aug 3, 2016 at 4:31 AM, Alban Bedel
wrote:
> When adding support for the driver model the SPI EEPROM feature had
> been ignored. Fix the build with both CONFIG_DM_ETH and
> CONFIG_E1000_SPI enabled.
>
> Signed-off-by: Alban Bedel
This was also sent by Yaroslav K. :
https://patchwork.ozla
On Tue, Aug 2, 2016 at 9:42 PM, Yaroslav K. wrote:
> Fix compile errors when enabling CONFIG_DM_ETH,
> CONFIG_CMD_E1000 and CONFIG_E1000_SPI.
>
> Signed-off-by: Yaroslav K.
Something about this patch email is malformed and not parsed by
patchwork properly.
Another patch with the same intent was
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> Reading the PCI BAR & converting the result to a physical address is not
> safe across all architectures. For example on MIPS the virtual:physical
> mapping is not 1:1, so we cannot directly make use of the physical
> address.
>
> Use the more g
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> The pch_gbe driver previously casted pointers to & from unsigned 32 bit
> integers in many locations. This breaks the driver on 64 bit systems,
> producing streams of compiler warnings about mismatched pointer &
> integer sizes and then failing
On Wed, Aug 3, 2016 at 4:31 AM, Alban Bedel
wrote:
> When adding support for the driver model the SPI EEPROM feature had
> been ignored. Fix the build with both CONFIG_DM_ETH and
> CONFIG_E1000_SPI enabled.
>
> Signed-off-by: Alban Bedel
Acked-by: Joe Hershberger
___
On 04/08/16 17:23, Joe Hershberger wrote:
Hi Paul,
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mis
Hi Paul,
On Thu, Aug 4, 2016 at 5:29 AM, Paul Burton wrote:
> The pch_gbe driver previously casted pointers to & from unsigned 32 bit
> integers in many locations. This breaks the driver on 64 bit systems,
> producing streams of compiler warnings about mismatched pointer &
> integer sizes and the
On Tue, Jul 12, 2016 at 4:52 PM, Chris Packham wrote:
> The __get_unaligned_le* functions may not be declared on all platforms.
> Instead, get_unaligned_le* should be used. On many platforms both of
> these are the same function.
>
> Signed-off-by: Chris Packham
Acked-by: Joe Hershberger
__
Hi Simon,
On Wed, Aug 3, 2016 at 8:17 PM, Simon Glass wrote:
> Hi Joe,
>
> On 3 August 2016 at 17:18, Joe Hershberger wrote:
>> On Tue, Aug 2, 2016 at 2:20 AM, Stefan Agner wrote:
>>> From: Stefan Agner
>>>
>>> Flush loaded data cacheline aligned. This avoids warnings such as
>>> CACHE: Misali
On 08/04/2016 05:32 PM, Chin Liang See wrote:
> On Thu, 2016-08-04 at 17:27 +0200, Marek Vasut wrote:
>> On 08/04/2016 05:08 PM, Chin Liang See wrote:
>>> Hi Marek,
>>
>> Hi,
>>
>>> On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
On 08/03/2016 05:17 PM, Chin Liang See wrote:
> Add ba
On 08/04/2016 05:12 PM, Chin Liang See wrote:
> On Thu, 2016-08-04 at 07:30 +0200, Marek Vasut wrote:
>> On 08/03/2016 05:22 PM, Chin Liang See wrote:
>>
>> Hi,
>
> Hi Marek,
>
>>
>> [...]
> It's the fat driver which is utilizing the malloc.
So fat is allocating stuff without freein
On Thu, Aug 04, 2016 at 11:36:01AM -0400, Tom Rini wrote:
> On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> > Hi,
> >
> > On 04/08/16 16:01, Tom Rini wrote:
> > > Hey guys,
> > >
> > > I just started trying out my Pine64 1GB and mainline U-Boot and I've
> > > found that:
> > > c
On Thu, Aug 04, 2016 at 04:14:21PM +0100, Andre Przywara wrote:
> Hi,
>
> On 04/08/16 16:01, Tom Rini wrote:
> > Hey guys,
> >
> > I just started trying out my Pine64 1GB and mainline U-Boot and I've
> > found that:
> > commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
> > Author: Siarhei Siamashka
On Thu, 2016-08-04 at 17:27 +0200, Marek Vasut wrote:
> On 08/04/2016 05:08 PM, Chin Liang See wrote:
> > Hi Marek,
>
> Hi,
>
> > On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
> > > On 08/03/2016 05:17 PM, Chin Liang See wrote:
> > > > Add base address header file for Stratix10 SoC
> > >
On 08/04/2016 05:08 PM, Chin Liang See wrote:
> Hi Marek,
Hi,
> On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
>> On 08/03/2016 05:17 PM, Chin Liang See wrote:
>>> Add base address header file for Stratix10 SoC
>>>
>>> Signed-off-by: Chin Liang See
>>> Cc: Marek Vasut
>>> Cc: Dinh Nguyen
On Thu, 2016-08-04 at 07:30 +0200, Marek Vasut wrote:
> On 08/03/2016 05:22 PM, Chin Liang See wrote:
>
> Hi,
Hi Marek,
>
> [...]
> > > > It's the fat driver which is utilizing the malloc.
> > >
> > > So fat is allocating stuff without freeing it ? I wonder if we
> > > should
> > > either fix
Hi,
On 04/08/16 16:01, Tom Rini wrote:
> Hey guys,
>
> I just started trying out my Pine64 1GB and mainline U-Boot and I've
> found that:
> commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
> Author: Siarhei Siamashka
> Date: Tue May 31 01:48:06 2016 +0300
>
> sunxi: Move the SPL stack top
On Wed, 2016-08-03 at 19:17 -0600, Simon Glass wrote:
> Hi,
>
Hi Simon,
> On 2 August 2016 at 21:24, Chin Liang See wrote:
> > Enable a simple malloc implementation which will minimize
> > memory usage prior relocation. This is essential as memory
> > available prior location is internal memory
Hi Marek,
On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
> On 08/03/2016 05:17 PM, Chin Liang See wrote:
> > Add base address header file for Stratix10 SoC
> >
> > Signed-off-by: Chin Liang See
> > Cc: Marek Vasut
> > Cc: Dinh Nguyen
> > Cc: Ley Foon Tan
>
> Applied to the 01-arria10
On Thu, Aug 04, 2016 at 03:14:34PM +0300, Alexey Brodkin wrote:
> As of now we have 2 flavors of ARC SDP boards:
> 1) AXS101 - with ARC770 in ASIC
> 2) AXS103 - with ARC HS38 in FPGA
>
> Both options share exactly the same base-board and only differ with
> CPU-tiles in use. That means all perip
On Thu, Aug 04, 2016 at 03:02:44AM +, york sun wrote:
> (Resend)
>
> Tom,
>
> The following changes since commit ad6a303c578b0087749510d20c1c46ae13f20367:
>
> Merge git://git.denx.de/u-boot-fsl-qoriq (2016-08-02 20:45:24 -0400)
>
> are available in the git repository at:
>
> git:/
Hey guys,
I just started trying out my Pine64 1GB and mainline U-Boot and I've
found that:
commit 1a83fb4a17d959d7b037999ab7ed7e62429abe34
Author: Siarhei Siamashka
Date: Tue May 31 01:48:06 2016 +0300
sunxi: Move the SPL stack top to 0x1A000 on Allwinner A64/A80
is breaking boot for me.
As of now we have 2 flavors of ARC SDP boards:
1) AXS101 - with ARC770 in ASIC
2) AXS103 - with ARC HS38 in FPGA
Both options share exactly the same base-board and only differ with
CPU-tiles in use. That means all peripherals are the same (they are
implemented in FPGA on the base-board) and so g
ARCangel was one of the main development boards back in the day but
now it's gone and replaced by other boards like ARC SDP.
But we also used to have simulation platform very similar to ARCangel4
in terms of CPU settings as well as basic IO like UART. Even though
ARCangel4 is long gone now we have
Starting from arc-2016.03 GNU tools linker properly works with
symbols defined in linker script and so external declarations
are no longer required, dump them.
Signed-off-by: Alexey Brodkin
---
arch/arc/cpu/u-boot.lds | 51 +++--
arch/arc/include/asm/s
Initially IVT for ARCv2 was simply copypasted from ARCompact
with some selected fixes so basic stuff works.
Now we update it with more ARCv2 specific vectors like
* Software Interrupt
* Division by zero
* Data cache consistency error
* Misaligned access
Also normal interrupts are now implemen
This might be useful to make sure relocation fixups really
happen. And since this info gets printed only in DEBUG
build it doesn't really hurt normal execution.
Signed-off-by: Alexey Brodkin
---
arch/arc/lib/relocate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arc/lib/reloc
Add a simple driver for the clocks provided by the MIPS Boston
development board. The system provides information about 2 clocks whose
rates are fixed by the bitfile flashed in the boards FPGA, and this
driver simply reads the rates of these 2 clocks.
Signed-off-by: Paul Burton
Reviewed-by: Simon
This patch introduces support for building U-Boot to run on the MIPS
Boston development board. This is a board built around an FPGA & an
Intel EG20T Platform Controller Hub, used largely as part of the
development of new CPUs and their software support. It is essentially
the successor to the older
Provide a trivial syscon driver matching the generic "syscon" compatible
string, allowing for simple system controllers to be used without a
custom driver just as in Linux.
Signed-off-by: Paul Burton
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in
Device model drivers have previously been matched to FDT nodes by virtue
of being the first driver in the driver list to be compatible with the
node. This ignores the fact that compatible strings in the device tree
are listed in order of priority - that is, if we have a node with 2
compatible strin
The regmap_read & regmap_write functions were previously declared in
regmap.h but not implemented anywhere. The regmap implementation &
commit message of 6f98b7504f70 ("dm: Add support for register maps
(regmap)") indicate that only memory mapped accesses are supported for
now, so providing simple
The pch_gbe driver previously casted pointers to & from unsigned 32 bit
integers in many locations. This breaks the driver on 64 bit systems,
producing streams of compiler warnings about mismatched pointer &
integer sizes and then failing to keep track of addresses correctly at
runtime.
Fix the dr
Reading the PCI BAR & converting the result to a physical address is not
safe across all architectures. For example on MIPS the virtual:physical
mapping is not 1:1, so we cannot directly make use of the physical
address.
Use the more generic BAR-mapping function dm_pci_map_bar to discover the
MMIO
In pci_uclass_pre_probe an attempt is made to detect whether the parent
of a device is a PCI device and that the device is thus a bridge. This
was being done by checking whether the parent of the device is of the
UCLASS_ROOT class. This causes problems if the PCI controller is a child
of some other
This patch adds a driver for the Xilinx AXI bridge for PCI express, an
IP block which can be used on some generations of Xilinx FPGAs. This is
mostly a case of implementing PCIe ECAM specification, but with some
quirks about what devices are valid to access.
Signed-off-by: Paul Burton
Reviewed-by
Import a copy of the dt-bindings/interrupt-controller/mips-gic.h header
from Linux, such that we can use device trees which include it without
modification.
Signed-off-by: Paul Burton
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
includ
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