Hi,
> On 08/29/2016 11:29 AM, Huan Wang wrote:
> >> On 18.07.16 05:24, Huan Wang wrote:
> >>> Hi, Alex,
> >>>
> >>>
> >>>
> >>>As there is strong objection to remove the codes
> >>> about switching to EL1, I think we have to remain it, do you agree?
> >> I agree, yes.
> >>
> >>>
Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: Daniel Allred
---
arch/arm/cpu/armv7/omap5/fdt.c | 64
Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
If the ending portion of the DRAM is reserved for secure
world use, then u-boot cannot use this memory for its relocation
purposes. To prevent issues, we mark this memory as PRAM and this
prevents it from being used by u-boot at all.
Signed-off-by: Daniel Allred
---
After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are
These patches to add secure memory reservations and EMIF firewall config to
SDRAM
init code. The reservation and firewall config is done using PPA installed HAL
APIs,
so they are not common to all platforms (so they are put in omap5 path instead
of
omap-common).
With these patches applied, a
On 09/01/2016 08:39 PM, Xiaoliang Yang wrote:
> Hi york,
>
> The silicon bug was existing in V1.0 of SoCs, we have already not supported
> them.
No good. SDK may not support it, but ss long as we have users with rev 1
SoC, we need to support it in U-Boot. You can add revision check and
skip
On Thursday 01 September 2016 10:34 AM, Madan Srinivas wrote:
> This series adds support for secure keystone family of devices, more
> specifically for K2E (Edison).This work is similar to what has already
> been done for the AM43xx and AM57xx SoCs and leverages much of the
> infrastructure from
On 09/01/2016 07:32 PM, Xiaoliang Yang wrote:
> Hi York,
>
> We need enable i-cache in low level in order to improve u-boot running speed.
> We have skipped lowlevel_init because a silicon bug before. (it could not run
> some instructions in lowlevel_init until DDR init, the bug has already
Hi Stephen,
> > Subject: [PATCH v1 2/2] clk: at91: Add .ops callback for clk_generic
> >
> > To avoid the wild pointer as NULL->of_xlate, add an empty .ops
> > callback for the clk_generic driver.
>
> This shouldn't be needed. If this driver isn't a clock provider, and it
> cannot be a
> clock
From: Bryan Wu
The Linux-for-Tegra kernel uses a very long command line.
The default value of CONFIG_SYS_CBSIZE is too small to printf out the
long command line and causes a message like:
bootarg overflow 602+0+0+1 > 512
on the console, and the board refuses to boot.
The
> "Stephen" == Stephen Warren writes:
Stephen> I don't have that message either, and Google can't find it.
I'll send it again.
Thanks.
--
Dr Peter Chubb Tel: +61 2 9490 5852 http://www.data61.csiro.au
http://ts.data61.csiro.au Software Systems
On 09/01/2016 04:53 PM, peter.ch...@data61.csiro.au wrote:
"Tom" == Tom Warren writes:
Tom> Peter, It appears that this got rolled into 'ARM: tegra: increase
Tom> console buffer size and sys args num', so I'm going to mark it as
Tom> Superseded in my Patchwork queue.
Yes,
Peter,
> -Original Message-
> From: peter.ch...@data61.csiro.au [mailto:peter.ch...@data61.csiro.au]
> Sent: Thursday, September 01, 2016 3:54 PM
> To: Tom Warren
> Cc: swar...@wwwdotorg.org; peter.ch...@data61.csiro.au; u-
> b...@lists.denx.de; Stephen Warren
* Scott Wood [160901 15:41]:
> Now that nand_info[] is an array of pointers we need to test the
> pointer itself rather than using name as a proxy for NULLness.
>
> Fixes: b616d9b0a708eb9 ("nand: Embed mtd_info in struct nand_chip")
> Signed-off-by: Scott Wood
Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Thursday, September 01, 2016 3:47 PM
> To: Tom Warren ; Steve Arnold
>
> Cc: Stephen Arnold ; u-boot@lists.denx.de; Stephen L
>
> "Tom" == Tom Warren writes:
Tom> Peter, It appears that this got rolled into 'ARM: tegra: increase
Tom> console buffer size and sys args num', so I'm going to mark it as
Tom> Superseded in my Patchwork queue.
Yes, Stephen asked me to cherrypick instead from the tegra
On 09/01/2016 04:36 PM, Tom Warren wrote:
Steve/Stephen,
-Original Message-
From: Stephen Warren [mailto:swar...@wwwdotorg.org]
Sent: Tuesday, July 26, 2016 2:57 PM
To: Steve Arnold
Cc: Stephen Arnold ; u-boot@lists.denx.de; Stephen L
Arnold
Peter,
It appears that this got rolled into 'ARM: tegra: increase console buffer size
and sys args num', so I'm going to mark it as Superseded in my Patchwork queue.
What's the status of the 'increase console buffer size and sys args num' patch?
I've currently got it marked as 'Changes
Now that nand_info[] is an array of pointers we need to test the
pointer itself rather than using name as a proxy for NULLness.
Fixes: b616d9b0a708eb9 ("nand: Embed mtd_info in struct nand_chip")
Signed-off-by: Scott Wood
Cc: Lukasz Majewski
Cc: Tony
Steve/Stephen,
> -Original Message-
> From: Stephen Warren [mailto:swar...@wwwdotorg.org]
> Sent: Tuesday, July 26, 2016 2:57 PM
> To: Steve Arnold
> Cc: Stephen Arnold ; u-boot@lists.denx.de; Stephen L
> Arnold ; Tom Warren
On 09/01/2016 08:12 PM, Max Ruttenberg wrote:
> Thanks for getting back to me.
Hi,
please avoid top-posting.
> At the moment the FPGA just has logic for peripheral management. Part of
> what I'm trying to do in U-Boot is program a bitfile to it over a PCIe
> connection.
Which FPGA
On 08/31/2016 10:14 PM, Sumit Garg wrote:
>> -Original Message-
>> From: york sun
>> Sent: Wednesday, August 31, 2016 9:04 PM
>> To: Sumit Garg ; u-boot@lists.denx.de
>> Cc: Prabhakar Kushwaha ; Ruchika Gupta
>>
>>
On 09/01/2016 04:46 PM, Max Ruttenberg wrote:
> Hi,
Hi,
> I'm find myself clueless in regards to writing a driver for an FPGA over a
> PCI bus. This U-Boot is running on an NXP t102xrdb board family, if that
> matters.
>
> The documentation in doc/driver-model/pci-info.txt mentions that I can
Tom,
Please pull u-boot-tegra/master into U-Boot/master. Thanks!
All Tegra builds are OK, and Stephen's automated test system reports that
all tests pass.
The following changes since commit cb1cbdd96962931de2ac948a184874e2672f3f96:
x86: qemu: efi: Add two boards for EFI 32-bit and 64-bit
Line up comments for readibility.
Signed-off-by: Robert P. J. Day
---
missed the last few lines with patch v1, and if i'm going to do it,
i might as well do it properly.
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index
On 08/31/2016 11:59 PM, Xiaoliang Yang wrote:
> Add lowlevel init in ls102xa, and delete the CONFIG_SKIP_LOWLEVEL_INIT
> define in ls1021atwr.h
Why do you need lowlevel_init now, but not before?
York
___
U-Boot mailing list
U-Boot@lists.denx.de
Hi Stefan,
applying patch [U-Boot,v4,06/13]ext4 and Michael Walles patch
[U-Boot,v4,3/4]ext4, I'm now able to write into directories on ext4 fs from
u-boot. However, when deleting a given file (i.e. when writing to an existing
filename), u-boot crashes when ext4 extents are enabled.
Some
On 08/30/2016 09:22 AM, Masahiro Yamada wrote:
Masahiro Yamada (4):
ARM: tegra: remove wrong dependency on SPL_BUILD
ARM: armv7: guard memory reserve for PSCI with #ifdef
CONFIG_ARMV7_PSCI
ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig
ARM: armv7: move ARMV7_PSCI_NR_CPUS to
SPL needs to have bigger stack size because of USB.
Simple malloc needs to be disabled because dfu code requires different
allocation functions. There is no space in OCM that's why random place
in DDR is used.
BOOTD must be disabled because it is causing compilation error.
All variables are
It should be enough to call low(5us)->high pulse for all cases
to provide proper reset. There is no need to call high->low->high.
Signed-off-by: Michal Simek
---
arch/arm/cpu/armv8/zynqmp/spl.c | 4
1 file changed, 4 deletions(-)
diff --git
Add USB boot mode.
Signed-off-by: Michal Simek
---
arch/arm/include/asm/arch-zynqmp/hardware.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h
b/arch/arm/include/asm/arch-zynqmp/hardware.h
index
Mode pins can be used as output for reset. Xilinx boards are using
this feature as additional way how to reset USB phys and also others
chips on the boards.
Mode1 is used on all these boards for this feature.
Let SPL toggle reset on this pin by default.
Signed-off-by: Michal Simek
With SPL_DFU support memory layout needs to be cleanup
that's why move bss to the start of memory.
Signed-off-by: Michal Simek
---
include/configs/xilinx_zynqmp.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/xilinx_zynqmp.h
Current code generates warning when it is compiled for arm64:
Warnings:
In file included from drivers/spi/zynq_spi.c:14:0:
drivers/spi/zynq_spi.c: In function ‘zynq_spi_init_hw’:
drivers/spi/zynq_spi.c:95:9: warning: large integer implicitly truncated
to unsigned type [-Woverflow]
Function is defined in g_dnl.h and have different parameter
then it is used. This patch fixes it.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/zynqmp.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/board/xilinx/zynqmp/zynqmp.c
On 08/29/2016 11:29 AM, Huan Wang wrote:
On 18.07.16 05:24, Huan Wang wrote:
Hi, Alex,
As there is strong objection to remove the codes about
switching to EL1, I think we have to remain it, do you agree?
I agree, yes.
If it is remained, I think your
Signed-off-by: Robert P. J. Day
---
given that this misspelling is being used for partition names, i
won't treat it as a normal typo, so sending a separate patch just for
this.
diff --git a/include/configs/at91-sama5_common.h
b/include/configs/at91-sama5_common.h
On Thu, 1 Sep 2016, Robert P. J. Day wrote:
> i'm sure i'll figure this out if i keep reading the code, but if i
> have a new board where the env will be stored in flash, and i flash
> a fresh build of u-boot with a default environment, at what point
> will that default environment be written
> -Original Message-
> From: york sun
> Sent: Wednesday, August 31, 2016 9:04 PM
> To: Sumit Garg ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Ruchika Gupta
>
> Subject: Re: [u-boot-release] [PATCH] fsl_sfp :
Hello Heiko and Michal,
Do you agree that the u-boot sources need to be adapted in order to have ubifs
on the Microblaze?
It would be good if the changes are somehow in the mainline.
BR
Marco
> -Original Message-
> From: Hoefle Marco
> Sent: Montag, 15. August 2016 13:55
> To:
i'm sure i'll figure this out if i keep reading the code, but if i
have a new board where the env will be stored in flash, and i flash a
fresh build of u-boot with a default environment, at what point will
that default environment be written to persistent storage (as defined
by
In case my on-board linux is not booting (kernel/rootfs problem), I would like
to have a chance to recover the device. As the only interface is ethernet, I
could try a tftpboot first and only if this fails boot from flash.
This of course has disadvantage that this tfpboot trial needs time, most
From: Shengzhou Liu
Enable ERRATUM_A008511, ERRATUM_A009801, ERRATUM_A009803,
ERRATUM_A009942, ERRATUM_A010165
Signed-off-by: Shengzhou Liu
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Add ERRATUM_A008511.
From: Mingkai Hu
LS1046ARDB Specification:
-
Memory subsystem:
* 8GByte DDR4 SDRAM (64bit bus)
* 512 Mbyte NAND flash
* Two 64 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
* On-board 4G eMMC
Ethernet:
* Two XFI
From: Shaohui Xie
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v3:
- No change.
v2:
- Use values directly
sec_init() which was earlier called in misc_init_r()
is now done in board_init() before PPA init as SEC
block will be used during PPA image validation.
Signed-off-by: Aneesh Bansal
Signed-off-by: Sumit Garg
---
Changes in v2:
Rebased Aneesh's
On 08/31/2016 11:21 AM, York Sun wrote:
> -Original Message-
> From: york sun
> Sent: Wednesday, August 31, 2016 11:21 PM
> To: Qiang Zhao
> Cc: u-boot@lists.denx.de; Shengzhou Liu ; Xiaobo
> Xie
> Subject: Re: [PATCH] pbl:
From: Mingkai Hu
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
From: Shaohui Xie
The CONFIG_STANDALONE_LOAD_ADDR is set to 0x8030 by default.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
---
v2-v3:
- No change.
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
1 file
From: Shaohui Xie
The 'commit 95279315076c ("board/ls2085rdb: Export functions for
standalone AQ FW load apps")' mentioned memset was exported but
it was not, this patch exports the memset.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
Hi all,
This is version 3 patchset mainly to add support for LS1046ARDB board.
It should be based on two DDR patches to work well on LS1046ARDB.
The two patches are:
http://patchwork.ozlabs.org/patch/663534/
http://patchwork.ozlabs.org/patch/663535/
PCIe and USB are not supported yet due to lack
From: Shaohui Xie
When CONFIG_SYS_FSL_ERRATUM_A009801 is defined but
CONFIG_SYS_FSL_ERRATUM_A008511 not defined, there is compile error that
temp32 undeclared, this patch fixes it.
Signed-off-by: Shaohui Xie
Signed-off-by: Gong Qianyu
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal
Signed-off-by: Sumit Garg
---
Rebased Aneesh's patchset. No dependency.
Link to
Hi,
On Thu, Sep 01, 2016 at 10:44:13AM +0200, Hans de Goede wrote:
> On 01-09-16 09:57, Antoine Tenart wrote:
> >Introducing the ARM_GIC configuration option, use it to only use GIC
> >specific code in ARM PSCI function when the SoC has a GIC.
>
> AFAIK sunxi is not the only user of these files,
Hi,
On Thu, Sep 01, 2016 at 10:47:28AM +0200, Hans de Goede wrote:
> On 01-09-16 09:57, Antoine Tenart wrote:
> >sun5i now implements the psci suspend function. In order to be used by
> >the kernel, we should now boot in non-secure mode. Enable it by default.
>
> The sun5i has a cortex a8, which
Use environment variable "kernel_addr_r" to indicate the location
in RAM where FIT image will be stored.
Use label command "kernel" to indicate which the FIT image at.
Signed-off-by: Wenbin Song
---
Changes for v2: Fixup the email address of author.
---
doc/README.pxe | 12
From: York Sun
When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.
Test cases:
1. Booting with legacy images
2. Booting with legacy images without initrd
3.
Add lowlevel init in ls102xa, and delete the CONFIG_SKIP_LOWLEVEL_INIT
define in ls1021atwr.h
Signed-off-by: Xiaoliang Yang
---
arch/arm/cpu/armv7/Makefile | 2 +-
arch/arm/cpu/armv7/ls102xa/soc.c | 4
include/configs/ls1021atwr.h | 1 -
3 files changed, 5
The sun5i SoCs can take advantage of the newly introduce PSCI suspend
function. Enable the PSCI support to denote this.
Signed-off-by: Antoine Tenart
---
include/configs/sun5i.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/sun5i.h
sun5i now implements the psci suspend function. In order to be used by
the kernel, we should now boot in non-secure mode. Enable it by default.
Signed-off-by: Antoine Tenart
---
board/sunxi/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi all,
This series adds an implementation of the psci suspend function for both
sun5i and sun7i. This was tested on Nextthing's CHIP and on a A20, using
cpuidle in Linux. My tests showed a power consumption reduced by a factor
2 on the CHIP when the system was idle. It went from ~1W without
Some SoC does not have a GIC. Adds a configuration option to denote
this, allowing to remove code configuring the GIC when it's not
possible.
Signed-off-by: Antoine Tenart
---
arch/arm/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git
Introducing the ARM_GIC configuration option, use it to only use GIC
specific code in ARM PSCI function when the SoC has a GIC.
Signed-off-by: Antoine Tenart
---
arch/arm/cpu/armv7/nonsec_virt.S | 6 ++
arch/arm/cpu/armv7/virt-v7.c | 38
Add the suspend psci function for sun5i and sun7i. When running on a
sun5i, this function put the ram into self-refresh, cut off some PLLs
and switch cpuclk to losc. When on a sun7i the suspend function
currently only cut off a few PLLs and switch cpuclk to osc24m. This
should be improved later.
From: Vitaly Andrianov
Like the OMAP54xx, AM43xx & AM33xx family SoCs, the keystone family
of SoCs also have high security enabled models. Allow K2E devices to
be built with HS Device Type Support.
This patch applies on top of the patch
ti: omap-common: Allow AM33xx devices to
Adds an additional image type needed for supporting secure keystone
devices. The build generates u-boot_HS_XIP_X-LOADER which can
be used to boot from all media on secure keystone devices.
Signed-off-by: Madan Srinivas
Cc: Andrew F. Davis
---
Changes in v2:
-
Select the newly introduced ARM_GIC option to the relevant sunxi
MACH configurations.
Signed-off-by: Antoine Tenart
---
board/sunxi/Kconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index
From: Vitaly Andrianov
Add a new defconfig file for the K2E High Security EVM.
This defconfig is the same as for the non-secure part, except for:
CONFIG_TI_SECURE_DEVICE option set to 'y'
CONFIG_FIT option set to 'y'
CONFIG_FIT_IMAGE_POST_PROCESS option
Add a section describing the secure boot image used on
keystone secure devices.
This patch applies on top of the patch
doc: Update info on using AM33xx secure devices from TI
submitted by Andrew Davis
Signed-off-by: Madan Srinivas
---
Changes in v2:
- Updates the secure
From: Wenbin song
Use environment variable "kernel_addr_r" to indicate the location
in RAM where FIT image will be stored.
Use label command "kernel" to indicate which the FIT image at.
Signed-off-by: Wenbin Song
---
v2: new add.
---
doc/README.pxe |
From: York Sun
When FIT image is used, a single image provides kernel, device
tree and optionally ramdisk. Argc and argv need to be adjusted
to support this.
Test cases:
1. Booting with legacy images
2. Booting with legacy images without initrd
3.
Hi Vladimir, yes the problem is resolved, it was a problem with the size of
uboot image when enabling MII commands. I was copying just 256KB to nand
flash and the image was a little larger than that, so I increased the uboot
memory section in nand flash and it started working fine. Thanks for your
From: Vitaly Andrianov
This commit implements the board_fit_image_post_process() function for
the keystone architecture. Unlike OMAP class devices, security
functions in keystone are not handled in the ROM.
The interface to the secure functions is TI proprietary and depending
on
This series adds support for secure keystone family of devices, more
specifically for K2E (Edison).This work is similar to what has already
been done for the AM43xx and AM57xx SoCs and leverages much of the
infrastructure from them.
The big difference here is the ROM on keystone2 devices does not
As K2 can directly boot u-boot, add u-boot_HS_MLO as the
secure image while booting secure K2 devicesr, for all
boot modes other than SPI flash.
Signed-off-by: Madan Srinivas
---
Changes in v2:
- Adds a new name for the signed output image in config_secure.mk
to keep it in
The function board_fit_image_post_process is defined only when the config
CONFIG_FIT_IMAGE_POST_PROCESS is enabled. For secure systems that do not
use SPL but use FIT kernel images, only CONFIG_FIT_IMAGE_POST_PROCESS will
be defined, which will result in an implicit declaration of function
On 16-08-23 15:17:12, Marek Vasut wrote:
> On 08/09/2016 08:14 PM, Sanchayan Maity wrote:
> > Hello,
> >
> > This is the second version of the patchset for migrating Vybrid
> > USB driver to driver model.
> >
> > Compare to the first version, this version takes care of dr_mode
> > property and
Add tabs or replace spaces so that all comments line up for easier
reading.
Signed-off-by: Robert P. J. Day
---
just to make for easier reading, compile-tested for MPC8315ERDB.
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index
All fields were accessed directly instead of using the proper byte swap
functions. Thus, ext4 write support was only usable on little-endian
architectures. Fix this.
Signed-off-by: Michael Walle
---
Changes:
v4:
- convert "unsigned int" to __le32 pointer in
On 09/01/2016 04:14 AM, Kever Yang wrote:
> The dwc3 controller is using 8 bit UTMI+ interface for USB2.0 PHY,
> add one variable in dwc3/dwc3_device struct to support 16 bit
> UTMI+ interface on some SoCs like Rockchip rk3399.
>
> Signed-off-by: Kever Yang
> ---
>
>
On 09/01/2016 04:14 AM, Kever Yang wrote:
> This patch add board_usb_init() and interrupt callback
> for dwc3 gadget.
>
> Signed-off-by: Kever Yang
> ---
>
> Changes in v4:
> - parse DT for quirk, base address and maximum speed
>
> Changes in v3:
> - remove utmi
On 09/01/2016 04:21 AM, Kever Yang wrote:
> Hi Marek,
>
> On 08/31/2016 08:30 PM, Marek Vasut wrote:
>> On 08/31/2016 10:40 AM, Kever Yang wrote:
>>> This patch add board_usb_init() and interrupt callback
>>> for dwc3 gadget.
>>>
>>> Signed-off-by: Kever Yang
>>> ---
ZynqMP provides an option to overwrite bootmode setting which
can change SPL behavior.
For example: boot SPL via JTAG and then SPL loads images from SD.
Signed-off-by: Michal Simek
---
Is there any way how to use symbols from headers?
Currently Kconfig just copies
Hi,
On 01-09-16 09:57, Antoine Tenart wrote:
sun5i now implements the psci suspend function. In order to be used by
the kernel, we should now boot in non-secure mode. Enable it by default.
Signed-off-by: Antoine Tenart
The sun5i has a cortex a8, which does
Hi,
On 01-09-16 09:57, Antoine Tenart wrote:
Hi all,
This series adds an implementation of the psci suspend function for both
sun5i and sun7i. This was tested on Nextthing's CHIP and on a A20, using
cpuidle in Linux. My tests showed a power consumption reduced by a factor
2 on the CHIP when
Hi,
On 01-09-16 09:57, Antoine Tenart wrote:
Introducing the ARM_GIC configuration option, use it to only use GIC
specific code in ARM PSCI function when the SoC has a GIC.
Signed-off-by: Antoine Tenart
AFAIK sunxi is not the only user of these files, so
TI QSPI has four 32 bit data registers which can be used to transfer 16
bytes of data at once. The register group QSPI_SPI_DATA_REG_3,
QSPI_SPI_DATA_REG_2, QSPI_SPI_DATA_REG_1 and QSPI_SPI_DATA_REG is
treated as a single 128-bit word for shifting data in and out. The bit
at QSPI_SPI_DATA_REG_3[31]
This udelay() was added as an HACK and is no longer required. All
read/write/erase operations work fine even without this delay. Hence,
remove the udelay() call.
Tested read/write/erase operation on AM437x SK. Also tested QSPI Boot.
Signed-off-by: Vignesh R
---
This patch series tries to improve QSPI write speed by writing 16 bytes
at once whenever possible. Also remove unnecessary 100us delay for
AM437x.
Tested on AM437x SK, DRA74 and DRA72 EVM.
Vignesh R (2):
spi: ti_qspi: use 128 bit transfer mode when writing to flash
spi: ti_qspi: Remove
Signed-off-by: Shengzhou Liu
---
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
board/freescale/ls1021atwr/ls1021atwr.c| 7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
Hi York,
> -Original Message-
> From: york sun
> Sent: Thursday, September 01, 2016 5:43 AM
> To: Qianyu Gong ; u-boot@lists.denx.de
> Cc: Prabhakar Kushwaha ; Mingkai Hu
> ; Shaohui Xie ; Zhiqiang
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