When booting from EMMC, load the DTB and pass it to the kernel.
Signed-off-by: Fabien Parent
Reviewed-by: Tom Rini
---
v1 -> v2:
* No change
---
include/configs/omapl138_lcdk.h | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/include/configs/omapl138_lcdk.h b/inclu
Just a note to myself mostly, I forgot to this one in the patch series,
son in v2 I'll add that as well.
diff --git a/net/eth_common.c b/net/eth_common.c
index e0d8b62..57ef821 100644
--- a/net/eth_common.c
+++ b/net/eth_common.c
@@ -51,7 +51,7 @@ void eth_parse_enetaddr(const char *addr, uchar
On Wed, Nov 23, 2016 at 07:13:25PM +, york sun wrote:
> Tom,
>
> Let's try again.
>
> The following changes since commit 693d4c9f1dc40fcf24ced459bc4d1b46db33298a:
>
>spl: Remove CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (2016-11-18 21:20:59
> -0500)
>
> are available in the git repository at
On 29/11/2016 16:13, Christoph Fritz wrote:
> This patch adds initial support for Samtec VIN|ING 2000 board.
>
> Signed-off-by: Christoph Fritz
> ---
> Changes since v1:
> - add more comments (enet phy init)
> - fix layout style e.g. multi-line-comments
> - use pinmux macros
> - use helper fu
On Wed, Oct 26, 2016 at 4:39 PM, Jagan Teki wrote:
> On Wed, Sep 28, 2016 at 4:39 PM, Yuan Yao wrote:
> > From: Yuan Yao
> >
> > Some new flash don't support bar register but use 4bytes address to
> > support exceed 16MB flash size.
> > So add flash flag:
> > ADDR_4B
> > for some flash which sup
This patch adds initial support for Samtec VIN|ING 2000 board.
Signed-off-by: Christoph Fritz
---
Changes since v1:
- add more comments (enet phy init)
- fix layout style e.g. multi-line-comments
- use pinmux macros
- use helper funcs clrsetbits_le32() and wait_for_bit()
- make some function
With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.
Signed-off-by: Dinh Nguyen
---
board/altera/arria5-socdk/MAINTAINERS | 2 +-
board/altera/cyclone5-socdk/MAINTAINERS | 2 +-
board/terasic/de0-nano-soc/MAINTAINERS |
On Dienstag, 29. November 2016 14:10:54 CET Sébastien Szymanski wrote:
>
> > Btw, which u-boot version are you using?
>
> I first noticed the issue on U-Boot 2016.05 so I rebase on master from
> http://git.denx.de/u-boot.git
>
> Regards,
That still doesn't make clear on which version you see th
Tim Harvey writes:
> On Tue, Nov 29, 2016 at 4:06 AM, Måns Rullgård wrote:
>> Tim Harvey writes:
>>
>>> Greetings,
>>>
>>> In debugging an issue with a rather old branch of U-Boot (2015-04) I
>>> found that the static assignment of a data buffer was not 32-bit
>>> aligned which caused data abor
On Tue, Nov 29, 2016 at 4:06 AM, Måns Rullgård wrote:
> Tim Harvey writes:
>
>> Greetings,
>>
>> In debugging an issue with a rather old branch of U-Boot (2015-04) I
>> found that the static assignment of a data buffer was not 32-bit
>> aligned which caused data aborts. However I find that curren
On Tue, Nov 29, 2016 at 11:31:09AM +0100, Fabien Parent wrote:
> On Mon, Nov 28, 2016 at 5:56 PM, Tom Rini wrote:
> > On Fri, Nov 25, 2016 at 11:11:23AM +0100, Fabien Parent wrote:
> >> In order to avoid having a random mac address assigned by Linux, let's
> >> fixup the dtb with the mac address t
A number of platforms had been using the distro default feature before
it was moved to Kconfig but did not enable the new Kconfig option when
it was enabled. This caused a regression in terms of features and this
introduces breakage when more things move to Kconfig.
Signed-off-by: Tom Rini
---
Also convert MENU while we're in here.
Signed-off-by: Tom Rini
---
cmd/Kconfig | 6 ++
common/Kconfig| 6 ++
configs/nokia_rx51_defconfig | 1 +
include/config_distro_defaults.h | 1 -
include/config_fallbacks.h| 1 -
include/config
NAND SPL boot was missing. Add it. The README specific to omapl138-lcdk
is also removed because its content does not apply anymore, i.e. the
generated AIS image can be flashed directly to the NAND without
using any external tool to create and bootable AIS image.
Signed-off-by: Fabien Parent
---
CONFIG_SYS_CLE_MASK is not used anywhere. It has probably been
renamed to CONFIG_SYS_NAND_MASK_CLE. Rename it and remove the former
from the config_whitelist.txt file.
Signed-off-by: Fabien Parent
---
include/configs/omapl138_lcdk.h | 2 +-
scripts/config_whitelist.txt| 1 -
2 files changed,
NAND_MAX_CHIPS is not used anymore and has been replaced by
CONFIG_SYS_MAX_NAND_DEVICE. There is no need to keep the former
define.
Signed-off-by: Fabien Parent
---
include/configs/omapl138_lcdk.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/omapl138_lcdk.h b/include/config
CONFIG_SYS_ALE_MASK is not used anywhere. It has probably been
renamed to CONFIG_SYS_NAND_MASK_ALE. Rename it and remove the former
from the config_whitelist.txt file.
Signed-off-by: Fabien Parent
---
include/configs/omapl138_lcdk.h | 2 +-
scripts/config_whitelist.txt| 1 -
2 files changed,
The default AIS image generated contains the SPL, but the latter is not able to
load u-boot because the NAND configuration is missing. This series adds SPL NAND
boot support and results in the AIS image that is generated able to boot from
NAND.
Fabien Parent (6):
NAND: davinci: add support for N
The omapl138_lcdk header defines CONFIG_SYS_NAND_BUSWIDTH_16_BIT while
the correct name is CONFIG_SYS_NAND_BUSWIDTH_16BIT.
While renaming the only occurrence of CONFIG_SYS_NAND_BUSWIDTH_16_BIT,
let's also remove it from the config_whitelist.txt file.
Signed-off-by: Fabien Parent
---
include/conf
The OMAPL138-LCD board uses a NAND chip with a 16 bits bus. Add
support into the davinci driver for 16 bit bus NAND chips.
Signed-off-by: Fabien Parent
---
drivers/mtd/nand/davinci_nand.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/da
The SPL is unable to load u-boot because the DDR2 is not configured.
Configure the DDR2.
Signed-off-by: Fabien Parent
---
v2 -> v3
* Use new Kconfig option SYS_DA850_DDR_INIT instead of defining it in
the config header file
v1 -> v2
* New patch
---
arch/arm/mach-davinc
Set the correct CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR value in order
to be able to boot from MMC/SD.
The SPL is stored at sector 0x75, while u-boot will follow at
sector 0xb5.
Signed-off-by: Fabien Parent
Reviewed-by: Tom Rini
---
v2 -> v3:
* No change
v1 -> v2:
* Rebased
The list of available boot method is not part of the binary which
prevent the SPL from booting u-boot or Linux.
Add the missing .u_boot_list* sections to the binary to fix it.
Signed-off-by: Fabien Parent
Reviewed-by: Tom Rini
---
v2 -> v3:
* No change
v1 -> v2:
* No change
Clean config headers by moving CONFIG_SYS_DA850_PLL_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent
---
v1 -> v3
* New patch
---
arch/arm/mach-davinci/Kconfig | 7 +++
include/configs/calimain.h| 1 -
include/configs/da850evm.h| 1 -
include/configs/ipam390.h
This patchset tries to fix the SPL on omapl138_lcdk. With this patchset, the SPL
will be able to boot from EMMC/SPI.
The NAND support is still broken so the default u-boot.ais image still has a SPL
that is unable to load u-boot.
Changes v2 .. v3
* Make CONFIG_SYS_DA850_PLL_INIT & CONFIG_SYS_DA85
The SPL is not able to boot properly because the PLL0 is not
configured. Configure it.
Signed-off-by: Fabien Parent
---
v2 -> v3
* Use new Kconfig option SYS_DA850_PLL_INIT instead of defining it in
the config header file
v1 -> v2
* New patch
---
arch/arm/mach-davinci/
Clean config headers by moving CONFIG_SYS_DA850_DDR_INIT away to a
Kconfig file.
Signed-off-by: Fabien Parent
---
v1 -> v3
* New patch
---
arch/arm/mach-davinci/Kconfig | 7 +++
include/configs/calimain.h| 1 -
include/configs/da850evm.h| 1 -
include/configs/ipam390.h
Introduce a new DT property to specify whether the QSPI Controller
samples the data on a rising edge. The default is falling edge.
Some versions of the QSPI Controller do not implement this bit, in
which case the property should be omitted.
Signed-off-by: Phil Edworthy
---
v3:
- Patch split so
This is in preparation for adding another arg.
Signed-off-by: Phil Edworthy
---
v3:
- New patch to split changes.
---
drivers/spi/cadence_qspi.c | 7 ---
drivers/spi/cadence_qspi.h | 2 +-
drivers/spi/cadence_qspi_apb.c | 2 +-
3 files changed, 6 insertions(+), 5 deletions(-)
dif
The Cadence QSPI controller has specified overheads for the various CS
times that are in addition to those programmed in to the Device Delay
register. The overheads are different for the delays.
In addition, the existing code does not handle the case when the delay
is less than a SCLK period.
Thi
Move the code to read the "sram-size" property into the other code
that reads properties from the node, rather than the SF subnode.
Signed-off-by: Phil Edworthy
---
v3:
- New patch to split changes.
---
drivers/spi/cadence_qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --g
On 11/29/2016 01:08 PM, Vignesh R wrote:
>
>
> On Tuesday 29 November 2016 04:23 PM, Marek Vasut wrote:
>> On 11/29/2016 05:58 AM, Vignesh R wrote:
>>>
>>>
>>> On Monday 28 November 2016 06:11 PM, Marek Vasut wrote:
On 11/28/2016 10:37 AM, Vignesh R wrote:
>
>
> On Friday 25 Nove
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 8
1 file changed, 8 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index e81d678..39e31f6 100644
--- a/drivers
Instead of extracting mode settings and passing them as separate
args to another function, just pass the SPI mode as an arg.
Signed-off-by: Phil Edworthy
---
v3:
- New patch introduced to address comments.
---
drivers/spi/cadence_qspi.c | 4 +---
drivers/spi/cadence_qspi.h | 3 +--
dr
A lot of the #defines are for single bits in a register, where the
name has _MASK on the end. Since this can be used for both a mask
and the value, remove _MASK from them.
Whilst doing so, also remove the unnecessary brackets around the
constants.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vas
Show what the output clock rate actually is.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/c
Most of the code already uses #defines for the bit value, rather
than the shift required to get the value. This changes the remaining
code over.
Whislt at it, fix the names of the "Rd Data Capture" register defs.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- Remove brackets tha
With the existing code, when the requested SPI clock rate is near
to the lowest that can be achieved by the hardware (max divider
of the ref clock is 32), the generated clock rate is wrong.
For example, with a 50MHz ref clock, when asked for anything less
than a 1.5MHz SPI clock, the code sets up t
This series has fixes, patches to clean the code up, and add support for
specifying the sampling edge.
Main changes in v3:
1. Added "spi: cadence_qspi: Use spi mode at the point it is needed" to
address comments for SPI pol/phase code.
2. "spi: cadence_qspi: Support specifying the sample
Or'ing together bit positions is clearly wrong.
Signed-off-by: Phil Edworthy
Acked-by: Marek Vasut
---
v3:
- No change.
v2:
- No change.
---
drivers/spi/cadence_qspi_apb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/
Hi Marek,
> On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
> > This define gives the possibility to copy entire image (including
> > header - e.g. u-boot.img) from NOR parallel memory to e.g. SDRAM.
> > The current code only supports loading the raw binary image (the
> > u-boot.bin).
> >
> > The
CONFIG_SYS_CONFIG_NAME is not proper config option for different low
level init files because different board revisions requires different
psu_init_gpl* files.
Also at the end of moving drivers to DM all board specific configuration
files should be removed.
The same changes was done for Zynq.
"AR
On Dienstag, 29. November 2016 10:50:45 CET you wrote:
> Hello,
>
> I am working on a i.MX6UL based board with a 4GB eMMC partitioned as
> following:
>
> Device Boot Start End Sectors Size Id Type
> /dev/sdb1 2048 264191 262144 128M 83 Linux
> /dev/sdb2264192 445849
Tim Harvey writes:
> Greetings,
>
> In debugging an issue with a rather old branch of U-Boot (2015-04) I
> found that the static assignment of a data buffer was not 32-bit
> aligned which caused data aborts. However I find that current U-boot
> master does not suffer this issue and no matter what
On Tuesday 29 November 2016 04:23 PM, Marek Vasut wrote:
> On 11/29/2016 05:58 AM, Vignesh R wrote:
>>
>>
>> On Monday 28 November 2016 06:11 PM, Marek Vasut wrote:
>>> On 11/28/2016 10:37 AM, Vignesh R wrote:
On Friday 25 November 2016 10:21 PM, Marek Vasut wrote:
> On 11/24/2
Signed-off-by: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index 67d605e..ab83e85 100644
--- a
On 11/29/2016 05:58 AM, Vignesh R wrote:
>
>
> On Monday 28 November 2016 06:11 PM, Marek Vasut wrote:
>> On 11/28/2016 10:37 AM, Vignesh R wrote:
>>>
>>>
>>> On Friday 25 November 2016 10:21 PM, Marek Vasut wrote:
On 11/24/2016 06:35 AM, Vignesh R wrote:
> According to Section 11.15.4.9
On 11/29/2016 10:11 AM, Lukasz Majewski wrote:
> Hi Marek,
>
>> On 11/28/2016 10:09 PM, Lukasz Majewski wrote:
>>> This define gives the possibility to copy entire image (including
>>> header - e.g. u-boot.img) from NOR parallel memory to e.g. SDRAM.
>>> The current code only supports loading the
Hi Rick,
Am Montag, 28. November 2016, 15:09:05 schrieb Simon Glass:
> + A few rockchip people and linux-rockchip
>
> Hi Rick,
>
> On 25 November 2016 at 11:20, Rick Bronson wrote:
> > Hi All,
> >
> > I've got unsupported RK3288 hardware running the latest git u-boot to
> >
> > SPL as expla
Hi Simon,
Am Sonntag, 27. November 2016, 10:01:47 schrieb Simon Glass:
> This is the only RK3288 device without DHCP. Enable it so that we
^^ rk3288/rk3399?
> can use a common BOOT_TARGET_DEVICES setting. It is likely useful to be
> able to use USB networking, at least. Full
|-Original Message-
|From: Sudeep Holla [mailto:sudeep.ho...@arm.com]
|Sent: Tuesday, November 22, 2016 10:11 AM
|To: Tom Rini; Liviu Dudau
|Cc: Sudeep Holla; Lorenzo Pieralisi; Jeremy Linton; U-Boot ML
|Subject: Re: [U-Boot] [PATCH] vexpress64: Juno: Change PCI buss addresses
|for IO to
This driver compatible with pcf2127 and pcf2129
Signed-off-by: Meng Yi
---
drivers/rtc/Makefile | 1 +
drivers/rtc/pcf2127.c | 94 +++
2 files changed, 95 insertions(+)
create mode 100644 drivers/rtc/pcf2127.c
diff --git a/drivers/rtc/Makefile
On Mon, Nov 28, 2016 at 5:56 PM, Tom Rini wrote:
> On Fri, Nov 25, 2016 at 11:11:23AM +0100, Fabien Parent wrote:
>> In order to avoid having a random mac address assigned by Linux, let's
>> fixup the dtb with the mac address that was programmed in the EEPROM.
>>
>> Signed-off-by: Fabien Parent
>
Hi Chin Liang,
On 28 November 2016 12:49 See, Chin Liang wrote:
> On Jum, 2016-11-25 at 14:38 +, Phil Edworthy wrote:
> >
> > The Cadence QSPI controller has specified overheads for the various
> > CS
> > times that are in addition to those programmed in to the Device Delay
> > register. The o
From: Nishanth Menon
Both AM57xx and DRA7xx share the same set of base addresses for DWC
controllers. The usage however differ with DWC2 instance used typically
in AM57xx evms while DWC1 instances used in DRA7x platforms.
Use TARGET_SOC config to differentiate so that CONFIG_AM57XX can be droppe
From: Nishanth Menon
CONFIG_AM57XX is just an unnecessary macro that is redundant given So,
remove the same instead of spreading through out the u-boot source
code and getting in the way to maintain common code for DRA7x family.
Acked-by: Andrew F. Davis
Signed-off-by: Nishanth Menon
Signed-of
CONFIG_AM57XX is redundant as DRA7 and AM57xx uses the same SoC type.
This series removes this config.
Nishanth Menon (2):
usb: xhci: Remove assumption of DWC instance based on DRA7 SoC type
ARM: DRA7x/AM57xx: Get rid of CONFIG_AM57XX
arch/arm/include/asm/arch-omap5/clock.h| 2 +-
arch/a
Hi Simon,
On 11/26/2016 03:39 AM, Simon Glass wrote:
Hi Kever,
On 24 November 2016 at 00:29, Kever Yang wrote:
The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to
the usb host port, we need to de-assert its reset pin to enable it.
Signed-off-by: Kever Yang
---
Changes in
On Fri, Nov 25, 2016 at 10:35:15PM +0530, Jagan Teki wrote:
> On Tue, Nov 22, 2016 at 6:08 PM, Maxime Ripard
> wrote:
> > We will need the bch functions in the tool to generate the SPL images for
> > the Allwinner SoCs.
> >
> > Do the needed adjustments so that we can use it on the host.
> >
> > S
Hi Marek,
On 11/26/2016 12:46 AM, Marek Vasut wrote:
On 11/24/2016 08:29 AM, Kever Yang wrote:
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
---
Changes in
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