Hi Kever,
Dne petek, 24. marec 2017 ob 03:38:16 CET je Kever Yang napisal(a):
> Hi Jernej,
>
> On 03/24/2017 08:11 AM, Jernej Skrabec wrote:
> > MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
> > micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
> > ex
Hi Tom,
please pull the following Marvell patches mainly adding
support for some new boards, like the ARMv8 community
boards MACCHIATOBin and ESPRESSBin.
Thanks,
Stefan
The following changes since commit 5877d8f398de26617be6f1f57bc30c49e9f90ebb:
Merge branch 'master' of git://git.denx.de/u-bo
On 22.02.2017 16:07, Mario Six wrote:
From: Dirk Eibach
The gdsys ControlCenter Digital board is based on a Marvell Armada 38x
SOC.
It boots from SPI-Flash but can be configured to boot from SD-card for
factory programming and testing.
On board peripherals include:
- 2 x GbE
- Xilinx Kintex-7
On 22.02.2017 16:07, Mario Six wrote:
Certain boards come in different variations by way of utilizing daughter
boards, for example. These boards might contain additional chips, which
are added to the main board's busses, e.g. I2C.
The device tree support for such boards would either, quite natur
On 08.02.2017 16:34, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Add GPIO nodes to AP-806 and CP-110-master DTSI files.
Change-Id: I05958698d460cb721b7d8683d34f74a5ea32532c
Signed-off-by: Konstantin Porotchkin
Cc: Stefan Roese
Cc: Nadav Haklai
Cc: Igal Liberman
Cc: Haim Boot
C
On 16.02.2017 12:52, kos...@marvell.com wrote:
From: Konstantin Porotchkin
Modify the file names and deifinitions relater to Marvell
db-77f3720 board support. Convert these names to more generic
armada-37xx platform for future addition of more boards
based on the same SoC family.
Signed-off-by
+ Hua, Wilson
From: Ken Ma
Sent: 2017年3月24日 11:04
To: 'Stefan Roese'; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek; Kostya Porotchkin
Subject: RE: [EXT] Re: [PATCH 7/7] scsi: dts: a3700: add scsi node
Hi Stefan
Thanks a lot for your kind advice and help!
Please see my reply inline.
Because the MMC SPL puts the bbs section in the ddr memory, move
calling mem_init() before calling spl_init().
Signed-off-by: Wenyou Yang
---
Changes in v2: None
arch/arm/mach-at91/spl_atmel.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/spl_atmel.c
The MMC SPL locates the BSS section to a different memory region
from text, then use "_image_binary_end" variable to point to the
correct device tree location.
Signed-off-by: Wenyou Yang
---
Changes in v2:
- Drop [PATCH] ARM: at91: lds: add test SPL binary size and bbs size.
arch/arm/mach-at9
Before setting up the serial communications, bring in the serial
device from the device tree file.
Signed-off-by: Wenyou Yang
---
Changes in v2: None
arch/arm/mach-at91/spl_atmel.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/s
When OF_CONTROL is enabled, MMC boot device should not be detected
automatically, it should be MMC1 fixedly only the status "enabled"
is available.
Add NAND Flash boot device as well.
Signed-off-by: Wenyou Yang
---
Changes in v2: None
arch/arm/mach-at91/spl.c | 7 +++
1 file changed, 7 in
To support the driver model and device tree in SPL, fix the boot
device, bring in the serial device from device tree, and use
"_image_binary_end" variable to point to the correct device tree
location when CONFIG_SPL_SEPARATE_BSS is enabled.
Changes in v2:
- Drop [PATCH] ARM: at91: lds: add test S
Hi Philipp,
On 03/24/2017 06:27 AM, Philipp Tomsich wrote:
The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. i
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The armclk starts in slow mode (24MHz) on the rk3188, which results in U-Boot
> startup taking a lot of time (U-Boot itself, but also the rc4 decoding done
> in the bootrom).
>
> With default pmic settings we can always reach a safe frequency of 6
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The ARMCLK starts at 24MHz on the rk3188 which makes u-boot startup
> unnecessary slow. We can easily switch to 600MHz without involving
> the pmic and thus do this in the SPL to also make the rc4-decoding
> of the U-Boot image faster.
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The Cortex-A9 socs rk3066 and rk3188 share the IP but have their own
> compatible values, so add them to make the i2c on these platforms accessible.
>
> Signed-off-by: Heiko Stuebner
> ---
> drivers/i2c/rk_i2c.c | 2 ++
> 1 file changed, 2 inser
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole
> startup take a lot of time. We therefore want to at least move to the safe
> 600MHz value we can use with default pmic settings.
> This is also the freqency the propriet
Hi Heiko,
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The rk3066/rk3188 introduced new i2c IP blocks but kept the old ones
> around just in case. The default also points to these old controllers.
>
> The "new" blocks proved stable and nobody ever used the old ones anywhere,
> not in the ke
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> The rock board uses the already existing act8846 as pmic, so enable the
> driver and needed pmic options for it.
>
> Signed-off-by: Heiko Stuebner
> ---
> configs/rock_defconfig | 4
> 1 file changed, 4 insertions(+)
Acked-by: Simon Glass
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> There was still a static ram value set in the rk3188-board from the
> time where we didn't have actual sdram init code.
> Now the sdram init leaves the ram information in SYS_REG2 and we can
> decode it similarly to the rk3288.
>
> Right now we ha
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> In the beginning, we did SPL -> TPL -> U-Boot, but after clarification
> of the real ordering swapped SPL and TPL.
> It seems some renames were forgotten and may confuse future readers, so
> also swap these to reflect the actual ordering.
>
> Sign
On 20 March 2017 at 05:40, Heiko Stuebner wrote:
> Right now we're setting the wrong value of 0 as base in the ram_info struct,
> which is obviously wrong for the rk3188. So instead set the correct value
> we already have in CONFIG_SYS_SDRAM_BASE.
>
> Signed-off-by: Heiko Stuebner
> ---
> arch/a
Hi Stefan
Thanks a lot for your kind advice and help!
Please see my reply inline.
Yours,
Ken
-Original Message-
From: Stefan Roese [mailto:s...@denx.de]
Sent: 2017年3月23日 22:06
To: Ken Ma; u-boot@lists.denx.de
Cc: Simon Glass; Michal Simek
Subject: [EXT] Re: [PATCH 7/7] scsi: dts:
Hi Heiko,
On 03/24/2017 07:41 AM, Heiko Stuebner wrote:
Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.
Signed-off-by: Heiko Stuebner
---
doc/READ
Hi Jernej,
On 03/24/2017 08:11 AM, Jernej Skrabec wrote:
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/Makefile |
Hi Philipp,
On 03/24/2017 06:24 AM, Philipp Tomsich wrote:
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB and for the RK3399-Q7 can be updated.
Signed-off-by: Philipp Tomsich
---
Chan
Hi Philipp,
On 03/24/2017 06:24 AM, Philipp Tomsich wrote:
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as
Simon,
I made it work. A patch set will be sent later (much later) after I
clean up and finish the project on hand.
York
On 03/22/2017 04:40 PM, york@nxp.com wrote:
> Guys,
>
> You were discussing loading FIT image for falcon boot about a year ago.
> I wonder if there is any follow-up on th
On 3/24/2017 3:54 AM, Lukasz Majewski wrote:
> Up till this commit passing NULL as input parameter was allowed, but not
> handled properly.
>
> When one passed NULL to one of this function parameters, the code was
> executed causing data abort.
>
> However, what is more interesting, the abort w
This patch adds the steps to manually (re)build a Quartus FPGA project,
generate the required BSP glue, and update u-boot handoff files for
mainline SPL support. Requires Quartus toolchain and current U-Boot.
Signed-off-by: Steve Arnold
Cc: Dinh Nguyen
Cc: Stefan Roese
Cc: Marek Vasut
---
Chan
On Thu, Mar 23, 2017 at 09:41:34AM -0600, Simon Glass wrote:
> Hi Tom,
>
> Here are the patches that survived testing so far. More to come next week.
>
>
> The following changes since commit 5877d8f398de26617be6f1f57bc30c49e9f90ebb:
>
> Merge branch 'master' of git://git.denx.de/u-boot-mmc (
The sama5d36ek CMP board is the variant of sama5d3xek board.
It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865, and
some power rails. The board is mainly used to measure the power
consumption. As all those changes are done in at91bootstrap,
in U-Boot, only use another device tree file, no
Add the device tree file for sama5d4ek board.
The dts file is copied from Linux-4.4, do the following changes.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compilation warning.
Signed-off-by: Wenyou Yang
-
Add the device tree files for sama5d4 Xplained board.
The dts files are copied from Linux-4.4, do the following changes.
- add reg property for pinctrl node.
- move the gpio nodes(pioA, pioB, pioC ...) from the pinctrl child's
nodes to its slibling nodes.
- add the "u-boot,dm-pre-reloc" prop
Add the device tree file for sama5d3 Xplained board.
The dts files are copied from the Linux-4.9, do changes as below.
- add the "u-boot,dm-pre-reloc" property to determine which nodes
which are needed by SPL and by the board_init_f stage.
- fix the compile warning.
Signed-off-by: Wenyou Yan
Add the device tree files for sama5d3xek board.
The dts files are copied from Linux-4.9, do the changes as below.
- add reg property for the pinctrl node.
- move the gpio nodes (pioA, pioB, pioC ...) as the pinctrl's
slibling nodes.
- add the "u-boot,dm-pre-reloc" property to determine which
The purpose of the patchset is add the device tree files for boards,
sama5d3/sama5d4 Xplained board and sama5d3/sama5d4 EK board.
Changes in v6:
- Fix the missing "u-boot,dm-pre-reloc" property for sama5d36ek_cmp board.
Changes in v5:
- Integrate the dts patches for sama5d3 to one.
- Add the "
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/atmel/sama5d3xek/sama5d3xek.c| 13 -
configs/sama5d3xek_mmc_defconfig | 6
Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
configs/sama5
Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: Wenyou Yang
---
Changes in v4: None
Changes in v3:
- Convert the macb to support DM and clean up macb init code.
- Remain the SPI speed macros.
- Update the config options for S
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/atmel/sama5d3_xplain
Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: Wenyou Yang
---
Changes in v4:
- Remove the ethernet init code completely.
Changes in v3: None
Changes
Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: Wenyou Yang
---
Changes in v4:
- Remove wrong using CONFIG_PHY_MICREL.
Changes in v3: Non
The purpose of patch set is to convert the board to support device
tree and driver model, and enable the early debug UART as well.
It is based on the patch set:
[PATCH v8 0/2] pinctrl: at91: Add pinctrl driver
https://lists.denx.de/pipermail/u-boot/2017-March/284577.html
Changes in
On Tue, Mar 21, 2017 at 4:22 PM, Simon Glass wrote:
>
> Hi Maxim,
>
> On 16 March 2017 at 15:36, Maxim Sloyko wrote:
> > Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
> > perform resets and thus depends on it. The actual Watchdog device used
> > needs to be configured in De
Thank you Joe for your time and feedback,
Please see the answers inline.
Suji
On Tue, Mar 21, 2017 at 11:53 AM, Joe Hershberger wrote:
> On Fri, Mar 3, 2017 at 7:06 PM, Steve Rae wrote:
> > From: Suji Velupillai
> >
> > move to Kconfig:
> > CONFIG_BCM_SF2_ETH
> > CONFIG_BCM_SF
Hi,
I'm new to Uboot. Can someone help me.
I went through the tbl_table (in tlb.c) and got puzzled by the following
entries:
...
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
...
SET_T
On Wed, Mar 22, 2017 at 6:06 AM, Simon Glass wrote:
> Hi Maxim,
>
> On 21 March 2017 at 17:44, Maxim Sloyko wrote:
> > Hi Joe,
> >
> > Please see responses inline, simply ACK'ed comments will be addressed
> > in the next version.
> >
> > On Tue, Mar 21, 2017 at 12:32 PM, Joe Hershberger
> > wro
MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
expansion ports.
Signed-off-by: Jernej Skrabec
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/rk3288-miqi.dts| 46
a
Building sd images for rk3188 requires more steps due to the needed split
into TPL and SPL as loaders. Describe how to build an image for it in a
separate paragraph in the READER.rockchip file.
Signed-off-by: Heiko Stuebner
---
doc/README.rockchip | 26 ++
1 file changed,
The Rock is a RK3188 based single board computer by Radxa.
Currently it still relies on the proprietary DDR init and
cannot use the generic SPL, but at least is able to boot
a linux kernel and system up to a regular login prompt.
Signed-off-by: Heiko Stuebner
Reviewed-by: Simon Glass
Tested-by:
Commit c67c8c604b6c ("board_init.c: Always use memset()") dropped the naive
memset alternative from board_init_f_init_reserve.
So activate CONFIG_TPL_LIBGENERIC for that common memset implementation.
We cannot use the ARCH-specific memset, as that would incur 200bytes of
additional TPL size, space
Applies on top of current rockchip master branch and needs
Kever's early_init patch for rk3188 and rk3399.
After this one series, there is of course still
rockchip: rk3188: fixups and armclk speedup
series and
rockchip: rk3188: enable remap function
patch open.
changes compared to the or
The BootROM of the RK3399 SoC does not initialise the cntfrq_el0 (which
holds the value 0 (zero) on entry into the SPL. This causes the timebase
for U-Boot not to advance (and will cause a hang where a timeout would
be expected... e.g. if something goes wrong during MMC/SD card startup).
This chan
Up till this commit passing NULL as input parameter was allowed, but not
handled properly.
When one passed NULL to one of this function parameters, the code was
executed causing data abort.
However, what is more interesting, the abort was not caught because of code
execution in HYP mode with mask
With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB and for the RK3399-Q7 can be updated.
Signed-off-by: Philipp Tomsich
---
Changes in v2: None
configs/evb-rk3399_defconfig| 2 ++
conf
The default configuration for debug output from the RK3399 SPL is
UART2 at 1.5MBaud. While this works reasonably well for the EVB,
custom boards may want to change these settings.
To simplify the enablement (i.e. to use the RS232 connector on our
baseboard and to improve the compatibility with co
The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).
To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the
On Thu, Mar 23, 2017 at 12:32 PM, Suji Velupillai
wrote:
> Thank you Joe for your time and feedback,
> Please see the answers inline.
> Suji
>
>
> On Tue, Mar 21, 2017 at 11:53 AM, Joe Hershberger
> wrote:
>>
>> On Fri, Mar 3, 2017 at 7:06 PM, Steve Rae wrote:
>> > From: Suji Velupillai
>> >
>>
Hi,
On 23 March 2017 at 12:36, Sébastien Basset wrote:
>
>
>
> 2017-03-23 3:19 GMT+01:00 Simon Glass :
>>
>> Hi,
>>
>> On 22 March 2017 at 10:35, Sébastien Basset wrote:
>> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
>> > 2/ Now i try to boot on usb key, but i don't see cont
2017-03-23 3:19 GMT+01:00 Simon Glass :
> Hi,
>
> On 22 March 2017 at 10:35, Sébastien Basset wrote:
> > 1/ No, As i am stuck on the mmc (pci controller internal soc),
> > 2/ Now i try to boot on usb key, but i don't see controller usb
> > Sorry, these are two different problems.
>
> It is better
ft_cpu_setup() already calls fdt_fixup_ethernet(), calling it
in image_setup_libfdt() is both redundant and breaks any modifications
done by ft_board_setup(). Restore the old behavior by removing
the call in image_setup_libfdt()
Signed-off-by: Joakim Tjernlund
---
common/image-fdt.c | 1 -
1 fil
Add a missing occurrance of PHY_INTERFACE_MODE_RGMII_ID, which should
be handled identical to PHY_INTERFACE_MODE_RGMII.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Cc: Joe Hershberger
---
Changes in v2:
- New patch
drivers/net/mvpp2.c | 1 +
1 fil
Hi Simon,
Am Donnerstag, 23. März 2017, 10:18:31 CET schrieb Simon Glass:
> On 21 February 2017 at 13:35, Simon Glass wrote:
> > On 18 February 2017 at 11:46, Heiko Stuebner wrote:
> >> The Rock is a RK3188 based single board computer by Radxa.
> >> Currently it still relies on the proprietary D
This patch does a bit of restructuring of the probe / init functions,
mainly to allow earlier register access as it is needed for the upcoming
GoP (Group of Ports) and NetC (Net Complex) code.
Signed-off-by: Stefan Roese
Cc: Joe Hershberger
---
Changes in v2:
- New patch
drivers/net/mvpp2.c
From: Thomas Petazzoni
This commit adds the description of the PPv2.2 hardware block for the
Marvell Armada 7K and Armada 8K processors, and their corresponding Armada
7040 and 8040 Development boards.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
On PPv2.2 we enable PHY polling, so we also need to configure the PHY
address in the specific PHY address rgisters.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers/net/mvpp
From: Thomas Petazzoni
Now that the mvpp2 driver has been modified to accommodate the support
for PPv2.2, we can finally advertise this support by adding the
appropriate compatible string.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v
This patch adds a remove function to the mvpp2 ethernet driver which is
called before the OS is started, doing:
- Allocate the used buffers back from the buffer manager
- Stop the BM activity
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Acked-by: Joe H
As pointed out by Stefan Chulski, this variable is unused and should be
removed.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
- Fixed small typo in commit text
drivers/net/mvpp2.c | 4
1 file changed, 4 deletions(
The Marvell PHY support is needed espescially for the A7040-DB with the
SGMII port (port 2). As without the marvell PHY driver configuration
for SGMII, ethernet won't work.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Acked-by: Joe Hershberger
---
Ch
This fixes problems noticed with the PPv2.2 A7k/8k port, when not all
elements of the descriptors had been cleared before use.
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers/net/mvpp2.c | 3 +++
1 file changed, 3 insertions(+)
diff
In U-Boot the MDIO / SMI support is integrated in the mvpp2 driver,
currently only supporting the 32bit platforms (Armada 37x). This patch
now adds the A7k/8k PPv2.2 MDIO support to that the phy / mii IF
can be used as well on these platforms.
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
The default configuration for the COMPHY-0 port should be 1G, as its
used as 1G SGMII connection. This change is necessary to get the
MAC2 port (SGMII) working on this DB.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Acked-by: Joe Hershberger
---
Cha
From: Thomas Petazzoni
In PPv2.1, we have a maximum of 8 RXQs per port, with a default of 4
RXQs per port, and we were assigning RXQs 0->3 to the first port, 4->7
to the second port, 8->11 to the third port, etc.
In PPv2.2, we have a maximum of 32 RXQs per port, and we must allocate
RXQs from th
From: Thomas Petazzoni
This commit modifies the mvpp2_defaults_set() function to not do the
loopback and FIFO threshold initialization, which are not needed for
PPv2.2.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver for the missing port 0. This code is
mostly copied from the Marvell U-Boot version and was written by Stefan
Chulski. Please note that only SFI support have been added, as this
is the only int
From: Thomas Petazzoni
This commit adjusts the allocation and freeing of BM pools to support
PPv2.2. This involves:
- Checking that the number of buffer pointers is a multiple of 16, as
required by the hardware.
- Adjusting the size of the DMA coherent area allocated for buffer
pointers. In
From: Thomas Petazzoni
This commit handles a few miscellaneous differences between PPv2.1 and
PPv2.2 in different areas, where code done for PPv2.1 doesn't apply for
PPv2.2 or needs to be adjusted (getting the MAC address, disabling PHY
polling, etc.).
Changed by Stefan for U-Boot:
Since mvpp2_p
This patch adds the GoP (Group of Ports) and NetC (Net Complex) setup to
the Marvell mvpp2 ethernet driver. This code is mostly copied from the
Marvell U-Boot version and was written by Stefan Chulski. Please
note that only RGMII and SGMII support have been added, as these are
the only interfaces t
From: Thomas Petazzoni
The MVPP2_RXQ_CONFIG_REG register has a slightly different layout
between PPv2.1 and PPv2.2, so this commit adapts the functions modifying
this register to accommodate for both the PPv2.1 and PPv2.2 cases.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked
From: Thomas Petazzoni
The mvpp2_bm_bufs_add() currently creates a fake cookie by calling
mvpp2_bm_cookie_pool_set(), just to be able to call
mvpp2_pool_refill(). But all what mvpp2_pool_refill() does is extract
the pool ID from the cookie, and call mvpp2_bm_pool_put() with this ID.
Instead of d
From: Thomas Petazzoni
The PPv2.2 unit is connected to an AXI bus on Armada 7K/8K, so this
commit adds the necessary initialization of the AXI bridge.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers
From: Thomas Petazzoni
In preparation to the introduction for the support of PPv2.2 in the
mvpp2 driver, this commit adds a hw_version field to the struct
mvpp2, and uses the .data field of the DT match table to fill it in.
Having the MVPP21 and MVPP22 definitions available will allow to start
a
This patch adds the new PHY interface modes XAUI, RXAUI and SFI that will
be used by the PPv2.2 support in the Marvell mvpp2 ethernet driver.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Kostya Porotchkin
Cc: Nadav Haklai
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by f
From: Thomas Petazzoni
This commit adjusts the mvpp2 driver register mapping and access logic
to support PPv2.2, to handle a number of differences.
Due to how the registers are laid out in memory, the Device Tree binding
for the "reg" property is different:
- On PPv2.1, we had a first area for
The macro GENMASK_ULL needs the BITS_PER_LONG_LONG macro which is
defined in the bitsperlong.h header. Lets include this header as
the upcoming A7k/8k support in the Marvell mvpp2 ethernet driver
uses this macro.
Signed-off-by: Stefan Roese
Reviewed-by: Tom Rini
Reviewed-by: Joe Hershberger
--
Hi Heiko,
On 21 February 2017 at 13:35, Simon Glass wrote:
> On 18 February 2017 at 11:46, Heiko Stuebner wrote:
>> The Rock is a RK3188 based single board computer by Radxa.
>> Currently it still relies on the proprietary DDR init and
>> cannot use the generic SPL, but at least is able to boot
From: Thomas Petazzoni
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers/net/mvpp2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index
From: Thomas Petazzoni
The mvpp2 is going to be extended to support the Marvell Armada 7K/8K
platform, which is ARM64. As a preparation to this work, this commit
enables building the mvpp2 driver on ARM64, by:
- Adjusting the Kconfig dependency
- Fixing the types used in the driver so that th
This patch moves the base_probe function mvpp2_base_probe() from the
MISC driver to the ETH driver. When integrated in the MISC driver,
probe is called too early before the U-Boot ethernet infrastructure
(especially the MDIO / PHY interface) has been initialized. Resulting
in errors in mdio_registe
From: Thomas Petazzoni
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers/net/mvpp2.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 365180d456..4
Since Armada 7K/8K is also equipped with a newer version of the MVPP2
ethernet controller, lets enable compilation of this driver for these
platforms.
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
drivers/net/Kconfig | 6 +++---
1 file cha
Since we've now integrated the A7k/8k support in the mvpp2 ethernet
driver, lets enable the support for both Marvell developments boards.
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
configs/mvebu_db-88f7040_defconfig | 2 +-
configs/mveb
From: Thomas Petazzoni
In PPv2.2, the MVPP2_RXQ_DESC_ADDR_REG and MVPP2_TXQ_DESC_ADDR_REG
registers have a slightly different layout, because they need to contain
a 64-bit address for the RX and TX descriptor arrays. This commit
adjusts those functions accordingly.
Signed-off-by: Thomas Petazzon
Testing shows, that PHY polling needs to be enabled on Armada 7k/8k.
Otherwise ethernet transfers will not work correctly. PHY polling
is enabled per default after reset, so we do not need to specifically
enable it, but this makes it clearer.
Signed-off-by: Stefan Roese
Cc: Stefan Chulski
Cc: Ko
From: Thomas Petazzoni
Since the format of the HW descriptors is different between PPv2.1 and
PPv2.2, this commit introduces an intermediate union, with for now
only the PPv2.1 descriptors. The bulk of the driver code only
manipulates opaque mvpp2_tx_desc and mvpp2_rx_desc pointers, and the
descr
From: Thomas Petazzoni
This commit adjusts how the MVPP2_ISR_RXQ_GROUP_REG register is
configured, since it changed between PPv2.1 and PPv2.2.
Signed-off-by: Thomas Petazzoni
Signed-off-by: Stefan Roese
Acked-by: Joe Hershberger
---
Changes in v2:
- Added Acked-by from Joe
- Rebased on late
From: Thomas Petazzoni
The PPv2.2 IP has a different TX and RX descriptor layout compared to
PPv2.1. In order to prepare for the introduction of PPv2.2 support in
mvpp2, this commit adds accessors for the different fields of the TX
and RX descriptors, and changes the code to use them.
For now, t
From: Thomas Petazzoni
Some of the MVPP2_PRS_RI_* definitions use the ~(value) syntax, which
doesn't compile nicely on 64-bit. Moreover, those definitions are in
fact unneeded, since they are always used in combination with a bit
mask that ensures only the appropriate bits are modified.
Therefor
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