Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++-
drivers/clk/aspeed/clk_ast2500.c | 11 +++
2 files changed, 13 insertions(+
Most Allwinner H5 boards start with VDD-CPUX at 1.1V (e.g. Orange Pi PC2,
NanoPi NEO2). Clocking it at 1008MHz is not so safe, and have shown
frequent CPU hang on my NanoPi NEO2 board.
Currently the ATF will also clock the system to 816MHz at boot.
So assign the default clock rate of H5 to 816MHz
On 2017-04-14, xypron.g...@gmx.de wrote:
> 0x1000 is the start of a 2 MiB area used by the
> ARM Trusted Firmware (BL31).
>
> See
> https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/tree/arch/arm64/boot/dts/amlogic/meson-gx.dtsi?id=refs/tags/v4.10.10
>
> So we should not l
On 2017-04-15, xypron.g...@gmx.de wrote:
> To enable automatic booting from SD card or eMMC the MMC
> devices 0, 1, and 2 are added to the BOOT_TARGET_DEVICES.
>
> Booting from SD card, eMMC, and DHCP are tried in sequence.
> A missing or failing device is gracefully handled.
>
> Cc: Andreas Färber
On 04/16/2017 09:34 PM, Simon Glass wrote:
> Hi Alex,
>
> On 16 April 2017 at 04:08, Alexander Graf wrote:
>>
>>
>> On 16.04.17 04:09, Heinrich Schuchardt wrote:
>>>
>>> On 04/15/2017 11:51 PM, Andreas Färber wrote:
Am 15.04.2017 um 23:16 schrieb Andreas Färber:
>
> Am 15.04.201
On Sat, Apr 15, 2017 at 10:45:35AM -0600, Simon Glass wrote:
> Hi Tom,
>
> This includes the DM LED support, some more Atmel patches and as much
> of the SCSI changes as I can apply so far. I have not applied the
> generic phy changes yet as I still have some nits.
>
>
> The following changes s
On Sat, Apr 15, 2017 at 12:55:38PM -0600, Simon Glass wrote:
> Hi Tom.
>
> Here are the rest of the rockchip changes. I have not been able to
> include the MIPI driver as it still needs work. Depending on timing
> that might come later but more likely it will go to -next.
>
>
> The following ch
Hey all,
It's release day and v2017.05-rc2 is out. I think my patchwork queue is
looking good currently. I have some outstanding removal patches to take
from Masahiro related to architectures that I removed as promised. The
release is bigger than I really wanted, but since I was on vacation for
On 2017-04-16, Andreas Färber wrote:
> Am 17.04.2017 um 00:01 schrieb Vagrant Cascadian:
>> Enable distro_bootcmd PXE functions on meson-gxbb systems.
>>
>> While DHCP boot is already supported, the format is fairly u-boot
>> specific, while PXE boot supports the widely used syslinux style boot
>>
From: Fabio Estevam
Select CONFIG_FSL_IIM and CONFIG_CMD_FUSE so that the fuse API can
be used.
Signed-off-by: Fabio Estevam
---
include/configs/mx25pdk.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index 4cee64d..eb64eda 100644
On 04/18/2017 06:18 AM, Heinrich Schuchardt wrote:
> On 04/16/2017 09:34 PM, Simon Glass wrote:
>> Hi Alex,
>>
>> On 16 April 2017 at 04:08, Alexander Graf wrote:
>>>
>>>
>>> On 16.04.17 04:09, Heinrich Schuchardt wrote:
On 04/15/2017 11:51 PM, Andreas Färber wrote:
>
> Am 15.04.
Am 18.04.2017 um 00:26 schrieb Vagrant Cascadian:
> DHCP the protocol is not at all u-boot specific, sure, but the boot
> method:
>
> #define BOOTENV_DEV_DHCP(devtypeu, devtypel, instance) \
> "bootcmd_dhcp=" \
> BOOTENV_RUN_NET_USB_START \
> BOOTENV_RUN_NET_PCI_E
On 04/17/2017 06:47 AM, Andreas Färber wrote:
> Am 16.04.2017 um 21:33 schrieb Simon Glass:
>> On 14 April 2017 at 04:27, Heinrich Schuchardt wrote:
>>> As a prerequisite for adding a Meson GX MMC driver update the
>>> Meson GXBB / Odroid-C2 device tree in Uboot with the latest
>>
>> U-Boot
>>
>>>
On 2017-04-17, Andreas Färber wrote:
> Am 18.04.2017 um 00:26 schrieb Vagrant Cascadian:
>> I guess I was referring to "source ${scriptaddr}; " line, which is quite
>> u-boot specific. I didn't realize that "DHCP" also had support for EFI
>> loaded over the network.
>
> DHCP just sets a filename th
Hi Fabio,
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Monday, April 17, 2017 11:00 PM
> To: Peng Fan
> Cc: Stefano Babic ; U-Boot-Denx
> Subject: Re: [U-Boot] [PATCH V2 12/12] imx: mx7dsabresd: add board revision
> check
>
> On Thu, Apr 13, 2017 at 3:1
On Mon, Apr 17, 2017 at 6:39 PM, Marek Vasut wrote:
> On 04/17/2017 05:05 AM, Ley Foon Tan wrote:
>> On Fri, Apr 14, 2017 at 6:25 PM, Marek Vasut wrote:
>>> On 04/13/2017 07:41 PM, Ley Foon Tan wrote:
Add config and defconfig for the Arria10 and update socfpga_common.h.
Signed-off-
Hi Marek,
On 04/06/2017 06:20 PM, Marek Vasut wrote:
On 04/06/2017 10:34 AM, Kever Yang wrote:
Hi Eddie,
On 04/06/2017 10:14 AM, Marek Vasut wrote:
On 04/06/2017 04:03 AM, Eddie Cai wrote:
We should invalidate the dcache before starting the DMA. In case
there are
any dirty lines from the DM
On 17 April 2017 at 02:42, Kever Yang wrote:
> RK3399 device memory region is 0xf800~0x.
>
> Signed-off-by: Kever Yang
> ---
>
> arch/arm/mach-rockchip/rk3399/rk3399.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Simon Glass
___
On 17 April 2017 at 03:48, Kever Yang wrote:
> The pwm3 on evb-rk3399 is used for pwm regulator, need to invert
> the polarity to make it works correct.
make it work correctly.
>
> Signed-off-by: Kever Yang
> ---
>
> arch/arm/dts/rk3399-evb.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletio
On 17 April 2017 at 03:48, Kever Yang wrote:
> Enable gmac for evb-rk3399.
>
> Signed-off-by: Kever Yang
> ---
>
> Changes in v2:
> - correct rst pin number
>
> arch/arm/dts/rk3399-evb.dts | 24
> configs/evb-rk3399_defconfig | 4
> 2 files changed, 28 insertions(+)
A
On 17 April 2017 at 08:24, Eric Gao wrote:
> Modify Makefile for rockchip video driver according to Kconfig, so that
> source code will not be compiled if not needed.
>
> Signed-off-by: Eric Gao
> ---
>
> drivers/video/rockchip/Makefile | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
On 17 April 2017 at 08:24, Eric Gao wrote:
> 1. add Kconfig for rockchip video driver, so that video port can be
> selected as needed.
> 2. move VIDEO_ROCKCHIP option to new Kconfig for concision.
>
> Signed-off-by: Eric Gao
>
> ---
>
> configs/chromebit_mickey_defconfig | 1 +
> configs/chromeboo
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> For the RK3399, i2c_set_rate (and by extension: our spi_set_rate,
> which had been mindlessly following the template of the i2c_set_rate
> implementation) miscalculates the rate returned due to a off-by-one
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> The original code for the clock clamping did not support going up to
> half the module input frequency (even when clocking the module at
> 99MHz), as a hard limit (of 48MHz) was used for the maximum bitrate
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> This change adds support for configuring the module clocks for SPI1 and
> SPI5 from the 594MHz GPLL.
>
> Note that the driver (rk_spi.c) always sets this to 99MHz, but the
> implemented functionality is mor
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> From: Jakob Unterwurzacher
>
> The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
> block found in the RK3399. This has been confirmed both with SPI NOR
> flashes and general SPI transfe
Hi Philipp,
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> To provide more (runtime) configuration points for the SPI data rate
> at higher speeds (e.g. above 9MHz), we increase the module input rate
> to 198MHz (from 99MHz) for the RK3399.
>
> Signed-
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> Dumpimage (it invoked with "-T rkspi" or "-T rksd") would not work due
> to check_params failing. These changes ensure that we can both be called
> with an empty imagename.
>
> Signed-off-by: Philipp Tomsic
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
Commit message?
> Signed-off-by: Philipp Tomsich
> ---
>
> tools/rksd.c | 7 +--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
Acked-by: Simon Glass
_
Hi Eric,
On 17 April 2017 at 08:21, Eric Gao wrote:
> Eric Gao (8):
> rockchip: video: Add mipi dsi driver for rk3399
> rockchip: video: vop: Add mipi display mode for rk3399
> rockchip: video: vop: Set different bitwidth for different display mode
> rockchip: video: vop: Reserve enough space for
On 17 April 2017 at 09:50, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> The DDR3-1333 timings for the RK3399-Q7 (Puma) has some unintended
> left-over comments in them. This change cleans the file up.
>
> Signed-off-by: Philipp Tomsich
> ---
>
> arch/arm/dts/rk3399-sdram-ddr3-
Hello Heinrih,
Am 15.04.2017 um 16:25 schrieb Heinrich Schuchardt:
A size_t variable can never be negative.
The problem was indicated by cppcheck.
Signed-off-by: Heinrich Schuchardt
---
cmd/ubi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Heiko Schocher
bye,
Hei
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> The calculation of the variable header size in rkcommon_vrec_header
> had been update twice in the earlier series (introducing boot0-style
> images to deal with the alignment of the first instruction in 64b
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> To include the ability to load from an SPI flash in SPL, it's not
> sufficient to define SPL_SPI_SUPPORT and SPL_SPI_FLASH_SUPPORT via
> Kconfig... so we conditionally define SPL_SPI_LOAD if SPI support
> i
On 17 April 2017 at 09:43, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> This commit adds support for the pin-configuration of the SPI5
> controller of the RK3399 through the following changes:
> * grf_rk3399.h: adds definition for configuring the SPI5 pins
> in the GPIO2C group
On 17 April 2017 at 09:45, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> For the RK3399-Q7, we need some flexibility (depending on the feature
> set we include in the SPL stage and how large our SPI flash is) in
> positioning the SPL payload (i.e. the FIT image containing U-Boot
On 17 April 2017 at 09:45, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> When OF control is enabled for the SPL stage, nodes are removed from
> the DTB to reduce its size. While /chosen is kept, /config is removed.
>
> There's no reason why /chosen should be kept over /config (a
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
>
> Our earlier change broke the generation of SPI images, by excluding the
> 2K used for header0 from the size-calculation.
>
> This commit makes sure that these are included before calculating the
> require
On 17 April 2017 at 09:45, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> This adds documentation on the u-boot,spl-payload-offset property
> (which overrides CONFIG_SYS_SPI_U_BOOT_OFFS during the SPI loading in
> the SPL stage, if present).
>
> Signed-off-by: Philipp Tomsich
>
Hi Philipp,
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> The rockchip image generation was previously missing the ability to
> verify the generated header (and dump the image-type) without having
> to resort to hexdump or od. Experience in our testin
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> The imagetool framework checks whether function pointer for the verify,
> print and extract actions are available and will will handle their
> absence appropriately.
>
> This change removes the unnecessary
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> This change set adds documentation to the header0 initialisation and
> improves readability for the calculations of various offsets/lengths.
>
> As the U-Boot SPL stage doesn't use any payload beyond what i
On 17 April 2017 at 09:48, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> In (first) breaking and (then) fixing the rkspi tool, I realised that
> the calculation of the required padding (for the header-size and the
> 2K-in-every-4K SPI layout) was not as self-explainatory as it c
On 17 April 2017 at 09:50, Philipp Tomsich <
philipp.toms...@theobroma-systems.com> wrote:
> With the validation done for DDR3-1600 (i.e. 800 MHz bus clock), we
> add the timings (rk3399-sdram-ddr3-1600.dtsi) and change rk3399-puma.dts
> to use these by default.
>
> Signed-off-by: Philipp Tomsich
Hi Jonas,
On 17 April 2017 at 15:13, Jonas Karlman wrote:
> Set ethernet mac address in late init for Tinker Board,
> prevents getting a random mac address each boot.
>
> Read mac address from eeprom, first 6 bytes from 0x50 on i2c2.
> Same as /etc/init.d/rockchip.sh on Tinker OS.
>
> Signed-off-
Hello Tom,
please pull from u-boot-ubi.git master
The following changes since commit f6c1df44b815a08585e7fd3805a1db51a5955d09:
Prepare v2017.05-rc2 (2017-04-17 18:16:49 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-ubi.git master
for you to fetch changes up to 1
On Tue, Apr 4, 2017 at 5:04 PM, Maxime Ripard
wrote:
> On Tue, Apr 04, 2017 at 03:26:55PM +0530, Jagan Teki wrote:
>> On Tue, Apr 4, 2017 at 3:11 PM, Maxime Ripard
>> wrote:
>> > On Tue, Apr 04, 2017 at 02:25:09PM +0530, Jagan Teki wrote:
>> >> On Tuesday 04 April 2017 01:42 PM, Maxime Ripard wro
On Sat, Mar 4, 2017 at 1:55 AM, Jelle van der Waa wrote:
> Add myself as maintainer of the NanoPi NEO Air board.
>
> Signed-off-by: Jelle van der Waa
Applied to u-boot-sunxi/master
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, In
On Fri, Apr 14, 2017 at 10:14 PM, Andreas Färber wrote:
> Currently $fdtfile is constructed from CONFIG_DEFAULT_TREE, containing
> the filename. However on arm64 that file is located in an allwinner
> subdirectory.
>
> To avoid the need for users/distros symlinking the .dtb files, prepend
> the ve
The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.
The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.
The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off
Hi everyone,
This is a resend of my Allwinner R40 SoC support series v2.
This is rebased on v2017.05-rc2. Maxime's ack for the first
two patches have been added, and the defconfig has been
regenerated which moved the CONFIG_SPL_I2C_SUPPORT=y line
around.
The patches can also be found here:
https
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/mach-sunxi/pmic_bus.c | 7 ++
According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.
This patch enables it for all the PLLs.
Signed-off-by: Chen-Yu Tsai
Acked-b
Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.
Fortunately Kconfig makes it easy to split them. The Kconfig language
document states
If multiple dependencies ar
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/
The R40 has the CPUCFG block at the same address as the A20.
Fix it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
b/arch/
The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/s
The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/timer.h| 5 ++---
arch/arm/include/asm/arch-sunxi/watchdog.h | 5 -
arch/arm/mac
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/board.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.
The Bananapi M2 Ultra is the first publicly available development board
featuring the R40 SoC.
This patch add barebone dtsi/dts files for the R40 and Bananapi M2 Ultra,
as well as a defconfig for it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/dts/Makefile
The R40's CPU controls are a combination of sun6i and sun7i.
All controls are in the CPUCFG block, and it seems the R40 does not
have a PRCM block. The core reset, power gating and clamp controls
are grouped like sun6i.
Last, the R40 does not have a secure SRAM block.
This patch adds a PSCI impl
These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff -
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 94d01cb5c1ec..5bc4ce037f54 100644
The device tree source files of AT91 SoCs's board are copied from
the Linux v4.10, and have some changes.
Changes in v3:
- Add Reviewed-by tag.
- Rebase on the master branch(ad46af0e76) of u-boot-dm git tree.
Changes in v2:
- Rebase on the master branch (22e10be45) of u-boot-dm git tree.
Weny
The device tree source files of at91sam9x5ek board are copied from
the Linux v4.10, do the changes below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc" prop
The device tree source files of at91sam9m10g45ek boards are copied
from the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm
The device tree source files of at91sam9n12ek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Change the compatible of th
The device tree source files of at91sam9g20ek and at91sam9260ek
boards are copied from the Linux v4.10, do the changes below.
- Fix the build error for the usb0 node.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
slibling nodes, ins
The device tree source files of at91sam9rlek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pre-reloc
The device tree source files of at91sam9263ek boards are copied from
the Linux v4.10, do the changes as below.
- Add the reg property for the pinctrl node.
- Move the gpio (pioA, pioB, pioC, pioD, pioE) nodes as the pinctrl's
slibling nodes, instead of the child nodes.
- Add the "u-boot,dm-pr
> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 13, 2017 9:15 PM
> To: Santan Kumar ; u-boot@lists.denx.de
> Cc: Priyanka Jain ; Abhimanyu Saini
>
> Subject: Re: [PATCH 2/2][v4] armv8: ls2080aqds: Add support for SD boot
>
> On 04/12/2017 11:18 PM
On 14.4.2017 03:55, Masahiro Yamada wrote:
> These drivers have no user since commit ea3310e8aafa ("Blackfin:
> Remove").
>
> Signed-off-by: Masahiro Yamada
> ---
>
> drivers/block/Makefile |1 -
> drivers/block/pata_bfin.c| 1209
> --
> dr
I'm not sure, but I can't see any reference to
uclass_get_device_by_phandle in
https://github.com/u-boot/u-boot/blob/master/drivers/sysreset/sysreset-uclass.cSo
I guess that the driver is never probed unless
Hi Simon,
When trying to fix sysreset driver as you suggested I realized that I'm not
allocating any size for priv on bmips cpu driver.Should I use priv_auto_alloc
for this?(Still learning about u-boot dm...)
On 04/18/2017 03:22 PM, Michal Simek wrote:
> On 14.4.2017 03:55, Masahiro Yamada wrote:
>> These drivers have no user since commit ea3310e8aafa ("Blackfin:
>> Remove").
>>
>> Signed-off-by: Masahiro Yamada
>> ---
>>
>> drivers/block/Makefile |1 -
>> drivers/block/pata_bfin.c| 1209
Hi Simon
On 04/09/2017 09:27 PM, Simon Glass wrote:
> Hi Patrice,
>
> On 3 April 2017 at 03:39, Patrice CHOTARD wrote:
>> Hi Simon
>>
>> On 04/01/2017 06:21 AM, Simon Glass wrote:
>>> Hi Patrice,
>>>
>>> On 23 March 2017 at 03:59, Patrice CHOTARD wrote:
Hi Simon
On 03/22/2017 02:0
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