On Wed, Jun 07, 2017 at 11:47:24AM +0800, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
> >
> >
> > 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
> >>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> >>> As we have now a basical implementation of PSCI for
Hi,
On Wed, Jun 07, 2017 at 08:47:20AM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
> contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
> A83T has two clusters of Cortex-A7.
>
> This patch adds a basic
On Wed, Jun 07, 2017 at 08:47:18AM +0800, Icenowy Zheng wrote:
> diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
> b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i.h
> new file mode 100644
> index 00..af1a1d56c9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun4i
Hi Pawel:
2017-06-07 2:50 GMT+08:00 Paweł Jarosz :
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/mach-rockchip/Kconfig| 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173
> +++
Move the only use of CONFIG_SF_DUAL_FLASH to defconfig. This makes the
associated topic_miamiplus.h header obsolete, so remove that as well.
Signed-off-by: Mike Looijmans
---
README| 6 --
configs/topic_miamiplus_defconfig | 3 ++-
drivers/mtd/spi/Kconfig
These two patches add support for the topic-miamilite board.
v2: Rebased, no change
v3: Added missing Kconfig
v2: Moved CONFIG_SF_DUAL_FLASH to defconfig
v3: No change, resend as series
___
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U-Boot@lists.denx.de
https://lists.denx.d
The topic-miamilite SoM contains a Zynq xc7z010 SoC, 1GB DDR3L RAM,
64MB dual-parallel QSPI NOR flash and clock sources.
Signed-off-by: Mike Looijmans
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-topic-miamilite.dts | 17 ++
.../topic/zynq/zynq-
From: Tien Fong Chee
This patch is for enabling FPGA driver support on SPL
Signed-off-by: Tien Fong Chee
---
configs/socfpga_arria5_defconfig | 1 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_de0_nano_soc_defconfig | 1 +
configs/socfpga_de10_nano_defconfig| 1 +
c
From: Tien Fong Chee
Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and
booting from there.
FPGA driver build on SPL must be enabled 1st before applying patch 8 to
avoid build failed, because fpga_manager whic
From: Tien Fong Chee
Move FPGA manager driver which is Gen5 specific code from arch/arm/
into FPGA driver at driver/fpga/. No functional change.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/Makefile | 1 -
arch/arm/mach-socfpga/fpga_manager.c | 78
From: Tien Fong Chee
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
.../include/mach/fpga_manager_arria10.h| 100 +
configs/socfpga_arria10_defconfig | 2 +
drivers/fpga/Make
From: Tien Fong Chee
This converts the following to Kconfig:
CONFIG_FPGA_SOCFPGA
Signed-off-by: Tien Fong Chee
---
configs/astro_mcf5373l_defconfig | 1 +
configs/socfpga_arria5_defconfig | 1 +
configs/socfpga_cyclone5_defconfig | 1 +
configs/socfpga_de0_nano_soc_defconfig
From: Tien Fong Chee
This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA
Signed-off-by: Tien Fong Chee
---
configs/theadorable_debug_defconfig | 1 +
configs/theadorable_defconfig | 1 +
include/configs/astro_mcf5373l.h| 2 --
include/configs/theadorable.h
From: Tien Fong Chee
Move FPGA driver which is Gen5 specific code into Gen5 driver file
and keeping common FPGA driver intact. All the changes are still keeping
in driver/fpga/ and no functional change. Subsequent patch would move
FPGA manager driver from arch/arm into driver/fpga/.
Signed-off-b
From: Tien Fong Chee
Remove parameter from socfpga_bridges_reset(), and keeping this function
for single purpose which is just triggering reset on bridges.
socfpga_reset_deassert_bridges_handoff() can be called for releasing reset
on any bridges based on the bridge setting defined in fdt.
Signed
From: Tien Fong Chee
This is the 9th version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Marek in [v8].
This series is working on top of u-boot-socfpga.git -
http://git.denx.de/u-boot-socfpga.git
[v8]: https://www.mail-archive.com/u
Hello,
I am trying to load standalone application.
It works fine with the hello_world example ( bin format).
Then I move to build and run another application (uc/os) in eclipse.
The problem is that the bin format is very large.
Is there a way to load other a standalone application in another forma
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
> contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
> A83T has two clusters of Cortex-A7.
>
> This patch adds a basic version that al
On 06/06/2017 02:57 PM, Christian Gmeiner wrote:
2017-06-06 14:51 GMT+02:00 Hannes Schmelzer
:
"U-Boot" schrieb am 06.06.2017 14:35:29:
Von: Christian Gmeiner
An: u-boot@lists.denx.de,
Kopie: joe.hershber...@ni.com, oe5...@oevsv.at
Datum: 06.06.2017 14:35
Betreff: [U-Boot] [PATCH] drivers/ne
Hello Marek,
Am 06.06.2017 um 14:04 schrieb Marek Behun:
From: Marek Behún
This I2C mux is found, for example, on the Turris Omnia board.
Signed-off-by: Marek Behun
Reviewed-by: Heiko Schocher
bye,
Heiko
diff --git a/drivers/i2c/muxes/pca954x.c b/drivers/i2c/muxes/pca954x.c
index 1a676
On 06/02/2017 06:30 PM, Keerthy wrote:
> Some boards like am437x-gp-evm require dcdc3 also to be configured
> as it feeds on to ddr. Hence add the capability as well.
>
> Signed-off-by: Keerthy
Applied to u-boot-mmc for pmic. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/power/pmic/pmic
On 06/02/2017 06:30 PM, Keerthy wrote:
> Add ddr voltage rail (dcdc3) configuration. Set the dcdc3
> DDR supply to 1.35V.
>
> Signed-off-by: Keerthy
Applied to u-boot-mmc for pmic. Thanks!
Best Regards,
Jaehoon Chung
> ---
> board/ti/am43xx/board.c | 7 +++
> include/power/tps65218.h | 1
On Wed, Jun 7, 2017 at 11:48 AM, Chen-Yu Tsai wrote:
> On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>> A83T SoC has two part of CPUCFG configurations -- one part is at
>> 0x0170, which contains most of the controls, and is like the one in
>> A80; the another part is at 0x01f01c00 (lik
Hi
On 06/02/2017 02:21 PM, Keerthy wrote:
> Add smps12 dual regulator for tps65917
>
> Signed-off-by: Keerthy
Applied to u-boot-mmc for pmic. Thanks!
Best Regards,
Jaehoon Chung
> ---
> drivers/power/regulator/palmas_regulator.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
The driver provides regulator set/get voltage
enable/disable functions for lp87565 family of PMICs.
Signed-off-by: Keerthy
---
Changes in v2:
* updated Kconfig description.
* Used -EINVAL instead of hardcoded -1.
* removed couple of unwanted braces.
* Changed volt2hex to volt2val and he
Add support to bind the regulators/child nodes with the pmic.
Signed-off-by: Keerthy
---
Changes in v2:
* Used dev_read_subnode function to fetch the regulators node.
drivers/power/pmic/Kconfig | 7
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/lp87565.c | 85
The series adds support for LP87565 family of PMICs.
Implements functions to configure regulators. Enable/Disable
Get/Set voltages of regulators.
Keerthy (2):
power: pmic: lp87565: Add the basic pmic support
power: regulator: lp87565: add regulator support
drivers/power/pmic/Kconfig
> "Simon" == Simon Glass writes:
:
Simon> Oh dear. I cannot find my board but will see if I can repeat
Simon> this on a beaver.
Thanks.
If there's any additional logging you'd like me to collect on the
Jetson, let me know.
Peter C
--
Dr Peter Chubb Tel: +61 2 9490 5852 http://t
Hi Simon,
On 05/28/2017 02:37 AM, Simon Glass wrote:
> Many devices support a child block device (e.g. MMC, USB). Add a
> convenient way to get this device given the parent device.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/block/blk-uclass.c | 26 ++
> include/bl
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> A83T SoC has two part of CPUCFG configurations -- one part is at
> 0x0170, which contains most of the controls, and is like the one in
> A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
> contains now only a few reg
On Wed, Jun 7, 2017 at 11:40 AM, Icenowy Zheng wrote:
>
>
> 于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>>> As we have now a basical implementation of PSCI for A83T, enable
>>> non-secure boot support and PSCI on A83T now.
>>>
>>> Sig
于 2017年6月7日 GMT+08:00 上午11:43:40, Chen-Yu Tsai 写到:
>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>> From: Chen-Yu Tsai
>>
>> The A80/A83T SoCs has a different CPUCFG register layout, likely due
>to
>> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
>> located at sing
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The A80/A83T SoCs has a different CPUCFG register layout, likely due to
> having 2 clusters. The A83T SoC has also a small extra CPUCFG part
> located at single cluster SoCs' CPUCFG address (in CPUs domain).
>
> Add a c
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> A83T come with two clusters of CPU, for each cluster 1 the new registers
> are in the reserved spaces after the original cluster 0.
>
> Make the registers to have an array with length 2 (2 clusters), and
> change the current code to reference
于 2017年6月7日 GMT+08:00 上午11:36:27, Chen-Yu Tsai 写到:
>On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
>> As we have now a basical implementation of PSCI for A83T, enable
>> non-secure boot support and PSCI on A83T now.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> arch/arm/mach-sunxi/Kconfi
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> As we have now a basical implementation of PSCI for A83T, enable
> non-secure boot support and PSCI on A83T now.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/mach-sunxi/Kconfig | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
On 2017/6/6 23:02, Marek Vasut wrote:
On 06/06/2017 12:33 PM, Meng Dongyang wrote:
In current code, after running the command of "usb start", the controller
will keep in otg mode and can't switch to host mode if not support
SNP/SRP capability. So add the property of "hnp-srp-disable" in the DT
Hi Marek,
On 06/05/2017 10:32 PM, Marek Vasut wrote:
> On 06/05/2017 03:11 PM, Jaehoon Chung wrote:
>> Hi,
>
> Hi,
>
>> On 2017년 06월 05일 20:57, Marek Vasut wrote:
>>> On 05/31/2017 07:07 AM, Nobuhiro Iwamatsu wrote:
Hi!
2017-05-31 11:06 GMT+09:00 Jaehoon Chung :
> On 05/31/201
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: "tpear...@raptorengineering.com"
Same thing with the author name.
>
> According to the user manuals released by Allwinner, the low 8-bit of
> the 0x24 register in "System Control" (marked SRAMC in U-Boot source as
> it controls some S
Simon,
On 06/01/2017 11:10 AM, Simon Glass wrote:
Hi Kever,
On 23 May 2017 at 20:35, Kever Yang wrote:
Hi Simon,
On 05/20/2017 10:29 AM, Simon Glass wrote:
Hi Kever,
On 16 May 2017 at 21:44, Kever Yang wrote:
In rk3328, some function pin may have more than one choice, and muxed
with m
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> A83T has some secure SRAM that can be used to place the PSCI code.
>
> Add the configuration of them.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
___
U-Boot mailing list
U-Boot@list
On Wed, Jun 7, 2017 at 8:47 AM, Icenowy Zheng wrote:
> From: "tpear...@raptorengineering.com"
You should fix his name here.
>
> This patch enables non-secure access to all system peripherals
> controlled by the STMA, and additionally sets the secure RAM
> range to 64k in line with other sunxi d
Simon,
On 06/07/2017 05:10 AM, Simon Glass wrote:
Hi Pawel,
On 6 June 2017 at 12:51, Paweł Jarosz wrote:
rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
internal dma support and max driver frequency.
Signed-off-by: Paweł Jarosz
---
drivers/mmc/rockchip_dw_mmc.c |
Hi Kever,
On 6 June 2017 at 20:41, Kever Yang wrote:
> Simon,
>
>
>
> On 06/07/2017 05:08 AM, Simon Glass wrote:
>>
>> Hi Kever,
>>
>> On 31 May 2017 at 04:50, Kever Yang wrote:
>>>
>>> I think the boot0 hook is suppose to add some data in the very beginning
>>> of the SPL image, am I right?
>>>
Simon, Pawel,
On 06/07/2017 05:10 AM, Simon Glass wrote:
On 6 June 2017 at 12:52, Paweł Jarosz wrote:
Commit message?
Signed-off-by: Paweł Jarosz
---
arch/arm/mach-rockchip/rk3066/Makefile | 1 +
arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111 +++
2
Hi Peter,
On 6 June 2017 at 17:36, wrote:
> Recent changes to U-Boot have broken u-boot-flasher.I now see,
> after
> ./tegra-uboot-flasher flash jetson-tk1
> on the serial port:
> >>> Selecting MMC device...
> tegra_mmc_send_cmd_bounced: MMC Timeout
> Interrupt status
Remove the CONFIG_DM_I2C_COMPAT config.
Signed-off-by: Jaehoon Chung
Reviewed-by: Simon Glass
---
Changelog on V2:
- Rebased on latest u-boot-samsung
- Added Simon's Reviewed tag
- Fix the typo (COMPAT_DM_I2C_COMPAT -> CONFIG_DM_I2C_COMPAT)
configs/odroid_defconfig | 2 +-
include/configs/odro
On Sel, 2017-06-06 at 11:50 +0200, Marek Vasut wrote:
> On 06/06/2017 11:46 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote:
> > >
> > > On 06/06/2017 11:36 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut
On Wednesday 07 June 2017 02:38 AM, Simon Glass wrote:
> Hi Keerthy,
>
> On 1 June 2017 at 23:19, Keerthy wrote:
>> The driver provides regulator set/get voltage
>> enable/disable functions for lp87565 family of PMICs.
>>
>> Signed-off-by: Keerthy
>> ---
>> drivers/power/regulator/Kconfig
Simon,
On 06/07/2017 05:08 AM, Simon Glass wrote:
Hi Kever,
On 31 May 2017 at 04:50, Kever Yang wrote:
I think the boot0 hook is suppose to add some data in the very beginning
of the SPL image, am I right?
Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for
On Wednesday 07 June 2017 02:38 AM, Simon Glass wrote:
> Hi,
>
> On 1 June 2017 at 23:19, Keerthy wrote:
>> Add support to bind the regulators/child nodes with the pmic.
>>
>> Signed-off-by: Keerthy
>> ---
>> drivers/power/pmic/Kconfig | 7
>> drivers/power/pmic/Makefile | 1 +
>> d
Hi Andre, Steve, Marek,
Could you help to check how to make it work with this patch on
sunxi, bcm and socfpga platform?
Thanks,
- Kever
On 05/31/2017 06:50 PM, Kever Yang wrote:
The boot0 hook suppose to add some data before the SPL data,
let's move it at very begining and before '_start'
Hi Tom,
2017-06-06 9:52 GMT+09:00 Tom Rini :
> Hey all,
>
> So it's release day and I've put up v2017.07-rc1. The merge window is
> now closed and I've updated git and the tarballs are also up now.
>
> As is often the case, my queue needs a bit of cleaning up still and as
> per the schedule, I p
The communication filter reads data in blocks and converts each block to
unicode (if necessary) one at a time. In the unlikely event that a unicode
character in the input spans a block this will not work. We get an error
like:
UnicodeDecodeError: 'utf8' codec can't decode bytes in position 1022-10
Unicode characters may appear in input patches so we should not warn about
them. Drop this warning.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/patchstream.py | 9 -
1 file changed, 9 deletions(-)
Applied to u-boot-dm, thanks!
__
Don't mess with the email address when outputting them. Just make sure
they are encoded with utf-8.
Signed-off-by: Simon Glass
---
Changes in v2:
- Expand the patch to cover all cases
- Drop RFC tag
- Rewrite commit message
tools/patman/gitutil.py | 2 ++
tools/patman/series.py | 10 +++-
From: Philipp Tomsich
This change encodes the CC list to UTF-8 to avoid failures on
maintainer-addresses that include non-ASCII characters (observed on
Debian 7.11 with Python 2.7.3).
Without this, I get the following failure:
Traceback (most recent call last):
File "tools/patman/patman",
There is no need for this function to return the same object that was
passed in. Drop the return value.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/patchstream.py | 1 -
tools/patman/patman.py | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
Applied to u-boo
This is not a good variable name in Python because 'str' is a type. It
shows up highlighted in some editors. Rename it.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/gitutil.py | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Applied to u-boot-dm, thanks!
On 13 May 2017 at 18:11, Tom Rini wrote:
> In os_dirent_get_typename() we are checking that type falls within the
> known values of the enum os_dirent_t. With clang-3.8 testing this value
> as being >= 0 results in a warning as it will always be true. This
> assumes of course that we are only gi
On 22 May 2017 at 11:48, Tom Rini wrote:
> In the case where a new build only decreases sizes and does not increase
> any size we still want to report what functions have been dropped when
> doing a bloat comparison.
>
> Cc: Simon Glass
> Signed-off-by: Tom Rini
> ---
> This is important when do
Add some unicode to the test patches to make sure that patman does the
right thing.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/test.py | 9 +
1 file changed, 9 insertions(+)
Applied to u-boot-dm, thanks!
___
U-Boot maili
This is not a good variable name in Python because 'list' is a type. It
shows up highlighted in some editors. Rename it.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/series.py | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
Applied to u-boot-dm,
Allow the add_maintainers parameter to be a list of maintainers, thus
allowing us to simulate calling the script in tests without actually
needing it to work.
Signed-off-by: Simon Glass
---
Changes in v2: None
tools/patman/series.py | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
The existing test (patman --test) only covers basic checkpatch output.
We have had some problems with unicode processing and could use test
coverage for the various tags patman supports.
Add a new functional test which runs most of the patman flow on a few
test commits and checks that the results
On 2017/6/6 19:11, Tom Rini wrote:
On Tue, Jun 06, 2017 at 09:07:51AM +, wenyou.y...@microchip.com wrote:
Hi Tom,
On Mon, Jun 05, 2017 at 09:32:28PM +0200, Stelian Pop wrote:
Hi everybody,
The problem here is that you need to remove the boards in question
as well. I see the baord mai
As we have now a basical implementation of PSCI for A83T, enable
non-secure boot support and PSCI on A83T now.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 7ced
From: Chen-Yu Tsai
Allwinner A80 and A83T SoCs have two clusters of CPU, each cluster
contains 4 cores. A80 is Cortex-A15 + Cortex-A7 configuration, while
A83T has two clusters of Cortex-A7.
This patch adds a basic version that allows bringing up the four cores
in the first cluster. The structur
A83T come with two clusters of CPU, for each cluster 1 the new registers
are in the reserved spaces after the original cluster 0.
Make the registers to have an array with length 2 (2 clusters), and
change the current code to reference only cluster 0 registers.
Signed-off-by: Icenowy Zheng
---
a
A83T SoC has two part of CPUCFG configurations -- one part is at
0x0170, which contains most of the controls, and is like the one in
A80; the another part is at 0x01f01c00 (like other post-sun6i SoCs), but
contains now only a few registers.
Call it SUNXI_R_CPUCFG_BASE, like what the BSP Linux
From: "tpear...@raptorengineering.com"
According to the user manuals released by Allwinner, the low 8-bit of
the 0x24 register in "System Control" (marked SRAMC in U-Boot source as
it controls some SRAMs' functionality since A10) is the silicon revision
of the chip.
This data is now important fo
From: Chen-Yu Tsai
The A80/A83T SoCs has a different CPUCFG register layout, likely due to
having 2 clusters. The A83T SoC has also a small extra CPUCFG part
located at single cluster SoCs' CPUCFG address (in CPUs domain).
Add a cpucfg header file for it, rename the original cpucfg.h to
cpucfg_s
From: "tpear...@raptorengineering.com"
This patch enables non-secure access to all system peripherals
controlled by the STMA, and additionally sets the secure RAM
range to 64k in line with other sunxi devices.
Signed-off-by: Timothy Pearson
Signed-off-by: Icenowy Zheng
---
arch/arm/cpu/armv7/
A83T has some secure SRAM that can be used to place the PSCI code.
Add the configuration of them.
Signed-off-by: Icenowy Zheng
---
include/configs/sun8i.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h
index 47f2813240..c6ba2a0c87 100644
--
This is an experimental support for the PSCI SMP bringup of the first
cluster of Allwinner A83T SoC.
It's based on some code by Timothy Pearson for A83T (already quite old)
and Chen-Yu Tsai (which are originally for A80).
In order to ensure the Linux kernel to work properly in SMP environment,
so
Hi,
On 6 June 2017 at 17:59, Dr. Philipp Tomsich
wrote:
> Simon,
>
>> On 06 Jun 2017, at 23:09, Simon Glass wrote:
>>
>> Hi Philipp,
>>
>> On 6 June 2017 at 07:42, Philipp Tomsich
>> wrote:
>>> The regs_otg field in uintptr_t of the platform data structure for
>>> dwc2-otg has thus far been an
Simon,
> On 06 Jun 2017, at 23:09, Simon Glass wrote:
>
> Hi Philipp,
>
> On 6 June 2017 at 07:42, Philipp Tomsich
> wrote:
>> The regs_otg field in uintptr_t of the platform data structure for
>> dwc2-otg has thus far been an unsigned int, but will eventually be
>> casted into a void*.
>>
>>
On 5 June 2017 at 16:50, Dr. Philipp Tomsich
wrote:
> I have this on my tree since you sent it out and my last round of
> patch-submissions was already done with this version of patman.
> There were a few UTF-8 characters involved and all worked as
> expected.
>
> So you can consider it
> Tested-b
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz wrote:
> update driver to support rk3066 serial
>
> Signed-off-by: Paweł Jarosz
> ---
> drivers/serial/serial_rockchip.c | 19 ++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
Similar comments here to the mmc driver.
Regards
On 6 June 2017 at 12:51, Paweł Jarosz wrote:
> mk808 is a tv stick with two usb ports, micro sd card slot, hdmi and
> nand onboard.
>
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3066a-mk808.dts | 172
>
Hi Pawel,
On 6 June 2017 at 12:51, Paweł Jarosz wrote:
> rk3066 and rk3288 mmc designware ip's are very similiar. They differ in
> internal dma support and max driver frequency.
>
> Signed-off-by: Paweł Jarosz
> ---
> drivers/mmc/rockchip_dw_mmc.c | 31 +--
> 1 file
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz wrote:
> Rockchip bootrom first reads 1KB data from nand at offset 0x10080C00 and
> executes it. Then waits for back to bootrom and loads another 32KB to sram
> which also executes. Sdram initialisation code needs to be in one of these two
> steps.
+Masahiro
On 6 June 2017 at 05:45, Kever Yang wrote:
>
> I notice that the dtb content in spl/u-boot-spl.bin and u-boot.bin not
>
> able to update after I modify the dts file and make again, I have to
>
> "make clean" first, and then the "make" can update the dtb content
>
> to output binary, whi
Hi Philipp,
On 6 June 2017 at 07:42, Philipp Tomsich
wrote:
> The regs_otg field in uintptr_t of the platform data structure for
> dwc2-otg has thus far been an unsigned int, but will eventually be
> casted into a void*.
>
> This raises the following error with GCC 6.3 and buildman:
> ../driver
Hi Pawel,
On 6 June 2017 at 12:53, Paweł Jarosz wrote:
> Add sdram initialisation code which will be ussed by tpl first boot stage.
> We need to implement sdram initialisation in tpl due to size issues on rk3066
> platform.
>
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/include/asm/arch-rockc
Hi Pawel,
On 6 June 2017 at 12:50, Paweł Jarosz wrote:
> Add core skeleton for rk3066
>
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/mach-rockchip/Kconfig| 16 +++
> arch/arm/mach-rockchip/Makefile | 4 +
> arch/arm/mach-rockchip/rk3066-board-spl.c | 173 +
Hi Matt,
On 8 May 2017 at 10:38, Simon Glass wrote:
> Hi Matt,
>
> On 1 May 2017 at 21:43, Matt Weber wrote:
>> Not all host systems want the default swig to be
>> used when building the tools. Allow for the
>> disabling of the wrapper to enable cross-compiling
>> of the tools on a host system
On 6 June 2017 at 03:48, Kever Yang wrote:
> According to rk3036 TRM, pll_con1[12] should be set to '1' for the pll
> interger mode, while the '0' means the frac mode.
Should that be 'integer' ?
>
> Signed-off-by: Kever Yang
> ---
>
> drivers/clk/rockchip/clk_rk3036.c | 2 +-
> 1 file changed,
+Bin
Hi Paul,
On 6 June 2017 at 08:53, Paul Knopf wrote:
> Does U-Boot support booting an Intel 64bit Linux kernel?
>
Yes, in various ways. See for example x86-fit-boot.txt (and README.x86).
> The bootloader itself doesn't need to be 64bit, but it needs (for me) to
> boot a 64bit kernel with
On 6 June 2017 at 12:49, Paweł Jarosz wrote:
> Add driver supporting pin multiplexing on rk3066 platform.
>
> Signed-off-by: Paweł Jarosz
> ---
> drivers/pinctrl/Kconfig | 9 +
> drivers/pinctrl/rockchip/Makefile | 1 +
> drivers/pinctrl/rockchip/pinctrl_rk3066.c |
On 6 June 2017 at 01:15, Philipp Tomsich
wrote:
> When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
> the following implicitly defined functions are raised due to a missing
> include directive:
>
> drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
> drivers/vide
On 6 June 2017 at 12:49, Paweł Jarosz wrote:
> Add support for system reset for rk3066 socs.
>
> Signed-off-by: Paweł Jarosz
> ---
> drivers/sysreset/Makefile | 1 +
> drivers/sysreset/sysreset_rk3066.c | 62
> ++
> 2 files changed, 63 insertions(+)
Hi,
On 6 June 2017 at 07:42, Philipp Tomsich
wrote:
> After rebasing to u-boot-rockchip/master@2b19b2f, buildman fails for
> rv1108 with:
> ../drivers/pinctrl/rockchip/pinctrl_rv1108.c: In function
> 'rv1108_pinctrl_get_periph_id':
> ../drivers/pinctrl/rockchip/pinctrl_rv1108.c:111:49: error
On 6 June 2017 at 12:52, Paweł Jarosz wrote:
Commit message?
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/mach-rockchip/rk3066/Makefile | 1 +
> arch/arm/mach-rockchip/rk3066/sdram_rk3066.c | 111
> +++
> 2 files changed, 112 insertions(+)
> create mode 1006
On 5 June 2017 at 23:31, Jagan Teki wrote:
> From: Jagan Teki
>
> Control reg write should be part of setbrg for better
> buadrate generation, so move cr1 and cr2 write to
> mxc_serial_setbrg
>
> Signed-off-by: Jagan Teki
> ---
> drivers/serial/serial_mxc.c | 8 +++-
> 1 file changed, 3 ins
Hi Pawel,
On 6 June 2017 at 12:48, Paweł Jarosz wrote:
> grf is needed by various drivers for rk3066 soc.
>
> Signed-off-by: Paweł Jarosz
> ---
> arch/arm/include/asm/arch-rockchip/grf_rk3066.h | 621
>
> 1 file changed, 621 insertions(+)
> create mode 100644 arch/arm
On 6 June 2017 at 01:15, Philipp Tomsich
wrote:
> With HDMI output for the RK3399 working, this update the RK3399-Q7
> (Puma) defconfig for the new functionality:
> 1. enables PMIC command (to check if the HDMI voltages are correct)
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> 2. e
On 6 June 2017 at 12:44, Philipp Tomsich
wrote:
> This adds the DDR3-1333 timing via its own DTS and wires it up. This
> is not the default timing for the RK3399-Q7 and should be selected
> explicitly via the config (CONFIG_DEFAULT_DEVICE_TREE).
>
> Signed-off-by: Philipp Tomsich
>
> ---
>
> Cha
On 6 June 2017 at 07:42, Philipp Tomsich
wrote:
> After rebasing to u-boot-rockchip/master@2b19b2f, buildman fails for
> rv1108 with:
> ../drivers/clk/rockchip/clk_rv1108.c: In function 'rv1108_clk_probe':
> ../drivers/clk/rockchip/clk_rv1108.c:191:22: warning: implicit declaration
> of funct
On 5 June 2017 at 23:31, Jagan Teki wrote:
> From: Jagan Teki
>
> - Remove space between #define to macro
> - Add tab between macro and value
>
> Signed-off-by: Jagan Teki
> ---
> drivers/serial/serial_mxc.c | 191
> ++--
> 1 file changed, 94 insertions(
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