This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear. Move it to defconfig.
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/Kconfig | 1 -
configs/uniphier_ld4_sld8_defconfig | 1 +
configs/uniphier_pro4_defconfig | 1 +
co
On 08/29/2017 01:30 AM, Alexander Graf wrote:
>
>
> On 28.08.17 18:54, Heinrich Schuchardt wrote:
>> Command 'bootefi hello' currently uses CONFIG_SYS_LOAD_ADDR
>> as loading address.
>>
>> qemu machines have by default 128 MiB RAM.
>> CONFIG_SYS_LOAD_ADDR for x86 is 0x2000 (512 MiB).
>> This
It was noticed a few times, that the reboot from Linux (reboot command)
is different from the reboot (reset command) under U-Boot. The U-Boot
version does seem to reset the board more deeply (PCI cards etc) than
the Linux reboot.
This is actually caused by missing full reset bit in the reset regis
On Mon, Aug 28, 2017 at 10:56:52PM -0400, Tom Rini wrote:
> Hey all,
>
> It's release day and v2017.09-rc3 is out. I think there's still a few
> outstanding important bugfixes that need to come in, and probably a few
> more Kconfig migrations as well.
The tag/changes not pushed to git yet?
>
>
Hi Andy,
On Tue, Aug 29, 2017 at 1:12 AM, Andy Shevchenko
wrote:
> Hi!
>
> I have a preliminary working ACPI tables for Intel Edison (to replace
> ugly SFI provided by firmware).
> What I would like to ask is how better from your point of view to proceed.
>
> I have apparently not all devices cov
Hi Heiko
2017-08-28 15:37 GMT+09:00 Heiko Schocher :
> Hello Masahiro,
>
> Am 25.08.2017 um 13:19 schrieb Masahiro Yamada:
>>
>> Hi all.
>>
>> It is more than one year since the last re-sync.
>> https://lists.denx.de/pipermail/u-boot/2016-May/256464.html
>>
>>
>> Any plan for re-sync?
>>
>>
>>
>>
On Tue, Aug 22, 2017 at 10:50:02AM -0500, Adam Ford wrote:
> Enable TI_COMMON_CMD_OPTIONS and remove similar options
> from the defconfig. Updated with savedefconfig.
>
> Signed-off-by: Adam Ford
Tested-by: Derald D. Woods
> ---
> board/logicpd/am3517evm/Kconfig | 2 ++
> configs/am3517_evm_
On Tue, Aug 22, 2017 at 10:50:01AM -0500, Adam Ford wrote:
> Much of the AM3517 functions are copies of the standard definitions
> used in ti_omap3_common.h. Moving to include a common file
> reduces the amount of duplicative code and clutter. A few
> AM3517 specific functions (like EMIF4) are ex
Signed-off-by: Masahiro Yamada
---
drivers/reset/reset-uniphier.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 8a037cf735dd..b6bde70d6f6e 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/driver
Import updates queued up for Linux 4.14-rc1.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-ld11-global.dts | 6 +-
arch/arm/dts/uniphier-ld11-ref.dts| 6 +++---
arch/arm/dts/uniphier-ld11.dtsi | 13 +
arch/arm/dts/uniphier-ld20-global.dts | 6 +-
arch
Hi York,
> + if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
> + ltssm == LTSSM_PCIE_DETECT_ACTIVE) {
When the pcie slot have no device, the pcie controller access this register
return LTSSM_PCIE_DETECT_QUIET or LTSSM_PCIE_DETECT_ACTIVE state, In order to
avoid unnecessary delay, return dire
Hey all,
It's release day and v2017.09-rc3 is out. I think there's still a few
outstanding important bugfixes that need to come in, and probably a few
more Kconfig migrations as well.
If anyone has critical fixes I've missed please speak up. I think I've
got an idea on what they are but never t
On Tue, Aug 22, 2017 at 08:15:10AM -0700, Bin Meng wrote:
> Capabilities register is RO and accessed at various places in the
> driver. Let's cache it in the controller driver's priv struct.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digi
On Tue, Aug 22, 2017 at 08:15:13AM -0700, Bin Meng wrote:
> The NVMe block read and write routines are almost the same except
> the command opcode. Let's consolidate them to avoid duplication.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Di
Support PXs3 SoC and its reference development board.
Signed-off-by: Masahiro Yamada
---
arch/arm/dts/uniphier-pxs3-ref.dts | 21 --
arch/arm/dts/uniphier-pxs3.dtsi| 127 -
2 files changed, 98 insertions(+), 50 deletions(-)
diff --git a/arch/arm/dts
LD20 has SD ctrl instead of MIO ctrl. LD11 has both of them.
Signed-off-by: Masahiro Yamada
---
drivers/reset/reset-uniphier.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index ebb2cae5eb33..8a037cf735
On Tue, Aug 22, 2017 at 08:15:07AM -0700, Bin Meng wrote:
> The codes currently try to read PCI vendor id of the NVMe block
> device by dm_pci_read_config16() with its parameter set as its
> root complex controller (ndev->pdev) instead of itself. This is
> seriously wrong. We can read the vendor i
On Tue, Aug 22, 2017 at 08:15:16AM -0700, Bin Meng wrote:
> At present the NVMe uclass driver uses a global variable nvme_info
> to store global information like namespace id, and NVMe controller
> driver's priv struct has a blk_dev_start that is used to calculate
> the namespace id based on the g
On Fri, Aug 25, 2017 at 02:27:37PM +0200, Hannes Schmelzer wrote:
> Before commit 26d6119 (fdt: Move fdt_fixup_ethernet to a common place)
> the fdt_fixup_ethernet(...) was called during do_bootvx_fdt(...).
>
> Afterwards the only (common) place for this fixup is during
> image_setup_libfdt(...)
On Tue, Aug 22, 2017 at 08:15:19AM -0700, Bin Meng wrote:
> This enables NVMe driver on sandbox for build testing.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot mailing
On Tue, Aug 22, 2017 at 08:15:15AM -0700, Bin Meng wrote:
> The codes in nvme_uclass_post_probe() can be replaced to call the
> blk_create_devicef() API directly.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
__
On Tue, Aug 22, 2017 at 08:15:12AM -0700, Bin Meng wrote:
> NVMe driver only uses two queues. The first one is allocated to do
> admin stuff, while the second one is for IO stuff. So far the driver
> uses magic number (0/1) to access them. Change to use macros.
>
> Signed-off-by: Bin Meng
Appli
On Tue, Aug 22, 2017 at 08:15:14AM -0700, Bin Meng wrote:
> So far cache operations are only applied on the submission queue and
> completion queue, but they are missing in other places like identify
> and block read/write routines.
>
> In order to correctly operate on the caches, the DMA buffer
On Tue, Aug 22, 2017 at 08:15:09AM -0700, Bin Meng wrote:
> So far this is not causing any issue due to NVMe and x86 are using
> the same endianness, but for correctness, it should be fixed.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digi
On Fri, Aug 25, 2017 at 12:06:29AM -0700, Wilson Lee wrote:
> The silent environment callback function does not update the silent
> flag during silent env set or unset. That is because of duplicated
> CONFIG keyword at preprocessor condition in silent environment
> callback function and cause sile
On Tue, Aug 22, 2017 at 08:15:18AM -0700, Bin Meng wrote:
> This adds invalidate_dcache_range() so that some drivers can build
> without error on sandbox.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
__
On Tue, Aug 22, 2017 at 08:15:11AM -0700, Bin Meng wrote:
> So far the driver unconditionally delays 10ms when en/disabling the
> controller and still return 0 if 10ms times out. In fact, spec defines
> a timeout value in the CAP register that is the worst case time that
> host software shall wait
On Tue, Aug 22, 2017 at 08:15:17AM -0700, Bin Meng wrote:
> Instead of having separate code in the 'nvme' command, adjust it to use
> the common function.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
__
On Tue, Aug 22, 2017 at 08:15:06AM -0700, Bin Meng wrote:
> These are leftover when the driver was ported from Linux and are not
> used by the U-Boot driver.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
On Tue, Aug 22, 2017 at 08:15:08AM -0700, Bin Meng wrote:
> ndev->queues is a pointer to pointer, but the allocation wrongly
> requests sizeof(struct nvme_queue). Fix it.
>
> Signed-off-by: Bin Meng
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
__
- Pass MTDPARTS kernel arguments to kernel
- Use Kconfig CONFIG_NAND instead of CONFIG_SYS_EXTRA_OPTIONS="NAND"
- Call 'usb_stop' on kernel start
- Update Falcon mode setup to match other OMAP3 boards
- Use "uEnv.txt" as boot script instead of "boot.scr"
---
board/ti/evm/evm.c | 20 ++
Hi Wilson,
On Fri, Aug 25, 2017 at 11:29 AM, Wilson Lee wrote:
> From: Keng Soon Cheah
>
> Some device the serial console's initialization cannot run early during
> the boot process. Hence, nulldev serial device is helpful on that
> situation.
>
> For example, if the serial module was implemente
On Mon, Aug 28, 2017 at 6:19 AM, Tom Rini wrote:
> On Wed, Aug 23, 2017 at 11:39:06AM +0530, Lokesh Vutla wrote:
>
>> Add support for selecting proper dtb for
>> am57xx BeagleBoard X15 revC u-boot from FIT
>>
>> Signed-off-by: Lokesh Vutla
>> Reviewed-by: Tom Rini
>> ---
>> arch/arm/dts/Makefil
On 28.08.17 18:54, Heinrich Schuchardt wrote:
Command 'bootefi hello' currently uses CONFIG_SYS_LOAD_ADDR
as loading address.
qemu machines have by default 128 MiB RAM.
CONFIG_SYS_LOAD_ADDR for x86 is 0x2000 (512 MiB).
This causes 'bootefi hello' to fail.
We should use the environment var
On 08/28/2017 11:33 PM, Łukasz Majewski wrote:
> On 08/28/2017 10:32 PM, Marek Vasut wrote:
>> On 08/28/2017 09:28 PM, Łukasz Majewski wrote:
>>> Dear Marek,
>>>
>>> Those patches are preferably for -next merge widow.
>>>
>>>
>>>
>>> The following changes since commit
>>> ae61b5353b48fa49c66376f273
Hi Simon / Tom,
It seems the SH4 build is failing with the current trunk. Or at least
my test build is failing and the change seems to have nothing to do
with the failure.
https://travis-ci.org/jhershbe/u-boot/jobs/269330102
Cheers,
-Joe
___
U-Boot mai
On 28/08/17 17:21, Chakra D wrote:
Hi,
> I'm trying to build ITB image for sunxi banana Pi M64 image in
> Buildroot. I'm facing issues with ITB format Uboot build.
>
> As per the readme file "board/sunxi/README.sunxi64", we need to build
> the bl31.bin image before uboot and pass the path of im
On Thu, 3 Aug 2017 09:53:24 +0300
Tomas Melin tomas.me...@vaisala.com wrote:
> From: Niko Mauno
>
> Before reading entire FIT image, add sanity check by testing image
> header against FDT_MAGIC. This should help avoid problems in situations
> where FIT is not yet available from storage device,
On Thu, 3 Aug 2017 12:47:00 -0400
Rob Clark robdcl...@gmail.com wrote:
> Not really qcom specific, but for now qcom/lk is the one firmware that
> is (afaiu) setting up the appropriate dt node for pre-configured
> display. Uses the generic simple-framebuffer DT bindings so this should
> be useful
On Thu, 3 Aug 2017 12:47:01 -0400
Rob Clark robdcl...@gmail.com wrote:
> The use-case is that the thing that loaded u-boot already put a splash
> image on screen. And we want to preserve that until grub boot menu
> takes over.
>
> Signed-off-by: Rob Clark
> ---
> drivers/video/Kconfig
On Sat, Aug 26, 2017 at 8:18 PM, Tom Rini wrote:
> In order to be able to reliably use fdt_totalsize, we must have
> included.
>
> Fixes: 767cb74a0028 ("cmd: spl: provide address and size of prepared FDT ...")
> Signed-off-by: Tom Rini
Reviewed-by: Joe Hershberger
Tested-by: Joe Hershberger
_
Hi Philippe,
On Thu, 3 Aug 2017 12:36:05 +0200
Philippe CORNU philippe.co...@st.com wrote:
> Version 1:
> - Initial commit
>
> The purpose of this set of patches is to add the STM32 LTDC display
> controller support.
> In preamble, a configuration switch is added for pwm-based backlights
> and a
On 08/28/2017 10:32 PM, Marek Vasut wrote:
On 08/28/2017 09:28 PM, Łukasz Majewski wrote:
Dear Marek,
Those patches are preferably for -next merge widow.
The following changes since commit
ae61b5353b48fa49c66376f273cc53cd3c06b656:
usb: dwc3: fix Kconfig dependency to accept host driver in
Hello Heinrich,
On Sun, 20 Aug 2017 10:32:03 +0200
Heinrich Schuchardt xypron.g...@gmx.de wrote:
...
> To clarify the responsibilities could you, please, update your entry in
> MAINTAINERS to include
>
> common/lcd*.c
> include/lcd*.h
I've sent a patch.
Thanks,
Anatolij
Hello Heinrich,
On Sun, 20 Aug 2017 10:32:03 +0200
Heinrich Schuchardt xypron.g...@gmx.de wrote:
...
> To clarify the responsibilities could you, please, update your entry in
> MAINTAINERS to include
>
> common/lcd*.c
> include/lcd*.h
I've send a patch.
Thanks,
Anatolij
LCD drivers are video related, so add them to video section.
Signed-off-by: Anatolij Gustschin
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f7e6abd..04acf2b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -449,6 +449,8 @@ M: Anatolij Gustsc
The following changes since commit 8b3cec7da18645eda7f7cd0b65ee9f2dac573409:
mtdparts: Fix uninitialized scalar usage (2017-08-26 16:59:24 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up to 6ea247d1376138026fcb4b9d869ed0956e
On 08/28/2017 09:28 PM, Łukasz Majewski wrote:
> Dear Marek,
>
> Those patches are preferably for -next merge widow.
>
>
>
> The following changes since commit
> ae61b5353b48fa49c66376f273cc53cd3c06b656:
>
> usb: dwc3: fix Kconfig dependency to accept host driver in
> drivers/usb/dwc3 (2017-
We do not use print_cpuinfo and clock command code in SPL,
disable it when building SPL image.
Signed-off-by: Anatolij Gustschin
---
arch/arm/mach-imx/cpu.c | 4 ++--
arch/arm/mach-imx/mx6/clock.c | 30 --
2 files changed, 18 insertions(+), 16 deletions(-)
dif
Dear Marek,
Those patches are preferably for -next merge widow.
The following changes since commit ae61b5353b48fa49c66376f273cc53cd3c06b656:
usb: dwc3: fix Kconfig dependency to accept host driver in
drivers/usb/dwc3 (2017-08-25 11:23:27 +0200)
are available in the git repository at:
Hi Anatolij,
bss section is cleared in crt0.S. board_init_r() is also
entered from crt0 code.
Reviewed-by: Lukasz Majewski
Signed-off-by: Anatolij Gustschin
Cc: Christian Gmeiner
Cc: Nikita Kiryanov
Cc: Jagan Teki
Cc: Tim Harvey
Cc: Marek Vasut
Cc: Lukasz Majewski
Cc: Fabio Estevam
bss section is cleared in crt0.S. board_init_r() is also
entered from crt0 code.
Signed-off-by: Anatolij Gustschin
Cc: Christian Gmeiner
Cc: Nikita Kiryanov
Cc: Jagan Teki
Cc: Tim Harvey
Cc: Marek Vasut
Cc: Lukasz Majewski
Cc: Fabio Estevam
---
board/bachmann/ot1200/ot1200_spl.c
Hi,
Request for review on comments below.
Regards,
Suneel
On Mon, Aug 14, 2017 at 8:06 PM, Suneel Garapati wrote:
> Hi Simon,
>
>
> On Sun, Aug 13, 2017 at 2:37 PM, Simon Glass wrote:
>> Hi Suneel,
>>
>> On 10 August 2017 at 23:53, Suneel Garapati wrote:
>>> usb tree and info commands may cau
On Mon, 28 Aug 2017, Chris Packham wrote:
Add a --bounce-file option which can be used to omit addresses that are
known to bounce. The option specifies a file which lists addresses (one
per line) that are stripped from the Cc list.
Reviewed-by: Philipp Tomsich
Absolutely love this (in fact
Hi Stefano,
On Mon, 28 Aug 2017 18:54:39 +0200
Stefano Babic sba...@denx.de wrote:
...
> > + /*
> > +* Check if IPU clock was enabled before. Won't access
> > +* IPU registers if clock is not enabled.
> > +*/
> > + reg = readl(&mxc_ccm->CCGR3);
> > + if ((reg & MXC_CCM_CCGR3_IPU1
Hi Fabio,
On Mon, 28 Aug 2017 13:22:19 -0300
Fabio Estevam feste...@gmail.com wrote:
...
> > + /*
> > +* Check if IPU clock was enabled before. Won't access
> > +* IPU registers if clock is not enabled.
> > +*/
> > + reg = readl(&mxc_ccm->CCGR3);
> > + if
On Mon, Aug 28, 2017 at 2:33 PM, Jagan Teki wrote:
> From: Jagan Teki
>
> Add CONFIG_MMC_SUNXI_SLOT_EXTRA=2 to use eMMC on
> BPI_M3 board.
>
> Cc: Chen-Yu Tsai
> Cc: Maxime Ripard
> Signed-off-by: Jagan Teki
> Tested-by: Jagan Teki
Since for eMMC fixes to test on A83T in Mainline, this patch
On Thu, Aug 24, 2017 at 12:20 PM, Jagan Teki wrote:
> On Thu, Aug 24, 2017 at 8:41 AM, Chen-Yu Tsai wrote:
>> On Wed, Aug 23, 2017 at 7:41 PM, Maxime Ripard
>> wrote:
>>> The driver-model rework changed, among other things, the way the private
>>> data were moved around. It now uses the private
On Sat, Aug 26, 2017 at 12:10 PM, Jagan Teki wrote:
> On Wed, Aug 23, 2017 at 3:33 PM, Maxime Ripard
> wrote:
>> Almost all of the newer Allwinner SoCs have a new operating mode for the
>> eMMC clocks that needs to be enabled in both the clock and the MMC
>> controller.
>>
>> Details about that m
On Wed, Aug 23, 2017 at 3:33 PM, Maxime Ripard
wrote:
> The eMMC controller for the A83T uses the new operating mode. Enable it.
>
> Signed-off-by: Maxime Ripard
> ---
Applied to u-boot-sunxi/master
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Mainta
+Xiaowei
On 08/28/2017 10:09 AM, Joakim Tjernlund wrote:
> On Mon, 2017-08-28 at 16:55 +, York Sun wrote:
>> On 08/28/2017 09:48 AM, Joakim Tjernlund wrote:
>>> FSL PCIe controller drivers before REV 3 has this test for link up:
>>> enabled = ltssm >= PCI_LTSSM_L0;
>>>
>>> We have a PCIe d
Hi!
I have a preliminary working ACPI tables for Intel Edison (to replace
ugly SFI provided by firmware).
What I would like to ask is how better from your point of view to proceed.
I have apparently not all devices covered in the tables, though I have
almost stable code which brings ACPI support
On Mon, 2017-08-28 at 16:55 +, York Sun wrote:
> On 08/28/2017 09:48 AM, Joakim Tjernlund wrote:
> > FSL PCIe controller drivers before REV 3 has this test for link up:
> >enabled = ltssm >= PCI_LTSSM_L0;
> >
> > We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) when non
>
From: Jagan Teki
Falcon mode, is updating DDR dt node configuration through
spl_fixup_fdt() so add appropriate DDR base and size through
dram_init_banksize.
Signed-off-by: Jagan Teki
---
arch/arm/mach-rockchip/rk3288-board-spl.c | 17 +
1 file changed, 17 insertions(+)
diff --
From: Jagan Teki
Since the size of SPL can't be exceeded 0x8000 bytes in RK3288,
it is not possible add new SPL features like Falcon mode or etc.
So add TPL stage so-that adding new features to SPL is possible.
- TPL: DRAM init, clocks
- SPL: MMC, falcon, etc
Booting from SD with TPL:
-
From: Jagan Teki
Add Falcon mode support in vyasa rk3288 board.
Signed-off-by: Jagan Teki
---
board/amarula/vyasa-rk3288/vyasa-rk3288.c | 13 +
include/configs/vyasa-rk3288.h| 17 +
2 files changed, 30 insertions(+)
diff --git a/board/amarula/vyasa-rk32
From: Jagan Teki
This series add falcon mode support on vyasa rk3288.
Jagan Teki (3):
rk3288: vyasa: Add TPL support
rk3288: vyasa: Add falcon mode support
rk3288: spl: Add dram_init_banksize
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3288-board-spl.c |
From: Jagan Teki
This patch adds support for Vyasa RK3288 initial board
from Amarula.
Boot from SDMMC:
---
U-Boot SPL 2017.09-rc1-00111-g3656991-dirty (Aug 10 2017 - 11:40:45)
Trying to boot from MMC1
U-Boot 2017.09-rc1-00111-g3656991-dirty (Aug 10 2017 - 11:40:45 +0530)
Model: Ama
From: Jagan Teki
This patch adds support for Vyasa RK3288 initial board
from Amarula.
Boot from SDMMC:
---
U-Boot SPL 2017.09-rc1-00111-g3656991-dirty (Aug 10 2017 - 11:40:45)
Trying to boot from MMC1
U-Boot 2017.09-rc1-00111-g3656991-dirty (Aug 10 2017 - 11:40:45 +0530)
Model: Ama
On 08/28/2017 09:48 AM, Joakim Tjernlund wrote:
> FSL PCIe controller drivers before REV 3 has this test for link up:
>enabled = ltssm >= PCI_LTSSM_L0;
>
> We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) when non
> ready
> for PCI transaktions. When FSL PCIe controller tries
Command 'bootefi hello' currently uses CONFIG_SYS_LOAD_ADDR
as loading address.
qemu machines have by default 128 MiB RAM.
CONFIG_SYS_LOAD_ADDR for x86 is 0x2000 (512 MiB).
This causes 'bootefi hello' to fail.
We should use the environment variable loadaddr if available.
It defaults to 0x1000
Hi Anatolji,
On 25/08/2017 15:10, Anatolij Gustschin wrote:
> Boards can skip display interface init using board_video_skip().
> If display interface was not initialized (e.g. no ipuv3 framebuffer
> registered or IPU clock disabled), booting Linux stops due to the
> crash in IPU shutdown function,
FSL PCIe controller drivers before REV 3 has this test for link up:
enabled = ltssm >= PCI_LTSSM_L0;
We have a PCIe dev. that stays in LTSSM=0x51 (Polling Compliance) when non ready
for PCI transaktions. When FSL PCIe controller tries to access this device, it
hangs forever.
Is LTSSM=0x51 real
On 08/26/2017 04:50 AM, Jagan Teki wrote:
> On Thu, Aug 3, 2017 at 1:02 AM, Tom Rini wrote:
>> On Wed, Aug 02, 2017 at 07:10:51PM +, York Sun wrote:
>>> On 04/18/2017 04:57 AM, B, Ravi wrote:
In single stage bootmode or falcon boot mode,
the SPL shall update the memory dt nodes
On 8/27/2017 3:04 PM, Eric Nelson wrote:
> This adds support for USB boot mode on the i.MX7D SoC, which
> is most useful when doing U-Boot development on this chip.
>
> i.e., it enables you to enter the ROM boot loader's serial
> download protocol using the command:
>
> => bmode usb
>
> Signed-o
On 08/27/2017 11:30 PM, Peng Fan wrote:
> Add pfuze dm code, this code does the same thing as pfuze.c, but
> only effects when CONFIG_$(SPL_)DM_PMIC_PFUZE100 enabled.
>
> Signed-off-by: Peng Fan
> Cc: York Sun
> Cc: Jaehoon Chung
> Cc: Stefano Babic
> ---
>
> V2: none
>
> board/freescale/c
Hi Anatolij,
On Fri, Aug 25, 2017 at 10:10 AM, Anatolij Gustschin wrote:
> void ipuv3_fb_shutdown(void)
> {
> - int i;
> + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> struct ipu_stat *stat = (struct ipu_stat *)IPU_STAT;
> + u32 reg;
> +
Hi all,
I'm trying to build ITB image for sunxi banana Pi M64 image in Buildroot.
I'm facing issues with ITB format Uboot build.
As per the readme file "board/sunxi/README.sunxi64", we need to build the
bl31.bin image before uboot and pass the path of image as BL31 variable to
UBOOT.
Is there an
On Fri, Aug 25, 2017 at 2:06 AM, Wilson Lee wrote:
> The silent environment callback function does not update the silent
> flag during silent env set or unset. That is because of duplicated
> CONFIG keyword at preprocessor condition in silent environment
> callback function and cause silent env ca
On Mon, Aug 28, 2017 at 6:13 AM, Tom Rini wrote:
> On Mon, Aug 28, 2017 at 12:01:51PM +0100, Måns Rullgård wrote:
>> Simon Glass writes:
>>
>> > This was broken by the recent environment refactoring. Specifically:
>> >
>> > $ make environ
>> > scripts/Makefile.build:59: tools/environ/Makefile: N
On 28/08/2017 17:46, Anatolij Gustschin wrote:
> There is no need to clear the control register 100 times in a
> loop, a single zero write clears the register. I didn't find any
> justification why clearing this register in a loop is needed
> (no info in i.MX6 errata or GPT timer linux driver, linu
On 28/08/2017 17:46, Anatolij Gustschin wrote:
> The GPT timer was already initialised in board_init_f() as
> it is needed in dram init. Do not repeat timer init in
> board_init_r().
>
> Signed-off-by: Anatolij Gustschin
> ---
> common/spl/spl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deleti
Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.
Signed-off-by: Masahiro Yamada
---
drivers/clk/uniphier/Makefile| 1 +
drivers/clk/uniphier/clk-uniphier-core.c | 30
drivers/clk/uniphier/clk-uniphier-sys.c | 34 +
On 28/08/2017 17:51, Anatolij Gustschin wrote:
> The soc_boot_modes array is only used by bmode command
> and not needed in SPL. Don't include it into SPL.
>
> Signed-off-by: Anatolij Gustschin
> ---
> arch/arm/mach-imx/mx6/soc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/a
On Sun, Aug 27, 2017 at 4:44 AM, Chris Packham wrote:
> This is not a valid option. Drop it.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Simon Glass
Reviewed-by: Joe Hershberger
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On Sun, Aug 27, 2017 at 4:44 AM, Chris Packham wrote:
> This is not a valid option. Drop it.
>
> Signed-off-by: Chris Packham
> Reviewed-by: Simon Glass
Reviewed-by: Joe Hershberger
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On Tue, Aug 22, 2017 at 10:25 PM, Wilson Lee wrote:
> Although Xilinx Zynq SoC was using MACB similar hardware. However,
> U-boot MACB driver was not supporting Xilinx Zynq SoC. This patch is
> to add support for the Xilinx Zynq SoC to the existing MACB network
> driver.
>
> This patch is to add Z
regex code is not used in SPL when environment support is disabled,
so do not include this code to reduce SPL size.
Signed-off-by: Anatolij Gustschin
---
lib/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/Makefile b/lib/Makefile
index 1ffa455..b0850a1 100644
--- a/lib/Makefi
We do not need hashtable code in SPL when building
without environment support. Also display options
code is not used in current SPL configuration and
can be disabled.
Signed-off-by: Anatolij Gustschin
---
lib/Makefile | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/lib
The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.
Signed-off-by: Anatolij Gustschin
---
arch/arm/mach-imx/mx6/soc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index 9ede1f5
The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().
Signed-off-by: Anatolij Gustschin
---
common/spl/spl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d
There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control regist
From: Dai Okamura
Signed-off-by: Dai Okamura
Signed-off-by: Masahiro Yamada
---
arch/arm/mach-uniphier/clk/pll-base-ld20.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 6
Hi Simon,
On Sat, 2017-08-26 at 07:37 -0600, Simon Glass wrote:
> On 11 August 2017 at 02:52, Pantelis Antoniou
> wrote:
> > Add unit tests for sandbox default config.
> >
> > Signed-off-by: Pantelis Antoniou
> > ---
> > configs/sandbox_defconfig | 2 ++
> > 1 file changed, 2 insertions(+)
>
>
On Sun, Aug 27, 2017 at 5:39 PM, Adam Ford wrote:
> What starting up the DA850-EVM, U-Boot generates a warning:
>WARNING: Caches not enabled
>
> Looking at other arm926 processors, this is an attempt
> to enable the caches and remove the warning.
>
> I am notsure who the proper TI or ARM peopl
Hello,
As you've noticed, I'm porting U-Boot to a SH4 board running
big-endian. The big-endian choice cannot be changed, because it's
selected by the HW design: moving to little endian would require a
modification of the board.
The serial_sh driver was working fine in big endian, with no change.
In the SH7785/SH7786 case, the SCSCR value is harcoded to be 0x3a,
which means bits CKE1/CKE0 have the value 10b. This tells the SCIF
that the "External clock/SCIF_SCK pin functions as clock input".
However, this is not the case in all designs, and it's the purpose of
the clk_mode = EXT_CLK to ind
The board_mmc_init() is no longer invoked when DM is used, so move
all the pinmux config into board_init() instead.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
board/renesas/salvator-x/salvator-x.c | 9 ++---
board/renesas/ulcb/ulcb.c | 9 ++---
2 files changed, 4 i
The IPSR18 register bits were missing from the R8A7795 ES2.0+ PFC
tables, which triggered a BUG() in sh_pfc driver. This is because
of an out-of-bounds access to the pinmux_gpios[] array in the PFC
tables, which was too short due to the missing IPSR18 bits.
Signed-off-by: Marek Vasut
Cc: Nobuhiro
The configuration option name is the later, so replace usage of
CONFIG_RAVB in board files with CONFIG_RENESAS_RAVB , otherwise
the RAVB pinmux is not set and ethernet does not work.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
board/renesas/salvator-x/salvator-x.c | 2 +-
board/renesas
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