Add DFU support for BTicino Mamoj board and update
the same steps in README.
Signed-off-by: Jagan Teki
Signed-off-by: Simone CIANNI
Signed-off-by: Raffaele RECALCATI
---
board/bticino/mamoj/README | 37
Enable fastboot and ums for host to interact eMMC on
Mamoj board.
Signed-off-by: Jagan Teki
Signed-off-by: Simone CIANNI
Signed-off-by: Raffaele RECALCATI
---
configs/imx6dl_mamoj_defconfig | 6 ++
1 file
Add Falcon mode support to boot Linux directly after SPL.
Signed-off-by: Jagan Teki
---
board/bticino/mamoj/README | 27 +++
board/bticino/mamoj/spl.c | 11 +++
configs/imx6dl_mamoj_defconfig | 1 +
MX6DL Mamoj boards has Freescale PFUZE100 PMIC, add support
for it through DM_PMIC dt definition.
pmic log:
Reviewed-by: Stefano Babic
=> pmic list
| Name| Parent name | Parent uclass @ seq
| pfuze100@08 |
Enable Secure boot(HAB) for BTicino Mamoj board.
Signed-off-by: Jagan Teki
---
configs/imx6dl_mamoj_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index d789496dff..0001457f5d 100644
---
i.MX6DL Mamoj has i2c3 and i2c4 buses, add support
through DM_I2C with dt definition.
i2c log:
Reviewed-by: Stefano Babic
===
=> i2c bus
Bus 2: i2c@021a8000
Bus 3: i2c@021f8000
=> i2c dev 2
Setting bus to 2
=> i2c speed 40
Setting bus speed to 40 Hz
=> i2c probe
Add initial support for i.MX6DL BTicino Mamoj board.
Mamoh board added:
- SPL
- SPL_DM
- SPL_OF_CONTROL
- DM for U-Boot proper
- OF_CONTROL for U-Boot proper
- eMMC
- FEC
- Boot from eMMC
- Boot from USB SDP
Signed-off-by: Simone CIANNI
Signed-off-by: Raffaele
This series add support for BTicino i.MX6DL Mamoj board.
Changes for v3:
- Use imx spl inbuilt functions for ddr config instead of register
writes.
- rebase to master
Changes for v2:
- Update Kconfig changes for CONFIG_FSL_ESDHC
- Add HAB support
Jagan Teki (7):
i.MX6: board: Add BTicino
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support
Signed-off-by: Vinitha V Pillai
This patch depends on the following patches:
https://patchwork.ozlabs.org/patch/908676/
https://patchwork.ozlabs.org/patch/908089/
Since, ppa firmware address is moved to board specific Kconfig, moving
their respective headers also to the same Kconfig files.
Signed-off-by: Vinitha V Pillai
This patch depends on the following patches:
https://patchwork.ozlabs.org/patch/908676/
2018-05-07 9:35 GMT+09:00 Marek Vasut :
> On 04/26/2018 01:26 PM, Tom Rini wrote:
>> Hey all,
>>
>> This was already brought up by Heinrich Schuchardt, but didn't get much
>> traction. So, I'm bringing it up again now. The little feedback from
>> that thread was we should
According to the emmc/sdcard index in dts alias, emmc is 0 and
sdcard is 1, let's update to using correct mmc number for distro
boot order in common header.
series-version: 2
series-changes: 2
- update the commit message
Signed-off-by: Kever Yang
---
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Wednesday, April 25, 2018 9:04 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: u-boot@lists.denx.de; Greentime Ying-Han Hu(胡英漢);
> rickche...@gmail.com
> Subject: Re: NDS32 toolchain?
>
> On Wed, Apr 25, 2018 at 03:27:11AM
Hi Klaus,
On 05/04/2018 05:19 PM, klaus.go...@theobroma-systems.com wrote:
> Hi Kever
>
>> On 04.05.2018, at 10:50, Kever Yang wrote:
>>
>> We define emmc/sdcard index in dts alias, emmc is 0 and sdcard is 1.
> The commit message is a bit misleading at first. When
On Mon, May 07, 2018 at 10:20:55AM +0800, Kever Yang wrote:
> Hi Marty,
>
>
> On 05/06/2018 10:25 PM, Marty E. Plummer wrote:
> > Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
> >
> > Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> > is incorrectly detected as
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, April 23, 2018 2:00 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Greentime Hu; Philipp Tomsich; Heinrich
> Schuchardt; sch...@suse.de
> Subject: [PATCH v3 7/8] riscv: nx25: Enable distro
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, April 23, 2018 2:00 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Greentime Hu; Philipp Tomsich; Heinrich
> Schuchardt; sch...@suse.de
> Subject: [PATCH v3 4/8] riscv: Add
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, April 23, 2018 2:00 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Greentime Hu; Philipp Tomsich; Heinrich
> Schuchardt; sch...@suse.de
> Subject: [PATCH v3 1/8] riscv: Add setjmp/longjmp
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, April 23, 2018 2:00 PM
> To: u-boot@lists.denx.de
> Cc: Rick Jian-Zhi Chen(陳建志); Greentime Hu; Philipp Tomsich; Heinrich
> Schuchardt; sch...@suse.de
> Subject: [PATCH v3 2/8] riscv: Enable function
Hi Marty,
On 05/06/2018 10:25 PM, Marty E. Plummer wrote:
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
I know the root cause for this issue, and I have a local
> -Original Message-
> From: Tom Rini [mailto:tr...@konsulko.com]
> Sent: Monday, May 07, 2018 5:12 AM
> To: Alexander Graf; Rick Jian-Zhi Chen(陳建志); Greentime Hu
> Cc: u-boot@lists.denx.de; Heinrich Schuchardt; sch...@suse.de
> Subject: Re: [U-Boot] [PATCH v3 0/8] riscv: Enable
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Monday, May 07, 2018 4:59 AM
> To: u-boot@lists.denx.de
> Cc: Heinrich Schuchardt; sch...@suse.de; Greentime Hu; Rick Jian-Zhi Chen(陳
> 建志)
> Subject: Re: [U-Boot] [PATCH v3 0/8] riscv: Enable efi_loader support
>
On Fri, May 4, 2018 at 10:30 PM, Nguyen, Dinh wrote:
>
>
>> -Original Message-
>> From: Tan, Ley Foon
>> Sent: Friday, May 4, 2018 5:49 AM
>> To: u-boot@lists.denx.de
>> Cc: Marek Vasut ; Ley Foon Tan ;
>> See, Chin Liang
On Sun, May 6, 2018 at 10:45 PM, Tom Rini wrote:
> The only place they'll now be allowed, just like with the Linux Kernel,
> is for the first line SDPX tag in some file formats. Bringing us in
> line with how the kernel goes is overall a good thing I believe.
Correct: it is
On Mon, May 07, 2018 at 02:35:16AM +0200, Marek Vasut wrote:
> On 04/26/2018 01:26 PM, Tom Rini wrote:
> > Hey all,
> >
> > This was already brought up by Heinrich Schuchardt, but didn't get much
> > traction. So, I'm bringing it up again now. The little feedback from
> > that thread was we
On 04/26/2018 01:26 PM, Tom Rini wrote:
> Hey all,
>
> This was already brought up by Heinrich Schuchardt, but didn't get much
> traction. So, I'm bringing it up again now. The little feedback from
> that thread was we should move to Linux Kernel style tags. I'm going to
> propose that we do
On Sun, May 06, 2018 at 09:25:10AM -0500, Marty E. Plummer wrote:
> Build and boot tested on my chromebook, which was generously altered by
> Simon Glass to have a servo header and also generously provided a servo
> board itself to do debugging with.
>
> It ''works'', but has a few oddities. I
On Mon, May 07, 2018 at 12:19:11AM +0200, Dr. Philipp Tomsich wrote:
>
> > On 6 May 2018, at 16:25, Marty E. Plummer wrote:
> >
> > Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
> >
> > Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> >
On Mon, May 07, 2018 at 12:12:54AM +0200, klaus.go...@theobroma-systems.com
wrote:
>
> > On 06.05.2018, at 16:25, Marty E. Plummer wrote:
> >
> > This adds support for the ASUS C201, a RK3288-based clamshell
> > device. The device tree comes from linus's linux tree at
>
> On 6 May 2018, at 16:25, Marty E. Plummer wrote:
>
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this change, my u-boot build for the asus c201 chromebook (4GiB)
> is incorrectly detected as 0 Bytes of ram.
Could you elaborate what the change is
> On 06.05.2018, at 16:25, Marty E. Plummer wrote:
>
> This adds support for the ASUS C201, a RK3288-based clamshell
> device. The device tree comes from linus's linux tree at
> 87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
> are for 4GB Samsung LPDDR3,
On Thu, May 03, 2018 at 09:12:25AM -0400, Tom Rini wrote:
> With tighter build flags the fact that this header referenced
> uchar/ushort without including what typedefs it causes an error. Rather
> than add another include here, drop the section in question as it is
> unused.
>
> Reported-by:
On Thu, May 03, 2018 at 09:12:26AM -0400, Tom Rini wrote:
> With tighter build flags the fact that doesn't have a
> reference back to MAX_NAMES causes an error. Include here and
> then in common/console.c use MAX_NAMES rather than 3 when working with
> stdio_names.
>
> Reported-by: Peter
On Thu, May 03, 2018 at 08:34:49PM +0530, Lokesh Vutla wrote:
> omap-common cache enabling sequence relies on cpu_init_cp15()
> (inside start.S) for enabling I-caches. But cpu_init_cp15()
> can be skipped if CONFIG_SKIP_LOWLEVEL_INIT is defined. So
> enable I-caches if not enabled already.
>
>
On Wed, May 02, 2018 at 06:07:18PM +0800, Kelvin Cheung wrote:
> Building with verified boot support requires hash, add that
> dependency here. Otherwise the following build error will come out
> without crc command.
>
> LD u-boot
> lib/built-in.o: In function `hash_calculate':
>
On Wed, May 02, 2018 at 03:06:31PM +0530, Keerthy wrote:
> A common voltage of 1.35V was being programmed for all am43 board
> versions. EPOS-EVM Needs 1.20V for LPDDR2.
>
> Fixes: fc69d472621b5 (“board: ti: AM43XX: Add ddr voltage rail configuration”)
> Reported-by: James Doublesin
On Mon, Apr 30, 2018 at 07:13:05PM -0400, Trevor Woerner wrote:
> Signed-off-by: Trevor Woerner
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Apr 05, 2018 at 09:39:20AM +0200, Alexander Graf wrote:
> On 04/04/2018 09:14 PM, Heinrich Schuchardt wrote:
> >On 04/04/2018 06:11 PM, Alexander Graf wrote:
> >>
> >>On 04.04.18 17:10, Heinrich Schuchardt wrote:
> >>>On 04/04/2018 02:32 PM, Alexander Graf wrote:
>
> On 03.04.18
On Mon, Apr 23, 2018 at 07:59:42AM +0200, Alexander Graf wrote:
> We now have RISC-V support in U-Boot - which is great!
>
> However, not that we're finally making progress to converge on
> efi_loader and distro boot for booting on ARM platforms, we
> really want to make sure there is no
On 23.04.18 07:59, Alexander Graf wrote:
> We now have RISC-V support in U-Boot - which is great!
>
> However, not that we're finally making progress to converge on
> efi_loader and distro boot for booting on ARM platforms, we
> really want to make sure there is no technical reason not to
> do
On Sun, May 06, 2018 at 10:21:55PM +0200, klaus.go...@theobroma-systems.com
wrote:
>
> > On 06.05.2018, at 22:03, Marty E. Plummer wrote:
> >
> > On Sun, May 06, 2018 at 02:08:25PM -0500, Marty E. Plummer wrote:
> >>> On Sun, May 06, 2018 at 08:39:23PM +0200,
> >>>
Hi Lukasz,
On Sun, May 6, 2018 at 5:26 PM, Lukasz Majewski wrote:
> diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
> index 1fb8225fbb..b187b6fac1 100644
> --- a/arch/sandbox/dts/sandbox.dts
> +++ b/arch/sandbox/dts/sandbox.dts
> @@ -115,6 +115,10 @@
>
On Sun, May 06, 2018 at 09:49:42PM +0200, Alexander Graf wrote:
> On 06.05.18 18:02, Heinrich Schuchardt wrote:
> > On 05/04/2018 11:18 AM, Marek Vasut wrote:
> >> On 05/04/2018 08:46 AM, Alexander Graf wrote:
> >>> On 05/04/2018 01:04 AM, Marek Vasut wrote:
> On 05/03/2018 11:57 PM,
The common code can be excluded to be reused by tests for other PMIC.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch
test/dm/pmic.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/test/dm/pmic.c b/test/dm/pmic.c
index
The struct dm_pmic_info's trans_len field stores the number of types to
be transmitted per PMIC transfer.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch
drivers/power/pmic/pmic-uclass.c | 10 ++
include/power/pmic.h | 4
2 files
Following tests has been added for mc34708 device:
- get_test for mc34708 PMIC
- Check if proper number of registers is read
- Check if default (emulated via i2c device) value is properly read
- Check if value write/read operation is correct
- Perform tests to check if pmic_clrsetbits() is
Up till now it was only possible to use 'pmic' command with a single byte
transmission.
The pmic_read|write functions has been replaced with ones, which don't need
the transmission length as a parameter.
Due to that it is possible now to read data from PMICs transmitting more
data than 1 byte at
This MC34708 PMIC is somewhat special - it used single transfers (R/W) with
3 bytes size - up till now u-boot's PMICs only used 1 byte.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch
configs/sandbox_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git
This change enables support for MC34708 PMIC in sandbox. Now we can
emulate the I2C transfers larger than 1 byte.
Notable changes for this driver:
- From now on the register number is not equal to index in the buffer,
which emulates the PMIC registers
- The PMIC register's pool is now
Adding this device required some changes into the PMIC uclass.
Most notable one was the support for 3 bytes r/w operations.
Moreover, emulation and tests for this device has been added to
sandbox.
Lukasz Majewski (11):
pmic: fsl: Provide some more definitions for MC34708 PMIC
pmic: fsl:
This commit provides support for transmissions larger than 1 byte for
PMIC devices used with DM (e.g. MC34708 from NXP).
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- pmic_reg_* fixes to use uclass private structure
drivers/power/pmic/pmic-uclass.c | 44
This patch adds support for MC34708 PMIC, to be used with driver model
(DM).
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- Support for uclass private data with trasfer length
drivers/power/pmic/Kconfig | 7 +++
drivers/power/pmic/Makefile | 1 +
This commit also provides the default values of the emulated MC34708 PMIC
internal registers content.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- New patch
arch/sandbox/dts/sandbox.dts | 4
arch/sandbox/dts/sandbox64.dts | 4
This commit adds some more defines for MC34708 PMIC.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- None
include/fsl_pmic.h | 40
1 file changed, 40 insertions(+)
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
index
This patch adds definition of the number of bytes sent at once by the
MC34708 PMIC.
Signed-off-by: Lukasz Majewski
---
Changes in v2:
- None
include/fsl_pmic.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/fsl_pmic.h b/include/fsl_pmic.h
index
> On 06.05.2018, at 22:03, Marty E. Plummer wrote:
>
> On Sun, May 06, 2018 at 02:08:25PM -0500, Marty E. Plummer wrote:
>>> On Sun, May 06, 2018 at 08:39:23PM +0200, klaus.go...@theobroma-systems.com
>>> wrote:
On 06.05.2018, at 16:25, Marty E. Plummer
On Sun, May 06, 2018 at 02:08:25PM -0500, Marty E. Plummer wrote:
> > On Sun, May 06, 2018 at 08:39:23PM +0200, klaus.go...@theobroma-systems.com
> > wrote:
> > > On 06.05.2018, at 16:25, Marty E. Plummer wrote:
> > > + * we use the 0x~0xfeff space
>
On 06.05.18 18:02, Heinrich Schuchardt wrote:
> On 05/04/2018 11:18 AM, Marek Vasut wrote:
>> On 05/04/2018 08:46 AM, Alexander Graf wrote:
>>> On 05/04/2018 01:04 AM, Marek Vasut wrote:
On 05/03/2018 11:57 PM, Alexander Graf wrote:
>
> On 01.05.18 04:09, Marek Vasut wrote:
>>
On 22.03.2018 19:39, Álvaro Fernández Rojas wrote:
> Convert bmips drivers to use live device tree instead of flattened device
> tree.
>
> v2: Introduce changes suggested by Daniel Schwierzeck and Simon Glass:
> - Add generic dev_remap_addr/dev_remap_addr_index functions.
> - Fix bcm63xx_spi
On 29.04.2018 21:56, Daniel Schwierzeck wrote:
> From: Álvaro Fernández Rojas
>
> Signed-off-by: Álvaro Fernández Rojas
> Reviewed-by: Daniel Schwierzeck
> Signed-off-by: Daniel Schwierzeck
>
On Sun, May 06, 2018 at 08:39:23PM +0200, klaus.go...@theobroma-systems.com
wrote:
> CC Philipp and Simon due maintainership (you may want to use
> get_maintainer.pl in the future)
> and Kever as the original author of the file.
>
> > On 06.05.2018, at 16:25, Marty E. Plummer
CC Philipp and Simon due maintainership (you may want to use get_maintainer.pl
in the future)
and Kever as the original author of the file.
> On 06.05.2018, at 16:25, Marty E. Plummer wrote:
>
> Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
>
> Without this
On 05/04/2018 11:18 AM, Marek Vasut wrote:
> On 05/04/2018 08:46 AM, Alexander Graf wrote:
>> On 05/04/2018 01:04 AM, Marek Vasut wrote:
>>> On 05/03/2018 11:57 PM, Alexander Graf wrote:
On 01.05.18 04:09, Marek Vasut wrote:
> On 04/30/2018 08:22 PM, Heinrich Schuchardt wrote:
>>
This adds support for the ASUS C201, a RK3288-based clamshell
device. The device tree comes from linus's linux tree at
87ef12027b9b1dd0e0b12cf311fbcb19f9d92539. The SDRAM parameters
are for 4GB Samsung LPDDR3, decoded from coreboot's
Taken from coreboot's src/soc/rockchip/rk3288/sdram.c
Without this change, my u-boot build for the asus c201 chromebook (4GiB)
is incorrectly detected as 0 Bytes of ram.
Signed-off-by: Marty E. Plummer
---
arch/arm/mach-rockchip/sdram_common.c | 62
Add entry for GigaDevice gd25q32b part.
Signed-off-by: Marty E. Plummer
---
drivers/mtd/spi/spi_flash_ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index ef55abb01d..de940645ed 100644
---
Build and boot tested on my chromebook, which was generously altered by
Simon Glass to have a servo header and also generously provided a servo
board itself to do debugging with.
It ''works'', but has a few oddities. I can't seem to get it to see my
external sdcard or a usb flash drive, so I've
Hello Igor, Alex, Kever,
Having these patches in mainline would be great, as this would reduce
the delta between our own and community U-boot trees. After having a
quick look at this series, I have some questions/review findings.
These patches appear to be slightly older than what is available
Add support for loading U-Boot on the Broadcom 7445D0 SoC. This port
assumes Broadcom's BOLT bootloader is acting as the second stage
bootloader, and U-Boot is acting as the third stage bootloader, loaded
as an ELF program by BOLT.
Signed-off-by: Thomas Fitzsimmons
Cc:
Hello all,
Take my apologies for the late activity and also for the mailer I am using,
which may disturb the following reading.
> Le 6 mai 2018 à 02:13, Tom Rini a écrit :
>
> On Sat, May 05, 2018 at 04:04:08PM -0700, Vagrant Cascadian wrote:
>
>> Hello U-Boot.
>>
>>
Hi,
This patch adds support for loading U-Boot on the Broadcom 7445D0 SoC,
as a third stage bootloader loaded by Broadcom's BOLT bootloader.
While this is only a partial port, it does enable some of U-Boot's
flexibility on this SoC, functionality beyond what BOLT provides.
Specifically, it
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