Re: [U-Boot] [PATCH v3 0/5] Add get_alt_function ops

On 10.9.2018 18:11, Patrice Chotard wrote: > > This series : > - Add new gpio ops get_alt_function > - Add get_function and get_alt_function support to stm32 gpio driver > - Add get_alt_function test I went quickly over this series and TBH I am not getting what this is for. It looks like

Re: [U-Boot] [PATCH 5/5] aspeed: Activate ethernet devices on the ast2500 Eval Board

On 09/11/2018 02:55 AM, Joel Stanley wrote: > On Mon, 10 Sep 2018 at 23:56, Cédric Le Goater wrote: >> diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts >> index 609678ff7989..1bd224dacf78 100644 >> --- a/arch/arm/dts/ast2500-evb.dts >> +++ b/arch/arm/dts/ast2500-evb.dts >

[U-Boot] [RESEND PATCH v2 11/15] riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/Makefile | 2 +- arch/riscv/cpu/Makefile | 2 ++ arch/riscv/cpu/ax25/Makefile | 2 -- arch/riscv/cpu/{ax25 =>

[U-Boot] [RESEND PATCH v2 15/15] riscv: Move do_reset() to a common place

We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer

[U-Boot] [RESEND PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL

RISC-V is a pretty new architecture and should support DM and OF_CONTROL by default. Signed-off-by: Bin Meng --- Changes in v2: None arch/Kconfig | 3 +++ configs/ax25-ae350_defconfig | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig

[U-Boot] [RESEND PATCH v2 14/15] riscv: Add QEMU virt board support

This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in

[U-Boot] [RESEND PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel

So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer Signed-off-by: Bin Meng --- Changes in v2: - new patch to pass mhartid CSR value to kernel arch/riscv/lib/bootm.c | 5 +++-- 1 file changed, 3 insertions(+),

[U-Boot] [RESEND PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts

There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/dts/ae350.dts | 177 --- 1 file changed, 90 insertions(+), 87 deletions(-) diff --git

[U-Boot] [RESEND PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h

There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng --- Changes in v2: - new patch to remove CSR read/write defines in encoding.h

[U-Boot] [RESEND PATCH v2 06/15] riscv: Fix coding style issues in the linker script

There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/cpu/u-boot.lds | 58 +++ 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/riscv/cpu/u-boot.lds

[U-Boot] [RESEND PATCH v2 08/15] riscv: Add a helper routine to print CPU information

This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c

[U-Boot] [RESEND PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler

At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain

[U-Boot] [RESEND PATCH v2 04/15] riscv: Remove mach type

Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/include/asm/mach-types.h | 29 - arch/riscv/include/asm/u-boot.h | 1 - board/AndesTech/ax25-ae350/ax25-ae350.c | 2 -- cmd/bdinfo.c

[U-Boot] [RESEND PATCH v2 05/15] riscv: Move the linker script to the CPU root directory

The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/cpu/{ax25 => }/u-boot.lds | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (100%) diff --git

[U-Boot] [RESEND PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id

The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is

[U-Boot] [RESEND PATCH v2 02/15] riscv: Remove setup.h

This was copied from ARM, and does not apply to RISC-V. While we are here, bootm.h is eventually removed as its content is only the inclusion of setup.h. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/setup.h | 194

[U-Boot] [RESEND PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling

It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng --- Changes in v2: None arch/Kconfig | 2 +- arch/riscv/Kconfig | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index bf1b4a9..42c23b5 100644 ---

[U-Boot] [RESEND PATCH v2 00/15] riscv: Add QEMU virt board support

This series adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. Some existing RISC-V codes have been changed to make it easily to support new targets. Some spotted coding style issues are fixed. This series is available at

[U-Boot] [PATCH v2 09/15] riscv: Remove CSR read/write defines in encoding.h

There is no reason to keep two versions of CSR read/write defines in encoding.h. We already have one set of defines in csr.h, which is from Linux kernel, and let's drop the one in encoding.h. Signed-off-by: Bin Meng --- Changes in v2: - new patch to remove CSR read/write defines in encoding.h

[U-Boot] [PATCH v2 12/15] riscv: ae350: Clean up mixed tabs and spaces in the dts

There are quite a lot of mixed tabs and spaces in the ae350.dts. Clean them up. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/dts/ae350.dts | 177 --- 1 file changed, 90 insertions(+), 87 deletions(-) diff --git

[U-Boot] [PATCH v2 08/15] riscv: Add a helper routine to print CPU information

This adds a helper routine to print CPU information. Currently it prints all the instruction set extensions that the processor core supports. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/Makefile | 1 + arch/riscv/cpu/Makefile | 5 ++ arch/riscv/cpu/cpu.c

[U-Boot] [PATCH v2 13/15] riscv: kconfig: Select DM and OF_CONTROL

RISC-V is a pretty new architecture and should support DM and OF_CONTROL by default. Signed-off-by: Bin Meng --- Changes in v2: None arch/Kconfig | 3 +++ configs/ax25-ae350_defconfig | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/Kconfig

[U-Boot] [PATCH v2 14/15] riscv: Add QEMU virt board support

This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in

[U-Boot] [PATCH v2 07/15] riscv: Explicitly pass -march and -mabi to the compiler

At present the compiler flag against which architecture and abi variant the riscv image is built for is not explicitly indicated which means the default compiler configuration is used. But this does not work if we want to build a different target (eg: 32-bit riscv images using a toolchain

[U-Boot] [PATCH v2 10/15] riscv: bootm: Pass mhartid CSR value to kernel

So far this is hardcoded to zero, and we should read the value from mhartid CSR and pass it to Linux kernel. Suggested-by: Lukas Auer Signed-off-by: Bin Meng --- Changes in v2: - new patch to pass mhartid CSR value to kernel arch/riscv/lib/bootm.c | 5 +++-- 1 file changed, 3 insertions(+),

[U-Boot] [PATCH v2 15/15] riscv: Move do_reset() to a common place

We don't have a reset method on any RISC-V board yet. Instead of adding the same 'unsupported' message for each CPU variant it might make more sense to add a generic do_reset function for all CPU variants to lib/, similar to the one for ARM (arch/arm/lib/reset.c). Suggested-by: Lukas Auer

[U-Boot] [PATCH v2 11/15] riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be common for all RISC-V targets. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/Makefile | 2 +- arch/riscv/cpu/Makefile | 2 ++ arch/riscv/cpu/ax25/Makefile | 2 -- arch/riscv/cpu/{ax25 =>

[U-Boot] [PATCH v2 06/15] riscv: Fix coding style issues in the linker script

There are several coding style issues in the linker script. Fix them. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/cpu/u-boot.lds | 58 +++ 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/arch/riscv/cpu/u-boot.lds

[U-Boot] [PATCH v2 05/15] riscv: Move the linker script to the CPU root directory

The linker script can be shared by all RISC-V targets. Move it to a common place. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/cpu/{ax25 => }/u-boot.lds | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename arch/riscv/cpu/{ax25 => }/u-boot.lds (100%) diff --git

[U-Boot] [PATCH v2 04/15] riscv: Remove mach type

Since the mach_id is not used by RISC-V, remove it. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/include/asm/mach-types.h | 29 - arch/riscv/include/asm/u-boot.h | 1 - board/AndesTech/ax25-ae350/ax25-ae350.c | 2 -- cmd/bdinfo.c

[U-Boot] [PATCH v2 03/15] riscv: bootm: Correct the 1st kernel argument to hart id

The first argument of Linux kernel is the risc-v core hart id, from which the kernel is booted from. It is not the mach_id, which seems to be copied from arm. While we are here, this also changes the Linux kernel entry parameters' type to support both 32-bit and 64-bit. Note the hart id is

[U-Boot] [PATCH v2 02/15] riscv: Remove setup.h

This was copied from ARM, and does not apply to RISC-V. While we are here, bootm.h is eventually removed as its content is only the inclusion of setup.h. Signed-off-by: Bin Meng --- Changes in v2: None arch/riscv/include/asm/bootm.h | 13 --- arch/riscv/include/asm/setup.h | 194

[U-Boot] [PATCH v2 01/15] riscv: kconfig: Normalize architecture name spelling

It's RISC-V that is the official name, not RISCV. Signed-off-by: Bin Meng --- Changes in v2: None arch/Kconfig | 2 +- arch/riscv/Kconfig | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/Kconfig b/arch/Kconfig index bf1b4a9..42c23b5 100644 ---

[U-Boot] [PATCH v2 00/15] riscv: Add QEMU virt board support

This series adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V. Some existing RISC-V codes have been changed to make it easily to support new targets. Some spotted coding style issues are fixed. This series is available at

Re: [U-Boot] [RFC PATCH 2/2] config.mk: Remove duplicated -fno-strict-aliasing

> From: Bin Meng [mailto:bmeng...@gmail.com] > Sent: Monday, September 10, 2018 9:54 PM > To: Simon Glass; Tom Rini; Rick Jian-Zhi Chen(陳建志); U-Boot Mailing List > Cc: Tuomas Tynkkynen > Subject: [RFC PATCH 2/2] config.mk: Remove duplicated -fno-strict-aliasing > > Now that we already

Re: [U-Boot] [PATCH 5/5] aspeed: Activate ethernet devices on the ast2500 Eval Board

On Mon, 10 Sep 2018 at 23:56, Cédric Le Goater wrote: > diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts > index 609678ff7989..1bd224dacf78 100644 > --- a/arch/arm/dts/ast2500-evb.dts > +++ b/arch/arm/dts/ast2500-evb.dts > + > + { > + status = "okay"; > + > +

Re: [U-Boot] .travis.yml: Fix typo in sun7i job description

On Sat, Sep 08, 2018 at 12:53:18AM +0300, Tuomas Tynkkynen wrote: > 'builman' -> 'buildman' > > Signed-off-by: Tuomas Tynkkynen Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature ___ U-Boot mailing list

[U-Boot] [ANN] U-Boot v2018.09 released

Hey all, It's release day, and here we are doing the release. It's live on git (I hope) and FTP and ACD (along with the PGP sig file). So with the v2018.07 release I mentioned various migration deadlines. We're closer to being able to call migrations done, but not quite. There's a few changes I

Re: [U-Boot] [RFC PATCH 1/2] Makefile: Use -fno-strict-aliasing globally

On Mon, Sep 10, 2018 at 06:53:45AM -0700, Bin Meng wrote: > The -fstrict-aliasing option is implicitly enabled at levels -O2, > -O3, -Os by GCC. This option allows the compiler to assume the > strictest aliasing rules applicable to the language being compiled. > For example, the practice of

Re: [U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

On Mon, Sep 10, 2018 at 11:17:30AM +0900, Masahiro Yamada wrote: > If the OOB size is not multiple of the cache line size, the ARMv7 > cache operation still warns "Misaligned operation at range". > > The real cache coherency problem was fixed by commit e3332e1a1a04 > ("Make kmalloc'ed memory

Re: [U-Boot] fdt: fix get_next_memory_node()

On Sun, Sep 09, 2018 at 04:30:11PM +0200, Marek Vasut wrote: > The get_next_memory_node() always sets mem to -1 , which is incorrect, > because then every iteration of memory bank parsing will start from the > first memory bank instead of the previous one. > > On systems with 1 memory bank

[U-Boot] [PATCH] socfpga: stratix10: fix sdram_calculate_size

Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen --- drivers/ddr/altera/sdram_s10.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_s10.c

[U-Boot] [PATCH v2 13/13] efi_loader: unset CONFIG_EFI_UNICODE_CAPITALIZATION

Unset CONFIG_EFI_UNICODE_CAPITALIZATION on boards with tough size restrictions. Signed-off-by: Heinrich Schuchardt --- v2 no change --- configs/vf610twr_defconfig | 1 + configs/vf610twr_nand_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/configs/vf610twr_defconfig

[U-Boot] [PATCH v2 09/13] efi_selftest: test EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL

Provide a unit test for the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. Signed-off-by: Heinrich Schuchardt --- v2 no change --- lib/efi_selftest/Makefile | 1 + lib/efi_selftest/efi_selftest_textinputex.c | 139 2 files changed, 140 insertions(+) create

[U-Boot] [PATCH v2 08/13] efi_loader: EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL

This patch implements the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. The implementation of notification functions is postponed to a later patch. Signed-off-by: Heinrich Schuchardt --- v2 rebase patch --- include/efi_api.h| 56 lib/efi_loader/efi_console.c | 253

[U-Boot] [PATCH v2 12/13] efi_selftest: test key notification functions

Use a key notification function to leave the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL test. Signed-off-by: Heinrich Schuchardt --- v2 no change --- lib/efi_selftest/efi_selftest_textinputex.c | 73 +++-- test/py/tests/test_efi_selftest.py | 4 +- 2 files changed, 68

[U-Boot] [PATCH v2 10/13] test/py: test EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL

Add a unit test for the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. Signed-off-by: Heinrich Schuchardt --- v2 no change --- test/py/tests/test_efi_selftest.py | 79 ++ 1 file changed, 79 insertions(+) diff --git a/test/py/tests/test_efi_selftest.py

[U-Boot] [PATCH v2 07/13] efi_loader: console input ESC a - ESC z

We have foreseen a work around for entering control codes in the EFI_SIMPLE_TEXT_INPUT_PROTOCOL. But currently we have an offset of one. ESC a should translate to 0x01 (CTRL+a). ESC z should translate to 0x1a (CTRL+z). Signed-off-by: Heinrich Schuchardt --- v2 no change ---

[U-Boot] [PATCH v2 11/13] efi_loader: implement key notify functions

Implement registering and unregistreing key notify functions in the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. Signed-off-by: Heinrich Schuchardt --- v2 rebase patch --- lib/efi_loader/efi_console.c | 101 +-- 1 file changed, 98 insertions(+), 3 deletions(-)

[U-Boot] [PATCH v2 0/13] efi_loader: EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL

Support Unicode letters received as UTF-8 from the serial console. Correct handling of the WaitForKey event. Update unit test for the EFI_SIMPLE_TEXT_INPUT__PROTOCOL. Fix bugs for the EFI_SIMPLE_TEXT_INPUT__PROTOCOL. Implement the EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL. Provide a unit test. Fix a

[U-Boot] [PATCH v2 04/13] efi_loader: rework event handling for console

Preread the next key in the console timer event. The EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL requires to trigger registered key notification functions based on the prefetched key. Signed-off-by: Heinrich Schuchardt --- v2 rebase patch --- lib/efi_loader/efi_console.c | 175

[U-Boot] [PATCH v2 06/13] test/py: rework test_efi_selftest_text_input()

Use more precise regular expressions. Signed-off-by: Heinrich Schuchardt --- v2 no change --- test/py/tests/test_efi_selftest.py | 17 +++-- 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/test/py/tests/test_efi_selftest.py

[U-Boot] [PATCH v2 03/13] efi_selftest: refactor text input test

Move reusable utility functions to efi_selftest_util.c. Signed-off-by: Heinrich Schuchardt --- v2 no change --- include/efi_selftest.h| 16 lib/efi_selftest/efi_selftest_textinput.c | 109 +- lib/efi_selftest/efi_selftest_util.c | 93

[U-Boot] [PATCH v2 05/13] efi_selftest: use WaitForKey to test text input

We should test the WaitForKey event. Testing for EFI_NOT_READY can be done after resetting the console. Signed-off-by: Heinrich Schuchardt --- v2 no change --- lib/efi_selftest/efi_selftest_textinput.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff

[U-Boot] [PATCH v2 02/13] test/py: Unicode w/ EFI_SIMPLE_TEXT_INPUT_PROTOCOL

Test that the Euro sign is correctly retrieved from the console via the EFI_SIMPLE_TEXT_INPUT_PROTOCOL. Signed-off-by: Heinrich Schuchardt --- v2 no change --- test/py/tests/test_efi_selftest.py | 7 +++ 1 file changed, 7 insertions(+) diff --git

[U-Boot] [PATCH v2 01/13] efi_loader: support Unicode text input

Up to now the EFI_TEXT_INPUT_PROTOCOL only supported ASCII characters. With the patch it can consume UTF-8 from the console. Currently only the serial console and the console can deliver UTF-8. Local consoles are restricted to ASCII. Signed-off-by: Heinrich Schuchardt --- v2: drop

Re: [U-Boot] [PATCH 3/3] arm; socfpga: stratix10: Add CONFIG_OF_EMBED

On 10.09.2018 20:21, Dalon L Westergreen wrote: On Mon, 2018-09-10 at 20:14 +0200, Simon Goldschmidt wrote: On 10.09.2018 19:28, Dalon Westergreen wrote: The dtb should be embedded in the u-boot-spl image so that the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it. This also affects the

Re: [U-Boot] Fwd: Parallel build is broken

On Wed, 2018-09-05 at 06:57 -0500, Adam Ford wrote: > On Wed, Sep 5, 2018 at 3:46 AM Alex Kiernan wrote: > > > > On Tue, Sep 4, 2018 at 3:54 PM Andy Shevchenko > > wrote: > > > > > > On Tue, Sep 4, 2018 at 5:50 PM Andy Shevchenko > > > wrote: > > > > > > > > On Tue, Sep 4, 2018 at 5:00 PM

Re: [U-Boot] [PATCH 0/3] add optional hex output of u-boot-spl

On 10.09.2018 20:18, Dalon L Westergreen wrote: On Mon, 2018-09-10 at 20:06 +0200, Simon Goldschmidt wrote: On 10.09.2018 19:28, Dalon Westergreen wrote: This patch set adds a possible hex output of the u-boot-spl elf and enables said output for the Intel Stratix10 device. Stratix10 requires a

Re: [U-Boot] [PATCH 3/3] arm; socfpga: stratix10: Add CONFIG_OF_EMBED

On Mon, 2018-09-10 at 20:14 +0200, Simon Goldschmidt wrote: > On 10.09.2018 19:28, Dalon Westergreen wrote: > The dtb should be embedded in the u-boot-spl image so that > the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it. > > This also affects the main u-boot image, so adjust >

Re: [U-Boot] [PATCH 0/3] add optional hex output of u-boot-spl

On Mon, 2018-09-10 at 20:06 +0200, Simon Goldschmidt wrote: > On 10.09.2018 19:28, Dalon Westergreen wrote: > This patch set adds a possible hex output of the > u-boot-spl elf and enables said output for the > Intel Stratix10 device. Stratix10 requires a hex > output of the elf for creating the

Re: [U-Boot] [PATCH 3/3] arm; socfpga: stratix10: Add CONFIG_OF_EMBED

On 10.09.2018 19:28, Dalon Westergreen wrote: The dtb should be embedded in the u-boot-spl image so that the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it. This also affects the main u-boot image, so adjust CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot,img which now Tiny typo: replace comma

Re: [U-Boot] [PATCH 0/3] add optional hex output of u-boot-spl

On 10.09.2018 19:28, Dalon Westergreen wrote: This patch set adds a possible hex output of the u-boot-spl elf and enables said output for the Intel Stratix10 device. Stratix10 requires a hex output of the elf for creating the secure device manager configuration bitstream. I don't use

[U-Boot] [PATCH 3/3] socfpga: common: add CONFIG_SPL_TARGET to gen5 and arria10 socfpga header

Add CONFIG_SPL_TARGET "u-boot-with-spl.sfp" to common header to generate the required u-boot-spl and u-boot combined image. Signed-off-by: Dalon Westergreen --- include/configs/socfpga_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/socfpga_common.h

[U-Boot] [PATCH 1/3] spl: socfpga: remove sfp generation

In preparation to move to using CONFIG_SPL_TARGET, remove sfp generation targets. Signed-off-by: Dalon Westergreen --- scripts/Makefile.spl | 12 1 file changed, 12 deletions(-) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 252f13826d..9314365aab 100644 ---

[U-Boot] [PATCH 2/3] socfpga: Add sfp generation targets

Some SOCFPGA platforms require a header be added to u-boot-spl and a combined spl / u-boot image. The combined image consists of 4 replicated u-boot-spl images with the afore mentioned header, and a u-boot image cat'ed together. Signed-off-by: Dalon Westergreen --- Makefile | 11 +++ 1

[U-Boot] [PATCH 0/3] socfpga: clean up sfp generation

Move gen5 and arria10 to use CONFIG_SPL_TARGET to specify the required SPL output. Dalon Westergreen (3): spl: socfpga: remove sfp generation socfpga: Add sfp generation targets socfpga: common: add CONFIG_SPL_TARGET to gen5 and arria10 socfpga header Makefile

[U-Boot] [PATCH 2/3] arm: socfpga: stratix10: add CONFIG_SPL_TARGET

Stratix10 combines the u-boot-spl image into the fpga configuration bitstream so that the SDM can load the processors memory. This process requires a hex format of the u-boot-spl image. CONFIG_SPL_TARGET is set to "spl/u-boot-spl.hex" Signed-off-by: Dalon Westergreen ---

[U-Boot] [PATCH 3/3] arm; socfpga: stratix10: Add CONFIG_OF_EMBED

The dtb should be embedded in the u-boot-spl image so that the CONFIG_SPL_TARGET of spl/u-boot-spl.hex includes it. This also affects the main u-boot image, so adjust CONFIG_SPL_FS_LOAD_PAYLOAD_NAME to u-boot,img which now also includes the dtb. Signed-off-by: Dalon Westergreen ---

[U-Boot] [PATCH 1/3] common: add spl/u-boot-spl.hex target

Some devices, namely Intel's stratix10 SoC, require u-boot-spl in a hex format. This patch adds spl/u-boot-spl.hex as a possible target. Signed-off-by: Dalon Westergreen --- Makefile | 5 + 1 file changed, 5 insertions(+) diff --git a/Makefile b/Makefile index f30dd8e9b7..133d7ac773

[U-Boot] [PATCH 0/3] add optional hex output of u-boot-spl

This patch set adds a possible hex output of the u-boot-spl elf and enables said output for the Intel Stratix10 device. Stratix10 requires a hex output of the elf for creating the secure device manager configuration bitstream. Dalon Westergreen (3): common: add spl/u-boot-spl.hex target arm:

[U-Boot] [PATCH v3 1/5] dm: gpio: Add get_alt_function ops

From: Patrick Delaunay When a pin is not configured as a GPIO, it could have several alternate function. To be able to identify the alternate function, add ops get_alt_function() to request the pin alternate function index from the driver when pin is not used as gpio. Signed-off-by: Patrick

[U-Boot] [PATCH v3 4/5] gpio: sandbox: Rename GPIOF_(OUTPUT|HIGH|ODR) to SANDBOX_GPIO_(OUTPUT|HIGH|ODR)

To avoid confusion with enum gpio_func_t GPIOF_OUTPUT defined in asm-generic/gpio.h, rename all sandbox flags GPIOF_(OUTPUT|HIGH|ODR) to SANDBOX_GPIO_(OUTPUT|HIGH|ODR) Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- Changes in v3: - Rename SDBX_GPIO_(OUTPUT|HIGH|ODR) to

[U-Boot] [PATCH v3 5/5] test: dm: Add gpio get_alt_function ops test

In order to test get_alt_function ops, add sandbox_gpio_set_function() and sandbox_gpio_set_alternate_function() to be able to configure a pin not as a GPIO and to select the alternate function index. Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- Changes in v3: - Rename

[U-Boot] [PATCH v3 0/5] Add get_alt_function ops

This series : - Add new gpio ops get_alt_function - Add get_function and get_alt_function support to stm32 gpio driver - Add get_alt_function test Changes in v3: - Rename get_alternate_function to get_alt_function in include/asm-generic/gpio.h - Rename get_alternate_function to

[U-Boot] [PATCH v3 3/5] gpio: stm32f7: Add ops get_alt_function

From: Patrick Delaunay Allow to display alternate function index using "gpio" command. Example, display all gpio state : gpio status -a GPIOD2: func: 12 GPIOD3: func: 9 GPIOE3: func: 9 GPIOG6: func: 10 It's useful to control pin configuration Signed-off-by: Patrick Delaunay

[U-Boot] [PATCH v3 2/5] gpio: stm32f7: Add ops get_function

From: Christophe Kerello This patch adds gpio get_function ops support. This function reports the state of a gpio. Signed-off-by: Christophe Kerello Reviewed-by: Simon Glass Signed-off-by: Patrice Chotard --- Changes in v3: None Changes in v2: None drivers/gpio/stm32f7_gpio.c | 20

[U-Boot] [PATCH 5/5] aspeed: Activate ethernet devices on the ast2500 Eval Board

Signed-off-by: Cédric Le Goater --- arch/arm/dts/ast2500-evb.dts | 17 + arch/arm/dts/ast2500.dtsi | 4 ++-- configs/evb-ast2500_defconfig | 8 3 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/ast2500-evb.dts

[U-Boot] [PATCH 4/5] net: ftgmac100: add support for Aspeed SoC

The Faraday ftgmac100 MAC controllers as found on the Aspeed SoCs have some slight differences in the HW interface (End-Of-Rx/Tx-Ring bits). Also include the Aspeed clock enablement. Signed-off-by: Cédric Le Goater --- drivers/net/ftgmac100.h | 5 +++ drivers/net/ftgmac100.c | 72

[U-Boot] [PATCH 3/5] aspeed: ast2500: fix missing break in D2PLL clock enablement

Signed-off-by: Cédric Le Goater --- drivers/clk/aspeed/clk_ast2500.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index c55f8d5ae30d..169c330d3d41 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++

[U-Boot] [PATCH 2/5] net: re-add support for the Faraday ftgmac100 controller

The driver is based on the previous one and adds the same support for the Faraday ftgmac100 controller with MAC and MDIO bus support for RGMII/RMII modes. Driver model support was added as well as some enhancements and fixes. Signed-off-by: Cédric Le Goater --- drivers/net/ftgmac100.h | 242

[U-Boot] [PATCH 1/5] net: remove the Faraday ftgmac100 controller driver

There are too many changes in the following patch fixing support for the Faraday ftgmac100 controller. To ease the review, remove the whole file which is not compiled anymore today (no Kconfig option for the driver). Signed-off-by: Cédric Le Goater --- drivers/net/ftgmac100.h | 242

[U-Boot] [PATCH 0/5] Support for the Faraday ftgmac100 controller

Hello, This series re-adds a driver for the Faraday ftgmac100 controller and its Aspeed variant as as one can find on the OpenPOWER platforms. I have choosen to remove and re-add the driver to ease review of the changes, which are numerous, but we can proceed differently if you prefer. The DT

[U-Boot] [PATCH 3/3] aspeed: Add SPI support to the ast2500 Eval Board

Signed-off-by: Cédric Le Goater --- arch/arm/dts/ast2500-evb.dts | 17 arch/arm/dts/ast2500-u-boot.dtsi | 12 ++ arch/arm/dts/ast2500.dtsi| 71 configs/evb-ast2500_defconfig| 10 + 4 files changed, 110 insertions(+) diff --git

[U-Boot] [PATCH 1/3] aspeed: ast2500: Add AHB clock

The AHB clock is used by the FMC/SPI controllers. Signed-off-by: Cédric Le Goater --- arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 2 ++ include/dt-bindings/clock/ast2500-scu.h| 1 + drivers/clk/aspeed/clk_ast2500.c | 12 3 files changed, 15

[U-Boot] [PATCH 2/3] spi: Add support for the Aspeed ast2500 SPI controllers

The Aspeed AST2500 SoC comes with three static memory controllers, all with a similar interface : * Firmware SPI Memory Controller (FMC) . BMC firmware . 3 chip select pins (CE0 ~ CE2) . supports SPI type flash memory (CE0 ~ CE1) . CE2 can be of NOR type flash but this is not

[U-Boot] [PATCH 0/3] Support for the Aspeed ast2500 FMC/SPI controllers

Hello, This series adds a driver for the Aspeed ast2500 FMC/SPI controllers as one can find on the POWER9 OpenPOWER platforms. It was tested on the AST2500 evb using a w25q256 flash device. Git tree available here: https://github.com/legoater/u-boot/commits/aspeed Thanks, C. Cédric Le

Re: [U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

2018-09-10 22:26 GMT+09:00 Marek Vasut : > On 09/10/2018 04:17 AM, Masahiro Yamada wrote: >> If the OOB size is not multiple of the cache line size, the ARMv7 >> cache operation still warns "Misaligned operation at range". >> >> The real cache coherency problem was fixed by commit e3332e1a1a04 >>

[U-Boot] [RFC PATCH 2/2] config.mk: Remove duplicated -fno-strict-aliasing

Now that we already disable the "strict-aliasing" globally, remove the duplicates in the nds32/riscv/x86 arch-specific Makefiles. Signed-off-by: Bin Meng --- arch/nds32/config.mk | 2 +- arch/riscv/config.mk | 2 +- arch/x86/config.mk | 1 - 3 files changed, 2 insertions(+), 3 deletions(-)

[U-Boot] [RFC PATCH 1/2] Makefile: Use -fno-strict-aliasing globally

The -fstrict-aliasing option is implicitly enabled at levels -O2, -O3, -Os by GCC. This option allows the compiler to assume the strictest aliasing rules applicable to the language being compiled. For example, the practice of reading from a different union member than the one most recently written

Re: [U-Boot] [PATCH] mtd: nand: denali: fix unaligned cache operation warnings on ARMv7 SoCs

On 09/10/2018 04:17 AM, Masahiro Yamada wrote: > If the OOB size is not multiple of the cache line size, the ARMv7 > cache operation still warns "Misaligned operation at range". > > The real cache coherency problem was fixed by commit e3332e1a1a04 > ("Make kmalloc'ed memory really DMA-safe").

Re: [U-Boot] [PATCH 2/6] efi_loader: support Unicode text input

On 09/10/2018 12:05 PM, Alexander Graf wrote: On 09/09/2018 07:57 AM, Heinrich Schuchardt wrote: Up to now the EFI_TEXT_INPUT_PROTOCOL only supported ASCII characters. With the patch it can consume UTF-8 from the serial console or codepage 437 special characters from the local keyboard.

Re: [U-Boot] [PATCH] fdt: fix get_next_memory_node()

On 10.9.2018 13:27, Marek Vasut wrote: > On 09/10/2018 01:23 PM, Michal Simek wrote: >> On 9.9.2018 16:30, Marek Vasut wrote: >>> The get_next_memory_node() always sets mem to -1 , which is incorrect, >>> because then every iteration of memory bank parsing will start from the >>> first memory bank

Re: [U-Boot] PBIAS driver and MMC Interaction in U-Boot Question

Hi Adam, On 09/09/2018 14:19, Adam Ford wrote: I was having some issues with a DM3730 properly reading the card detect on GPIO 127 and attributed it to being related to the pbias register. I have since submitted a patch to enable GPIO_127, but I am not the best approach. On the HSMMC driver,

Re: [U-Boot] [PATCH] fdt: fix get_next_memory_node()

On 09/10/2018 01:23 PM, Michal Simek wrote: > On 9.9.2018 16:30, Marek Vasut wrote: >> The get_next_memory_node() always sets mem to -1 , which is incorrect, >> because then every iteration of memory bank parsing will start from the >> first memory bank instead of the previous one. >> >> On

Re: [U-Boot] [PATCH] fdt: fix get_next_memory_node()

On 9.9.2018 16:30, Marek Vasut wrote: > The get_next_memory_node() always sets mem to -1 , which is incorrect, > because then every iteration of memory bank parsing will start from the > first memory bank instead of the previous one. > > On systems with 1 memory bank defined in DT and

[U-Boot] kgdb support for aarch64 architecture based boards

Hi All, I am planning to understand & work on kgdb stubs on u-boot for aarch64 architecture. Is anyone working on it and are they have any progress / stubs done for the aarch64. I saw there are stubs in u-boot directory for 'power pc' architecture. I am planning to bring the similar way of

[U-Boot] [PATCH] Convert CONFIG_DISABLE_CONSOLE to Kconfig

This converts the following to Kconfig: CONFIG_DISABLE_CONSOLE Signed-off-by: Christian Gmeiner --- common/Kconfig | 5 + scripts/config_whitelist.txt | 1 - 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index

Re: [U-Boot] [PATCH 2/6] efi_loader: support Unicode text input

On 09/09/2018 07:57 AM, Heinrich Schuchardt wrote: Up to now the EFI_TEXT_INPUT_PROTOCOL only supported ASCII characters. With the patch it can consume UTF-8 from the serial console or codepage 437 special characters from the local keyboard. Signed-off-by: Heinrich Schuchardt ---

[U-Boot] [PATCH 1/1] video: cfb_console: flush cache in display_rle8_bitmap

Otherwise BMP RLE8 images are not properly displayed. Signed-off-by: Sébastien Szymanski --- drivers/video/cfb_console.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 40110668a6..636c3e8c18 100644 ---

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