From: Siva Durga Prasad Paladugu
This patch adds new config option which is used for
reserving a specific memory for MMU Table and in this
case we are using TCM for that purpose.
Signed-off-by: Siva Durga Prasad Paladugu
Signed-off-by: Michal Simek
---
arch/arm/mach-versal/Kconfig
Convert board from OF_EMBED to OF_SEPARATE.
Signed-off-by: Michal Simek
---
configs/bitmain_antminer_s9_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/bitmain_antminer_s9_defconfig
b/configs/bitmain_antminer_s9_defconfig
index 545042f4bdc3..82354a515608 100644
---
On Wed, Dec 12, 2018 at 11:08 PM Vignesh R wrote:
>
> Add non DM version of SPI_MEM to support easy migration to new SPI NOR
> framework. This can be removed once DM_SPI conversion is complete.
>
> Signed-off-by: Vignesh R
> ---
> drivers/spi/Kconfig| 4 +-
> drivers/spi/Makefile
On Fri, Dec 21, 2018 at 12:08 PM Vignesh R wrote:
>
> It is necessary to call spi_claim_bus() before starting any SPI
> transactions and this restriction would also apply when calling spi-mem
> operationss. Therefore claim and release bus before requesting transfer
> via exec_op.
>
>
The am654_sdhci driver needs to switch the clock off
before disabling its phy dll and needs to re-enable
the clock before enabling the phy again.
Therefore, make the sdhci_set_clock() function accessible
in the am654_sdhci driver.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 2 +-
From: Faiz Abbas
Add a platform specific set_control_reg() callback to help switch to
UHS speed modes.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/am654_sdhci.c
From: Faiz Abbas
The HOST_CONTROL2 register is a part of SDHC v3.00 and not just specific
to arasan/zynq controllers. Add the same to sdhci.h.
Also create a common API to set UHS timings in HOST_CONTROL2.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 28
Make set_ios_post() return int to faciliate error handling in
platform drivers.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 6 +-
drivers/mmc/xenon_sdhci.c | 4 +++-
include/sdhci.h | 2 +-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git
Add Support for CONFIG_REGMAP.
Signed-off-by: Faiz Abbas
---
configs/am65x_evm_a53_defconfig | 2 ++
configs/am65x_evm_r5_defconfig | 2 ++
2 files changed, 4 insertions(+)
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 6db3dac4c7..8fb28ca127 100644
---
Add an API to continuously read a register until a condition is
satisfied or a timeout occurs.
Signed-off-by: Faiz Abbas
---
include/regmap.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/include/regmap.h b/include/regmap.h
index 3cd97d3b94..dfc3a4f231
In device nodes with more than one entry in the reg property,
it is sometimes useful to regmap only of the entries. Add an
API regmap_init_mem_index() to facilitate this.
Signed-off-by: Faiz Abbas
---
drivers/core/regmap.c | 42 ++
include/regmap.h |
Add Support for masking some bits in the capabilities
register of a host controller.
Also remove the redundant readl() into caps1.
Signed-off-by: Faiz Abbas
---
drivers/mmc/sdhci.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/sdhci.c
Add support in the driver for handling phy specific registers.
Signed-off-by: Faiz Abbas
---
drivers/mmc/Kconfig | 1 +
drivers/mmc/am654_sdhci.c | 224 +-
2 files changed, 222 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/Kconfig
With changes in the driver requiring phy related properties,
add the same for the SD card node to prevent breaking boot with
the driver update.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
Sync the sdhci0 node from kernel. This changes the compatible that is
required to be there in the driver. Change the same for the SD card node
which is not yet supported in kernel.
Also sync the main_pmx0 node as a side effect.
Signed-off-by: Faiz Abbas
---
arch/arm/dts/k3-am65-main.dtsi
The host controller works perfectly well without having to add any
quirks. Remove them.
Signed-off-by: Faiz Abbas
---
drivers/mmc/am654_sdhci.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 3afdb58293..69914deb0c 100644
---
This driver works with the sdhci controller present on TI's AM65x devices.
Change the name to make this clearer and match the compatible with
kernel.
Signed-off-by: Faiz Abbas
---
configs/am65x_evm_a53_defconfig | 2 +-
configs/am65x_evm_r5_defconfig| 2 +-
Add Support for eMMC in TI's AM65x-evm. The series starts
by syncing the sdhci0 node from the kernel. Then it adds APIs and
changes to the driver required for handling the driver's integrated
phy. The current maximum supported speed is DDR52. Higher speeds and
tuning support will be added in a
On 25.01.19 18:04, Vladimir Vid wrote:
This adds initial support for micro-DPU (uDPU) board which is based on
Armada-3720 SoC.
micro-DPU is the single-port FTTdp "distribution point unit" made by Methode
Electronics
which offers complete modularity with replaceable SFP modules both for uplink
On Fri, Jan 25, 2019 at 8:30 PM Vignesh R wrote:
>
>
>
> On 25/01/19 8:17 PM, Jagan Teki wrote:
> > On Fri, Dec 21, 2018 at 12:18 PM Vignesh R wrote:
> >>
> >> SF_DUAL_FLASH claims to enable support for SF_DUAL_STACKED_FLASH and
> >> SF_DUAL_PARALLEL_FLASH. But, in current U-Boot code, grepping
Do you have this whole series in some branch in github? I'm unable to
apply it on master.
On Fri, Dec 21, 2018 at 12:15 PM Vignesh R wrote:
>
> Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
> support 4 byte addressing opcodes, SFDP table parsing and different types
> Enable sound for this board, which has the same codec as jerry.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/arm/dts/rk3288-veyron-minnie.dts | 12
> configs/chromebook_minnie_defconfig | 5 +
> 2 files changed, 17 insertions(+)
>
Reviewed-by: Philipp Tomsich
> Add a driver for I2S which allows audio data to be sent from the SoC to
> the audio codec. The sample rate and other settings are hard-coded for now
> as there is no suitable device-tree binding available.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/sound/Kconfig| 9 +++
>
> Add a sound driver for rk3288 supporting chromebook_jerry. This uses the
> I2S driver, and existing audio codec and the clock/pinmux support.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/sound/Makefile | 2 +-
> drivers/sound/rockchip_sound.c | 132
> Jerry uses a max98090 audio codec and the internal SoC I2S peripheral.
> Enable sound support and add the required device-tree pieces.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/arm/dts/rk3288-veyron-jerry.dts | 12
> arch/arm/dts/rk3288-veyron.dtsi | 1 +
>
> Add support for setting pinctrl and clock for I2S on rk3288. This allows
> the sound driver to operate. These settings were created by rkmux.py
>
> Signed-off-by: Simon Glass
> ---
>
> .../include/asm/arch-rockchip/cru_rk3288.h| 8 ++
> .../include/asm/arch-rockchip/grf_rk3288.h| 96
AVB version 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].
Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent
AVB version 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].
Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent
Am 26.01.2019 um 10:00 schrieb Marek Vasut:
On 1/25/19 9:30 PM, Simon Goldschmidt wrote:
This commit removes ad-hoc reset handling for peripheral resets from SPL
for socfpga gen5.
This is done because as U-Boot drivers support reset handling by now.
For kernels that don't support taking
Am 26.01.2019 um 09:59 schrieb Marek Vasut:
On 1/25/19 9:30 PM, Simon Goldschmidt wrote:
This adds reset handling to the devicetree-enabled denalid nand driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: Simon Goldschmidt
---
Am 26.01.2019 um 09:58 schrieb Marek Vasut:
On 1/25/19 9:30 PM, Simon Goldschmidt wrote:
To clean up reset handling for socfpga gen5, let's move the code snippet
taking the DDR controller out of reset from SPL to the DDR driver.
Signed-off-by: Simon Goldschmidt
---
Am 26.01.2019 um 09:57 schrieb Marek Vasut:
On 1/25/19 9:30 PM, Simon Goldschmidt wrote:
The SPL for socfpga gen5 currently takes all peripherals out of reset
unconditionally. To implement proper reset handling for peripherals,
some device tree nodes are missing reset handles.
Since the
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