Add init_func_vid() which calls adjust_vdd()
This ensures adjust_vdd() is called via
init_sequence_f[]
Signed-off-by: Priyanka Jain
---
board/freescale/lx2160a/lx2160a.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/board/freescale/lx2160a/lx2160a.c
On 02/02/19 2:34 AM, Andrew F. Davis wrote:
> The second loader stages may be stored on GPT partitions,
> enable support for this here.
>
> Signed-off-by: Andrew F. Davis
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
___
U-Boot mailing list
On 02/02/19 2:34 AM, Andrew F. Davis wrote:
> The first element in the debug section is expected to be debugUID.
> ROM will not parse this correctly when out of order, fix this here.
>
> Signed-off-by: Andrew F. Davis
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
On 02/02/19 2:34 AM, Andrew F. Davis wrote:
> Bootm will fail to load kernels over 8MB, this is not enough
> for our 64bit kernel images. Increase this to 64MB.
>
> Signed-off-by: Andrew F. Davis
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
> ---
> include/configs/am65x_evm.h | 2
From: Grygorii Strashko
Enable TI K3 AM65x CPSW NUSS driver.
Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
Changes in v2:
Added Tom's Reviewed-by
configs/am65x_evm_a53_defconfig | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Grygorii Strashko
Add mcu cpsw nuss pinmux and phy defs required by cpsw.
Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
Changes in v2:
Added Tom's Reviewed-by
arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 59
1 file
From: Grygorii Strashko
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface
On 04/02/19 9:34 AM, Keerthy wrote:
> Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
> NUSS). It has two ports and provides Ethernet packet communication for the
> device and can be configured as an Ethernet switch. CPSW NUSS features: the
> Reduced Gigabit Media
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
Add new driver for the TI AM65x SoC Gigabit Ethernet Switch subsystem (CPSW
NUSS). It has two ports and provides Ethernet packet communication for the
device and can be configured as an Ethernet switch. CPSW NUSS features: the
Reduced Gigabit Media Independent Interface (RGMII), Reduced Media
From: Grygorii Strashko
Use phys_addr_t for mdio_base address to avoid build warnings on arm64.
Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
Changes in v2:
Added Tom's Reviewed-by
drivers/net/ti/cpsw_mdio.c | 2 +-
drivers/net/ti/cpsw_mdio.h |
From: Grygorii Strashko
Add mcu cpsw and its components along with scm_conf node
to have ethernet functional.
Signed-off-by: Grygorii Strashko
Signed-off-by: Keerthy
Reviewed-by: Tom Rini
---
Changes in v2:
Added Tom's Reviewed-by
arch/arm/dts/k3-am65.dtsi|
For the RK3399-Q7 we recommend storing SPL and u-boot.itb in the
on-module 32MBit (and sometimes even larger, if requested as part of a
configure-to-order configuration) SPI-NOR flash that is clocked for a
bitrate of 49.5MBit/s and connected in a single-IO configuration (the
RK3399 only supports
The SPI controller's documentation (I only had access to the RK3399,
RK3368 and PX30 TRMs) specifies that, when operating in master-mode,
the controller will stop the SCLK to avoid RXFIFO overruns and TXFIFO
underruns. Looks like my worries that we'd need to support DMA-330
(aka PL330) to make
While rkspi_enable_chip is called with true/false everywhere else in
the file, one call site uses '0' to denot 'false'.
This change this one parameter to 'false' and effects consistency.
Signed-off-by: Philipp Tomsich
---
drivers/spi/rk_spi.c | 2 +-
1 file changed, 1 insertion(+), 1
The maximum transfer length (in a single transaction) for the Rockchip
SPI controller is 64Kframes (i.e. 0x1 frames) of 8bit or 16bit
frames and is encoded as (num_frames - 1) in CTRLR1. The existing
code subtracted the "minus 1" twice for a maximum transfer length of
0x (64K - 1) frames.
The SPI-NOR driver has traditionally been slow enough to impact
boot-time from SPI-NOR (which is the recommended storage for
u-boot.itb on the RK3399-Q7): transfer for the ~890KB exceeded 0.8s
even though the SPI-NOR bitrate was configured to 49.5MBit/s.
This series provides some urgently needed
To support unaligned output buffers (i.e. 'in' in the terminology of
the SPI framework), this change splits each 16bit FIFO element after
reading and writes them to memory in two 8bit transactions. With this
change, we can now always use the optimised mode for receive-only
transcations
The logic in the main transmit loop took a bit of reading the TRM to
fully understand (due to silent assumptions based in internal logic):
the "wait until idle" at the end of each iteration through the loop is
required for the transmit-path as each clearing of the ENA register
(to update
Even though the priv-structure and the claim-bus function contain
logic for 16bit frames and for unidirectional transfer modes, neither
of these is used anywhere in the driver.
This removes the unused (as in "has no effect") logic and fields.
Signed-off-by: Philipp Tomsich
---
In analysing delays introduced for large SPI reads, the absence of any
indication when a delay was inserted (to ensure the CS toggling is
observed by devices) became apparent.
Add an additional debug-only debug message to record the insertion and
duration of any delay (note that the debug-message
On 2019-02-03 15:59, Philipp Tomsich wrote:
Over the last quarter, a part of our production has used NOR flash
from Gigadevice in addition to the Winbond parts that we typically
source. This requires the SPI_FLASH_GIGADEVICE config to be set.
Enable SPI_FLASH_GIGADEVICE in the board's default
Over the last quarter, a part of our production has used NOR flash
from Gigadevice in addition to the Winbond parts that we typically
source. This requires the SPI_FLASH_GIGADEVICE config to be set.
Enable SPI_FLASH_GIGADEVICE in the board's default defconfig.
Signed-off-by: Philipp Tomsich
The PCIe slot PERST signal is active low. Fix the gpio signal
description in the dts.
This happened to work because the pcie_dw_mvebu driver sets the reset
gpio level to 1 (high) to release the reset. The following commit will
fix that.
Signed-off-by: Baruch Siach
---
Describe the mini-PCIe slot gpio reset signal. This enables PCIe devices
on Clearfog GT-8K.
Signed-off-by: Baruch Siach
---
arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.
Reported-by: Sven Auhagen
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