Greetings Alex and everyone,
Currently I'm trying to block all some PC applications that is appearing as
hidden, system files as well as unknown files on my mobile phones, and any
related to my laptop. It's blocking me from writing proper commands. And
upon every restore, reinstall etc, I will ha
With board_ahci_enable() implementation for Armada 38x in place we can
now enable 38x support in the ahci_mvebu driver.
Signed-off-by: Baruch Siach
---
drivers/ata/ahci_mvebu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index 6e3f17ee2
This allows the ahci_mvebu driver to do A38x platform specific
configuration at initialization.
Signed-off-by: Baruch Siach
---
arch/arm/mach-mvebu/cpu.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index
Update the kirkwood entry to match MAINTAINERS following commit
1579faf52b9f4 ("MAINTAINERS: Update u-boot-marvell entry").
Signed-off-by: Baruch Siach
---
doc/git-mailrc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/doc/git-mailrc b/doc/git-mailrc
index c2eee8c7d82f..ee
This patch series adds basic boot support on eMMC for the MediaTek MT8516 SoC
based boards. This series adds the clock, pinctrl drivers and the SoC
initialization code.
Fabien Parent (7):
mmc: mtk-sd: add source_cg clock support
mmc: mtk-sd: add support for MT8516
mmc: mtk-sd: fix configurat
Some MediaTek SoC need an additional clock "source_cg". Enable
this new clock. We reuse the same clock name as in the kernel.
Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
---
v3:
* No change
v2:
* Get rid of variable has_src_clk_cg
---
drivers/mmc/mtk-sd.c | 5 +
1 fi
Add config for handling MT8516 SoC.
Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
---
v3:
* No change
v2:
* No change
---
drivers/mmc/mtk-sd.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index eed98b769c..b446
Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
---
v3:
* No changes
---
drivers/clk/mediatek/clk-mtk.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/
We either need to use IS_ENABLED(CONFIG_FOO) or CONFIG_IS_ENABLED(FOO).
IS_ENABLE(FOO) will always return false.
This commit fixes the comparison by using the CONFIG_IS_ENABLED(FOO)
syntax.
Signed-off-by: Fabien Parent
---
v3:
* New patch
---
drivers/mmc/mtk-sd.c | 8
1 file
Add Pinctrl driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
---
v3:
* Fix incorrect field size for mt8516_pin_mode_range
v2:
* No change
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
Add support for MediaTek MT8516 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: Fabien Parent
Reviewed-by: Tom Rini
---
v3:
* No change
v2:
* Move u-boot,dm-pre-reloc into a seperate dts
* Implement dram_init_banksi
Hi Daniel,
The 03/15/2019 13:02, Daniel Schwierzeck wrote:
> External E-Mail
>
>
> Hi Horatio,
>
> Am 06.03.19 um 23:11 schrieb Horatiu Vultur:
> > Hi Daniel,
> >
> > The 03/06/2019 14:19, Daniel Schwierzeck wrote:
> >>
> >>
> >> Am 05.03.19 um 12:57 schrieb Horatiu Vultur:
> >>> In Jaguar2 S
Add clock driver for MediaTek MT8516 SoC.
Signed-off-by: Fabien Parent
Acked-by: Ryder Lee
---
v3:
* Remove invalid clocks
v2:
* Fix invalid GATE_TOP5 flag
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8516.c | 802 +++
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.
Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However,
On Mon, 2019-03-11 at 14:01 +, Igor Opaniuk wrote:
> Off-topic: I'm just wondering, why no one introduced a proper Kconfig
> symbol for
> FDT_FIXUP_PARTITIONS. Currently there is no any description of this
> option through
> the code and what it's actually used for. But, anyway, it doesn't
> di
Hi Stefano
On Wed, 2019-03-13 at 09:38 +, sba...@denx.de wrote:
> > From: Gerard Salvatella
> > The PMIC on the Colibri iMX6 may have ECC errors in fuses that will
> > prevent correct settings. Up to one bit error per fuse bank can be
> > reported and corrected by the ECC logic. Two bit error
From: Hou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape series SoCs.
Resend this patch set with the rev1.0 only workaround patches removed.
Hou Zhiqiang (9):
armv8: fsl-layerscpae: correct the PCIe controllers' region size
armv8: lx2160a: add MMU table entries for PCIe
pci: Add PCIe
From: Hou Zhiqiang
The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape
From: Hou Zhiqiang
The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl
From: Hou Zhiqiang
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang
Signed-off-by: Bao Xiaowei
---
V4:
- No change
drivers/pci/Kconfig
From: Hou Zhiqiang
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/cpu/armv8/fsl-layerscape/cpu.c| 12
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
.
From: Hou Zhiqiang
Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB
and LX2160AQDS boards.
Signed-off-by: Hou Zhiqiang
---
V4:
- Add PCI command support
- Enable PCIe in more LX2160A defconfigs
configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 5 +
configs/lx2160aqds_tfa_def
From: Hou Zhiqiang
This patch introduce a set of PCI/PCIe capability accessors,
including 16-bit and 32-bit read, write and clear_and_set
operations.
Signed-off-by: Hou Zhiqiang
---
V4:
- New patch
drivers/pci/pci-uclass.c | 153 +++
include/pci.h
From: Hou Zhiqiang
Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
drivers/pci/Makefile | 3 +-
drivers/pci/pcie_layerscape_gen4.c
From: Hou Zhiqiang
The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: Hou Zhiqiang
---
V4:
- No change
arch/arm/dts/fsl-lx2160a.dtsi | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/dts/fsl-lx2160a.dtsi b/arch/arm/dts/fsl-lx2160a.d
From: Hou Zhiqiang
This patch introduce APIs for getting and updating the MPS
and MRRS fields of Device capability Device control register.
Signed-off-by: Hou Zhiqiang
---
V4:
- New patch
drivers/pci/pci-uclass.c | 92
include/pci.h| 13 ++
Hi Prabhakar,
Thanks a lot for your comments!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: 2019年3月17日 11:28
> To: Z.q. Hou ; u-boot@lists.denx.de;
> bmeng...@gmail.com; albert.u.b...@aribaud.net; Priyanka Jain
> ; York Sun ;
> sriram.d...@nxp.com; yamada.masah...@socionext.com;
On Fri, Mar 22, 2019 at 7:39 PM Simon Goldschmidt
wrote:
>
> On Fri, Mar 22, 2019 at 10:05 AM Ley Foon Tan wrote:
> >
> > Add QSPI device tree to Stratix 10.
> > Sync from Linux Stratix 10 dts.
> >
> > Tested on Stratix 10 SoC devkit.
> > SOCFPGA_STRATIX10 # sf probe 0:0
> > SF: Detected mt25qu02
On Fri, Mar 22, 2019 at 8:42 PM Simon Goldschmidt
wrote:
>
> Marek Vasut schrieb am Fr., 22. März 2019, 13:35:
>
> > On 3/22/19 1:27 PM, Simon Goldschmidt wrote:
> > > On Fri, Mar 22, 2019 at 1:18 PM Simon Goldschmidt
> > > wrote:
> > >>
> > >> On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut wrote:
Add QSPI device tree to Stratix 10.
Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit.
SOCFPGA_STRATIX10 # sf probe 0:0
SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256
MiB
Signed-off-by: Ley Foon Tan
---
v2->v3:
- Change flash compatible to "jedec,sp
On Mon, Mar 4, 2019 at 8:24 PM Jagan Teki wrote:
>
> On Wed, Feb 27, 2019 at 11:06 AM Ley Foon Tan wrote:
> >
> > Use quad write if SPI_TX_QUAD flag is set.
> >
> > Tested quad write on Stratix 10 SoC board (Micron
> > serial NOR flash, mt25qu02g)
> >
> > Signed-off-by: Ley Foon Tan
> >
> > ---
Reviewed-by: Bernhard Messerklinger
Tested-by: Bernhard Messerklinger
Von:Anssi Hannula
An: u-boot@lists.denx.de, Bernhard Messerklinger
Kopie: Hannes Schmelzer
Datum: 02/27/2019 11:56 AM
Betreff:[PATCH v2] fs: fat: fix reading non-cluster-aligned root
directory
A F
Hi Seung-Woo,
On Tue, 20 Nov 2018 at 11:25, Seung-Woo Kim wrote:
>
> This reverts commit 232ed3ca534708527a9515c7c41bc3542949525c.
>
> In exynos boards, ${console} is used to set bootargs but it sets
> without "console=", so CONFIG_DEFAULT_CONSOLE for these boards is
> designated with "console="
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