On 26.04.19 08:23, Qiang Zhao wrote:
Signed-off-by: Zhao Qiang
---
include/configs/ls1028a_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 3cb64c5f0c..3aec8087af 100644
--- a/include/configs/ls1028a_commo
On 26.04.19 08:22, Qiang Zhao wrote:
sp805 is watchdog on some NXP layerscape SoCs, Now add its driver in uboot.
Signed-off-by: Zhao Qiang
---
MAINTAINERS | 1 +
common/board_f.c | 2 +-
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile|
Hi Jan,
> Subject: [EXT] [U-Boot] [PATCH] MMC HW partition switching must also
> invalidate the cache
>
Please add a bit more commit information about why and how.
Thanks,
Peng.
>
> Signed-off-by: Jan Šedivý
> ---
>
> drivers/mmc/mmc.c | 14 --
> 1 file changed, 12 insertions(+
On Tue, Apr 23, 2019 at 6:14 PM Marek Vasut wrote:
>
> The usage of socfpga_sdram_apply_static_cfg() seems rather dubious and
> is confirmed to lead to a rare system hang when enabling bridges. This
> patch removes the socfpga_sdram_apply_static_cfg() altogether, because
> it's use seems unjustifi
On Mon, Apr 22, 2019 at 9:24 PM Marek Vasut wrote:
>
> On 4/22/19 9:18 PM, Simon Goldschmidt wrote:
> >
> >
> > On 22.04.19 20:41, Marek Vasut wrote:
> >> On 4/22/19 8:22 PM, Simon Goldschmidt wrote:
> >>> Am 22.04.2019 um 20:01 schrieb Marek Vasut:
> On 4/19/19 10:00 PM, Simon Goldschmidt wr
On Fri, Apr 26, 2019 at 2:23 PM Qiang Zhao wrote:
>
> Signed-off-by: Zhao Qiang
> ---
> include/configs/ls1028a_common.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/configs/ls1028a_common.h
> b/include/configs/ls1028a_common.h
> index 3cb64c5f0c..3aec8087af 100644
> --- a
Signed-off-by: Zhao Qiang
---
include/configs/ls1028a_common.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index 3cb64c5f0c..3aec8087af 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.
sp805 is watchdog on some NXP layerscape SoCs, Now add its driver in uboot.
Signed-off-by: Zhao Qiang
---
MAINTAINERS | 1 +
common/board_f.c | 2 +-
drivers/watchdog/Kconfig | 8 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/sp805_wdt.c | 70 +++
Marek Vasut schrieb am Fr., 26. Apr. 2019, 00:22:
> On 4/25/19 9:22 PM, Simon Goldschmidt wrote:
> > If the malloc range passed to mem_malloc_init() is at the end of address
> > range and 'start + size' overflows to 0, following allocations fail as
> > mem_malloc_end is zero (which looks like uni
On Mon, 2019-04-22 at 13:29 -0400, Tom Rini wrote:
> On Wed, Feb 13, 2019 at 08:32:24PM +0800, tien.fong.c...@intel.com
> wrote:
>
> >
> > From: Tien Fong Chee
> >
> > This would print out all the FPGA node names setting to fpga
> > property.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> >
Hi Peng,
Thank you for your feedback.
> > Subject: [PATCH v3 07/11] dm: clk: Define clk_get_parent_rate() for
> > clk operations
> >
> > This commit adds the clk_get_parent_rate() function, which is
> > responsible for getting the rate of parent clock.
> > Unfortunately, u-boot's DM support for
On Fri, 26 Apr 2019 02:56:48 +
Breno Matheus Lima wrote:
> In certain i.MX devices the encrypted boot image is failing to boot.
>
> According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled
> Devices" it's necessary to pad CSF to 0x2000 and append DEK blob.
>
> In this case the total i
On Fri, Apr 12, 2019 at 11:38 AM Frank Wunderlich
wrote:
>
Missing description here. I just saw I forgot this comment for the 1/2
patch, too.
There's no description there as well.
> Signed-off-by: Frank Wunderlich
> ---
> env/mmc.c | 28
> 1 file changed, 28 insert
On Fri, Apr 12, 2019 at 11:38 AM Frank Wunderlich
wrote:
>
> Signed-off-by: Frank Wunderlich
> ---
> cmd/nvedit.c | 13 +
> env/env.c | 30 ++
> include/environment.h | 17 +
> 3 files changed, 60 insertions(+)
>
> diff
Hi,
On 24/04/19 6:32 PM, Rajat Srivastava wrote:
> Some Freescale QSPI controllers require driver to send only 16 bytes
> aligned data to TxFIFO while performing flash write operation. The extra
> data is not actually written on flash. The patch enables driver to send
> 16 bytes aligned data to Tx
On 25/04/19 5:20 PM, Rajat Srivastava wrote:
>
>
>> -Original Message-
>> From: Vignesh Raghavendra
>> Sent: Wednesday, April 24, 2019 10:17 PM
>> To: Rajat Srivastava ; u-boot@lists.denx.de;
>> ja...@openedev.com
>> Cc: Ashish Kumar
>> Subject: [EXT] Re: [PATCH 2/2] fsl_qspi: Improve
On 26/04/19 4:56 AM, Simon Glass wrote:
> Hi Bin,
>
> I find that 'sf test 0 1000' does not work anymore since this commit:
>
> c4e8862308 mtd: spi: Switch to new SPI NOR framework
>
> Have you seen any problems? This seems to prevent proper SPI flash
> writing (not sure about reading).
>
Sorr
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/include/asm/mrccache.h | 11 ++
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/intel_common/Makefile | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/int
This is again too small, so increase it slightly.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
configs/chromebook_samus_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/chromebook_samus_defconfig
b/configs/chromebook_samus_defc
There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
doc/README.x86 | 14 ++
1 file changed, 14 inse
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if need
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/intel_common/Makefile | 6 ++
arch/x86/cpu/intel_common/cpu_from_spl.c | 27 +
Implement this ioctl() to support power off.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to implement PCH_REQ_PMBASE_INFO on ivybridge
arch/x86/cpu/ivybridge/bd82x6x.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch
On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to implement power-off if available
drivers/sysreset/sysreset_x86.c | 82
The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.
Separate
Add a new ioctl() request to read information about the power-management
system. This can be used to power off the device.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to add an ioctl to read power-management info
include/pch.h | 18 ++
1 file changed, 18 inser
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/include/asm/spl.h| 17 -
arch/x86/lib/Makefile | 9 ++-
arch/x86/li
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add a new patch allowing jumping from TPL to SPL
arch/x86/cpu/start.S | 13 +
1 file changed, 13 insertions(+)
diff --git a/arc
When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/pci/pci_rom.c | 2 +-
1 file changed, 1 insertion(+), 1 del
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/bootm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/x86/dts/u-boot.dtsi | 26 --
1 file changed, 24 insertion
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 22 +-
1 file changed, 21 insertions(+), 1 deletio
Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Sort defconfig and adjust it t
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2:
- Update the comment in fsp_cap.S too
arch/x86/cpu/intel_common/car.S | 2 +-
arch/x86/lib/fsp/fsp_car.S | 2 +-
2 files changed,
The memory map currently omits the environment and the MRC region. Add
these in for completeness.
Signed-off-by: Simon Glass
---
Changes in v2: None
doc/README.x86 | 2 ++
1 file changed, 2 insertions(+)
diff --git a/doc/README.x86 b/doc/README.x86
index d5224b75367..8e0a3f36edf 100644
--- a/
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
Makefile | 1 +
arch/x86/Makefile | 4 ++--
arch/x
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add a new patch to update PCH to work in TPL
arch/x86/cpu/broadwell/pch.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
With the move to Kconfig this option should be set in Kconfig, not in the
config header file. Move it.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to enable the RTC in Kconfig
arch/Kconfig | 1 +
configs/chromebook_link_defconfig | 1 +
include/configs/x8
Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.
Signed-off-by: Simon Glass
---
Changes in v2: None
drivers/sysreset/sysreset_
Add debugging during SDRAM init so that problems are easier to
diagnose.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/broadwell/sdram.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/arch/x86/cpu/
At present only chromebook_link64 supports SPL. It is useful to eb able to
support both TPL and SPL to implement verified boot on x86.
Enable the options for both along with some suitable default options
needed to boot through these phases.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/init_helpers.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/lib/init_helpers.c b/a
This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d.
Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.
The offending line is in UCLASS_DRIVER(
Add labels for these nodes so that board DT files can reference them.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/dts/reset.dtsi | 2 +-
arch/x86/dts/rtc.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/reset.dtsi
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/broadwell/Makefile | 15 +++
When a previous phase of U-Boot has run we need to adjust the init of
subsequent states to avoid messing up the CPU state.
Add a new version of the start logic for SPL, when it boots from TPL
(start_from tpl.c) and a new version for U-Boot when it boots from SPL.
Signed-off-by: Simon Glass
---
This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.
Also drop the unnecessary extra newline on this message, which causes two
line breaks.
Signed-off-by: Simon Glass
---
Cha
Add an arch-specific handoff header so that we can use the HANDOFF feature
on x86 devices.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/include/asm/handoff.h | 15 +++
1 file changed, 15 insertions(+)
create mode 100644 arch/x86/include/asm/ha
Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.
This allows device-tree aliases to be used to refer to cros-ec devices,
for example:
aliases {
cros-ec0 = &ec;
cros-ec1 = &pd;
};
Signed-
Add tags to allow required nodes to be present in SPL / TPL. Also enable
the sysreset driver.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 38 +++
1 file changed, 34 insertions(+), 4 deletions(-)
diff
Allow broadwell to build for SPL and include the reference code.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/broadwell/Makefile | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/broadwell/Makefile b/arch/x86/cpu/b
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/bro
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/lib/mrccache.c | 16
1 file changed, 12 insertions(+), 4 delet
Implement this ioctl() to support power off.
Signed-off-by: Simon Glass
---
Changes in v2:
- Add new patch to implement PCH_REQ_PMBASE_INFO on broadwell
arch/x86/cpu/broadwell/pch.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/arch/x86/cpu/broadwell/pch.c b/ar
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.
Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to red
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/broadwell/Makefile | 1 +
arch/x86/cpu/broadwell/c
There is a typo in this header. Fix it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/start64.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S
index a78a3316b6d..7be834788b9 100644
---
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/i386/c
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/dts/u-boot.dtsi | 147 +++
1 file changed, 73 insertions(+), 74 deletions(-)
diff --git a/a
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.
Add a new Kconfig option for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/Kconfig | 9 ++
Update the condition to translate only if this is enabled for SPL.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
drivers/core/ofnode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 785f5c3acf7
It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.
Move the exception to where the data is actually used.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in
An important property is missing. Update the entry comment to include
this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
tools/binman/etype/vblock.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/binman/etype/vblock.py b/tools/binman/etype/vblock.py
ind
At present many of the functions in this file return -1 as an error
number. which is -EPERM. Update the code to use real error numbers.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/mp_init.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions
At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.
Signed-off-by: Simon Glass
---
Changes in v2:
- Fix map output when section offset is not set (make it 0)
- Add a test for sections wit
Hi Jagan,
On Thu, 25 Apr 2019 at 11:54, Jagan Teki wrote:
>
> Rockchip platform would require an explicit call to mkimage for
> creating bootable images which indeed specific to SoC family
> along with boot devices.
>
> Example of creating bootable image for rk3399 family with SD
> boot device as
At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.
Note that the new logic is not quite the same as the old logic. It was
previously assumed that checkin
Hi Bin,
On Fri, 22 Feb 2019 at 00:20, Bin Meng wrote:
>
> Hi Simon,
>
> On Wed, Jan 30, 2019 at 12:01 PM Simon Glass wrote:
> >
> > Add a default implementation of this method which always indicates that
> > the last reset was a power-on reset. This is the most likely type of reset
> > and witho
At present SPL is used on 64-bit platforms, to allow SPL to be built as
a 32-bit program and U-Boot proper to be built as 64-bit.
However it is useful to be able to use SPL on any x86 platform, where
U-Boot needs to be updated in the field. Then SPL can select which U-Boot
to run (A or B) and most
On 25/04/19 10:59 PM, Andreas Dannenberg wrote:
> Transition to the IOPAD macros as used in Linux in which the pin mux
> mode is specified using a dedicated parameter while also dropping the
> related MUX_MODEx macros that are no longer needed. This transition
> will allow us to keep both Linux a
On 25/04/19 10:57 PM, Andreas Dannenberg wrote:
> Switch from using the high priority DMSC transmit message queue used
> by the secure R5 MCU island boot context to the low priority message
> queue. While the change in priority is irrelevant for the current boot
> architecture it however gives us
In certain i.MX devices the encrypted boot image is failing to boot.
According to AN12056 "Encrypted Boot on HABv4 and CAAM Enabled Devices"
it's necessary to pad CSF to 0x2000 and append DEK blob.
In this case the total image size in boot data structure must cover the
entire binary otherwise the
> Subject: [PATCH v3 11/11] clk: Port Linux common clock framework [CCF] for
> imx6q to U-boot (tag: 5.0-rc3)
>
> This commit brings the files from Linux kernel to provide clocks support as
> it is
> used on the Linux kernel with common clock framework [CCF] setup.
>
> The directory structure ha
> Subject: [PATCH v3 08/11] dm: clk: Define clk_get_by_id() for clk operations
>
> This commit adds the clk_get_by_id() function, which is responsible for
> getting
> the udevice with matching clk->id. Such approach allows re-usage of inherit
> DM list relationship for the same class (UCLASS_CLK
> Subject: [PATCH v3 07/11] dm: clk: Define clk_get_parent_rate() for clk
> operations
>
> This commit adds the clk_get_parent_rate() function, which is responsible for
> getting the rate of parent clock.
> Unfortunately, u-boot's DM support for getting parent is different (the parent
> relationsh
> Subject: [PATCH v3 06/11] dm: clk: Define clk_get_parent() for clk operations
>
> This commit adds the clk_get_parent() function, which is responsible for
> getting the parent's struct clock pointer.
>
> U-boot's DM support for getting parent is different (the parent relationship
> is
> in ude
> Subject: [PATCH v3 05/11] clk: Provide struct clk for fixed rate clock
> (clk_fixed_rate.c)
>
> Up till now the fixed rate clock ('osc') has been added to UCLASS_CLK without
> declaring struct clk. As a result it was only accessible by iterating the
> udevice's uclass list.
>
> This is a proble
Hi Lukasz,
> Subject: [PATCH v3 04/11] clk: Extend struct clk to provide information
> regarding clock rate
>
> This commit extends the struct clk to provide information regarding the clock
> rate.
> As a result the clock tree traversal is performed at most once, and further
> reads are using the
> Subject: [PATCH v3 03/11] clk: Remove clock ID check in .get_rate() of
> clk_fixed_*
>
> This check requires the struct clk passed to .get_rate() to be always cleared
> out as any clock with valid ID causes -EINVAL return value.
>
> The return code of fixed clocks shall always be returned.
>
> Subject: [PATCH v3 01/11] dm: Fix documentation entry as there is no
> UCLASS_CLOCK uclass
>
> There is no UCLASS_CLOCK uclass defined. Instead we do use the
> UCLASS_CLK.
>
> Signed-off-by: Lukasz Majewski
> Reviewed-by: Simon Glass
> ---
>
> Changes in v3: None
>
> include/clk.h | 2 +-
>
> Subject: [PATCH v3 02/11] cmd: Do not show frequency for clocks
> which .get_rate() return error
>
> It may happen that some UCLASS_CLK clocks drivers work as a "managers", to
> call other, proper clocks. This situation is present in the iMX{6|8} clocks
> when
> supporting CONFIG_CLK (and CCF).
Hi Stefano,
> Subject: Re: [PATCH v2 5/5] board: toradex: add colibri imx8qxp 2gb wb it
> v1.0b module support
>
> Hi Marcel,
>
> On 25/04/19 14:35, Marcel Ziswiler wrote:
> > Hi Stefano
> >
> > On Thu, 2019-04-25 at 12:48 +0200, Stefano Babic wrote:
> >> Hi Marcel,
> >>
> >> On 09/04/19 17:25,
Read the temperature when print cpu inforation.
Signed-off-by: Peng Fan
---
V2:
Fix build warning when CONFIG_IMX_SCU_THERMAL not defined.
Hi Stefano,
I not post the whole series, not posted out this specific patch,
the v1 patch https://patchwork.ozlabs.org/patch/1084464/
or do you expect th
On 4/25/19 9:56 PM, Atish Patra wrote:
> Add gz parsing logic so that booti can parse both Image
> and Image.gz.
>
> Signed-off-by: Atish Patra
> ---
> arch/riscv/lib/image.c | 28 +++-
> 1 file changed, 27 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/lib/ima
Hi Ramon,
On Thu, 25 Apr 2019 at 05:35, Ramon Fried wrote:
>
> On Thu, Apr 25, 2019 at 2:29 AM Simon Glass wrote:
> >
> > Hi Ramon,
> >
> > On Wed, 24 Apr 2019 at 12:54, Ramon Fried wrote:
> >
> > Please add a commit message.
> >
> > >
> > > Signed-off-by: Ramon Fried
> > > ---
> > >
> > > ar
Hi Heiko,
On Thu, 25 Apr 2019 at 03:00, Heiko Stuebner wrote:
>
> Hi Simon,
>
> Am Donnerstag, 25. April 2019, 00:26:28 CEST schrieb Simon Glass:
> > On Thu, 18 Apr 2019 at 10:47, Heiko Stübner wrote:
> > >
> > > Am Donnerstag, 18. April 2019, 08:35:49 CEST schrieb Philipp Tomsich:
> > > > Simon
Currently in do_efi_boot_dump(), we directly read EFI variables from
related environment variables. To accommodate alternative storage
backends, we should switch to using the UEFI API instead.
Signed-off-by: AKASHI Takahiro
---
cmd/efidebug.c | 79 +++-
This patch is a spin-off from my "non-volatile support" patch[1].
[1] https://lists.denx.de/pipermail/u-boot/2019-April/366214.html
Changes (Apr 26, 2019)
* use memcmp() instead of u16_strncmp()
* merge u16_isxdigit() and u16_tohex() into one function
AKASHI Takahiro (1):
cmd: efidebug: rework
Hi Bin,
I find that 'sf test 0 1000' does not work anymore since this commit:
c4e8862308 mtd: spi: Switch to new SPI NOR framework
Have you seen any problems? This seems to prevent proper SPI flash writing
(not sure about reading).
Also, it seemed to increase code size on samus by >2KB.
Regard
On 4/25/19 1:36 PM, Eugeniu Rosca wrote:
Hi Roman,
...
On Thu, Apr 25, 2019 at 02:18:22PM +0300, roman.stratiie...@globallogic.com
wrote:
From: Roman Stratiienko
This allows retrieving uuid of the partition using it's name.
IMHO not seeing any real-life motivation (backed up by use-cases
On 4/25/19 9:22 PM, Simon Goldschmidt wrote:
> If the malloc range passed to mem_malloc_init() is at the end of address
> range and 'start + size' overflows to 0, following allocations fail as
> mem_malloc_end is zero (which looks like uninitialized).
>
> Fix this by subtracting 1 of 'start + size
Hi Bryan,
Em ter, 23 de abr de 2019 às 07:20, Bryan O'Donoghue
escreveu:
>
> We need to handle the case where DEK blobs are passed to the BootROM. In
> this case, unlike in HAB authentication the BootROM checks job-ring
> ownership set to secure world.
>
> One possible solution is to set the job-
On 17. 04. 19 19:46, Philip Balister wrote:
> Signed-off-by: Philip Balister
> ---
> configs/zynq_minized_defconfig | 16 +---
> 1 file changed, 5 insertions(+), 11 deletions(-)
>
> diff --git a/configs/zynq_minized_defconfig b/configs/zynq_minized_defconfig
> index d61659f785..6c56b
On 17. 04. 19 19:46, Philip Balister wrote:
> Signed-off-by: Philip Balister
> ---
> include/configs/zynq_minized.h | 54 ++
> 1 file changed, 54 insertions(+)
> create mode 100644 include/configs/zynq_minized.h
>
> diff --git a/include/configs/zynq_minized.h b/i
On 17. 04. 19 19:46, Philip Balister wrote:
> Signed-off-by: Philip Balister
> ---
> arch/arm/dts/zynq-minized.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/zynq-minized.dts b/arch/arm/dts/zynq-minized.dts
> index 525921ee7b..9ad7f090fe 100644
> --- a/arch/arm/dts/zyn
In the UEFI context GUIDs are expected to be rendered in upper case.
The patch uses the formerly unused bit 1 of the parameter str_format
of function uuid_bin_to_str() to indicate if we need upper or lower case
output.
Function uuid_string() in vsprint.c is adjusted to correctly set the bit
depen
On 19. 04. 19 6:38, Alex Kiernan wrote:
> This converts the following to Kconfig:
>CONFIG_SUPPORT_EMMC_BOOT
>
> Signed-off-by: Alex Kiernan
> ---
> Green travis build:
>
> https://travis-ci.org/akiernan/u-boot/builds/521906850
>
> Testing affected boards for configuration changes:
>
> bo
On Thu, 2019-04-25 at 09:00 +0800, Rick Chen wrote:
> Bin Meng 於 2019年4月24日 週三 下午3:02寫道：
> > On Wed, Apr 24, 2019 at 2:38 PM Andes wrote:
> > > From: Rick Chen
> > >
> > > This patch will fix prior_stage_fdt_address write failure problem, when
> > > AE350 was booting from flash.
> >
> > was ->
On Wed, 2019-04-24 at 14:33 +0800, Andes wrote:
> From: Rick Chen
>
> When AE350 was booting from ram, use CONFIG_OF_PRIOR_STAGE instead
> of CONFIG_OF_BOARD.
>
> Signed-off-by: Rick Chen
> Cc: Greentime Hu
> ---
> configs/ae350_rv32_defconfig | 2 +-
> configs/ae350_rv64_defconfig | 2 +-
>
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