Hi Tom,
I have been meaning to have a crack at setting up a little hardware
lab for a while.
I made some progress recently and hooked up a rpi_3 with sdwire for
USB/SD, ykush for power and a little computer to control it. It builds
U-Boot, sticks it on the SD card and runs pytest.
I pushed a
On Sat, Nov 23, 2019 at 11:59 AM Andre Przywara wrote:
>
> Commit b618b3707633 ("net: Convert CONFIG_TFTP_BLOCKSIZE to Kconfig")
> accidentally set the default *option* TFTP block size to 512 bytes, even
> though the comment in the code says that this is a terrible choice. Most
> boards didn't
On Thu, Nov 28, 2019 at 6:37 AM Cédric Le Goater wrote:
>
> Fixes: e766849713ff ("net: ftgmac100: convert the RX/TX descriptor arrays")
> Signed-off-by: Cédric Le Goater
Acked-by: Joe Hershberger
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On Wed, Oct 23, 2019 at 5:47 AM wrote:
>
> From: Nicolas Ferre
>
> The KSZ8081 PHY has a factory test mode which is set at the de-assertion
> of the reset line based on the RXER (KSZ8081RNA/RND) or TXC
> (KSZ8081MNX/RNB) pin. If a pull-down is missing, or if the pin has a
> pull-up, the factory
On Mon, Oct 14, 2019 at 9:27 AM Florin Chiculita
wrote:
>
> Aquantia quad-phys may take longer to initialize. This commit adds
> a polling mechanism for a global alarm bit that tells if phy init
> sequence is completed.
>
> Signed-off-by: Florin Chiculita
Acked-by: Joe Hershberger
> ---
>
On Fri, Oct 25, 2019 at 7:29 PM Michael Walle wrote:
>
> The two functions are now exactly the same, remove one of them.
>
> Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
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On Fri, Oct 25, 2019 at 7:29 PM Michael Walle wrote:
>
> We can configure the clock output in the device tree. Disable the
> hardcoded one in here. This is highly board-specific and should have
> never been enabled in the PHY driver.
>
> If bisecting shows that this commit breaks your board it
On Fri, Oct 25, 2019 at 7:29 PM Michael Walle wrote:
>
> Add support for configuring the CLK_25M pin as well as the RGMII I/O
> voltage by the device tree.
>
> By default the AT803x PHYs outputs the 25MHz clock of the XTAL input.
> But this output can also be changed by software to other
On Fri, Oct 25, 2019 at 7:30 PM Michael Walle wrote:
>
> The delay_config() code could only set the delay bit. Thus, it could
> only enable the delay mode, but not disable it. To make things worse,
> the RX delay mode is enabled by default after a hardware reset, so it
> could never be disabled.
On Fri, Oct 25, 2019 at 7:31 PM Michael Walle wrote:
>
> Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
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On Fri, Oct 25, 2019 at 7:30 PM Michael Walle wrote:
>
> Instead of doing a hard write, do a read-modify-write.
>
> Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
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On Fri, Oct 25, 2019 at 7:29 PM Michael Walle wrote:
>
> Remove the hard-coded delay configuration. The AR8035 config() always
> enabled the TX delay mode, although it will be set according to the PHY
> interface mode, too.
>
> If bisecting shows that this commit breaks your board you probably
On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
>
> Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
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On Fri, Oct 25, 2019 at 7:28 PM Michael Walle wrote:
>
> Provide functions to read and write the Atheros debug registers.
>
> Signed-off-by: Michael Walle
Acked-by: Joe Hershberger
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On Sun, Oct 27, 2019 at 3:38 PM Michael Walle wrote:
>
> The network driver has to set the PHY node correctly. If that is not the
> case, ar803x_of_init() will fail. Add some debugging output.
>
> If the device tree binding is not working for you have a look at the
> ar803x_of_init: found PHY
On Mon, Oct 21, 2019 at 6:03 PM Michael Walle wrote:
>
> device_probe() may fail in which case the seq_id will be -1. Don't
> display these devices during startup. While this is only a cosmetic
> change, the return value of eth_initialize() will also change to the
> actual number of available
On Wed, Oct 2, 2019 at 2:46 PM Josef Holzmayr
wrote:
>
> This allows passing arbitrary addresses through macb_miiphy_read and
> macb_miiphy_write, therefore enabling the mii command to access
> all mdio bus devices instead of only the defined phy.
>
> Signed-off-by: Josef Holzmayr
Acked-by: Joe
On Wed, Oct 2, 2019 at 2:47 PM Josef Holzmayr
wrote:
>
> To support accessing arbitrary addresses the mii/mdio bus it is
> neccesary that the macb_mdio_read and macb_mdio_write functions
> do not implicitly use the address of the connected phy.
>
> The function signature is extended according to
On Mon, Sep 30, 2019 at 3:33 AM Stefan Roese wrote:
>
> I've noticed that in most cases when genphy_update_link() is called, the
> ethernet driver (mt7628-eth in this case) fails with the first ethernet
> packets. Resulting in a timeout of the first tftp command. Increasing
> the delay in the
On Wed, Sep 11, 2019 at 12:19 PM Thierry Reding
wrote:
>
> From: Thierry Reding
>
> This version of the RTL-8168 chip can be found on some add-in cards sold
> by CSL-Computer GmbH & Co. KG. The chip isn't special in any way, but it
> needs to have the ChipCmd register programmed after the DMA
On Thu, Aug 15, 2019 at 5:09 PM wrote:
>
> From: Nevo Hed
>
> Changes to mvpp2.c require the MVMDIO module which in turn uses
> DM_MDIO.
>
> Signed-off-by: Nevo Hed
Acked-by: Joe Hershberger
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On Thu, Aug 15, 2019 at 5:09 PM wrote:
>
> From: Nevo Hed
>
> This commit ports mvpp2 to use the recently introduced Marvell MDIO
> (MVMDIO) driver. It removes direct interaction with the SMI & XSMI
> busses. This commit is based in part on earlier work by
> Ken Ma in Marvell's own downstream
On Thu, Aug 15, 2019 at 5:09 PM wrote:
>
> From: Nevo Hed
>
> Based on upstream-linux
> See https://github.com/torvalds/linux/commit/f66b2aff.
>
> However made the XSMI register window 0x16 (22) bytes per my reading
> of the functional spec. Similar commits in Marvels own repo bump it
> to
On Thu, Aug 15, 2019 at 5:09 PM wrote:
>
> From: Grzegorz Jaszczyk
>
> If the phy doesn't match with any existing u-boot drivers, the phy
> framework will connect it to the generic one which uid ==
> 0x. In this case, act as if the phy wouldn't be declared in
> dts. Otherwise, in case of
On Thu, Aug 15, 2019 at 5:09 PM wrote:
>
> From: Stefan Chulski
>
> Issue:
> - Network stuck if autonegotion fails.
>
> Issue root cause:
>
> - When autonegotiation fails during port open procedure, the packet
> processor configuration does not finish and open procedure exits
> with error.
>
Hi Alex,
On Mon, Nov 25, 2019 at 9:54 AM Alex Marginean
wrote:
>
> DSA stands for Distributed Switch Architecture and it covers switches that
> are connected to the CPU through an Ethernet link and generally use frame
> tags to pass information about the source/destination ports to/from CPU.
>
On Mon, Nov 25, 2019 at 9:58 AM Alex Marginean
wrote:
>
> This bus is used to access internal SoC PHYs. These PHYs are configured
> by the ENETC driver directly, but it's useful to have command line access
> to this MDIO to debug the system especially when using new external PHYs.
>
>
On Thu, Nov 14, 2019 at 10:59 AM Alex Marginean
wrote:
>
> On some boards MDIO may get stuck if it detects echo on the line. This is
> a know hardware issue, there is a board fix for it. In case we're running
> on a board that doesn't have the fix, we don't want to loop here forever
> and
On Thu, Nov 14, 2019 at 10:59 AM Alex Marginean
wrote:
>
> The original code enabled link speeds up to 1Gbps, but the interface can
> go up to 2.5G, enable that speed to in PHY AN mask.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
___
On Thu, Nov 14, 2019 at 10:59 AM Alex Marginean
wrote:
>
> This reduces the time needed to establish a link as we don't reset the link
> each time the interface is used. Our Link capabilities do not change at
> run-time so there is no need to re-apply PHY configuration each time.
>
>
On Thu, Nov 14, 2019 at 10:31 AM Alex Marginean
wrote:
>
> Apply 10G PCS init for USXGMII, XFI interface types.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
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On Thu, Nov 14, 2019 at 10:34 AM Alex Marginean
wrote:
>
> A couple of optional properties have been introduced for Aquantia PHY
> allowing the driver to set up wiring related configuration points that
> are otherwise driven by firmware.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe
On Thu, Nov 14, 2019 at 10:33 AM Alex Marginean
wrote:
>
> It defines that PHY nodes must be children on MDIO bus nodes and defines
> the only required property in U-Boot, reg. This property along with the
> example provided are copied over from Linux.
>
> Signed-off-by: Alex Marginean
On Thu, Nov 14, 2019 at 10:32 AM Alex Marginean
wrote:
>
> In some cases the link on the system interface of the aquantia PHY comes up
> after the link on line interface. The link state loop only checks the line
> side, which may result in first packet sent being lost.
> Use aquantia_link_is_up
On Thu, Nov 14, 2019 at 10:31 AM Alex Marginean
wrote:
>
> Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
> on this interface are normally set up by PHY firmware, but depending on the
> board they may end up not being unique. Add an optional DT property used
> to
On Thu, Nov 14, 2019 at 10:34 AM Alex Marginean
wrote:
>
> MDI pins up to the RJ45 connector may be reversed on the board and the
> default PHY configuration applied by firmware may or may not match that.
> Add an optional DT property to configure MDI reversal for this case.
>
> Signed-off-by:
On Thu, Nov 14, 2019 at 10:33 AM Alex Marginean
wrote:
>
> If PHY is not ready for data by the time _config is called, reconfigure the
> PHY system interface to use the proper protocol based on phydev->interface,
> just in case the defaults set by PHY firmware don't match current
> configuration.
On Thu, Nov 14, 2019 at 10:32 AM Alex Marginean
wrote:
>
> Uses the data field in phy_driver structure to identify the PHY generation.
> This is useful for custom configuration as non-generic PHY registers are
> not 100% compatible between generations.
>
> Signed-off-by: Alex Marginean
On Thu, Nov 14, 2019 at 10:35 AM Alex Marginean
wrote:
>
> The PHY supports XFI and USXGMII, the notable difference being that USX AN
> is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
> detects whether USX AN should be enabled or not using a PHY status
> register. Keep that
On Thu, Nov 14, 2019 at 10:30 AM Alex Marginean
wrote:
>
> This is useful to carry custom information between the driver structure
> associated with a specific HW and the driver code.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
___
On Thu, Nov 14, 2019 at 10:31 AM Alex Marginean
wrote:
>
> Drivers currently use XGMII for XFI and USXGMII and, where needed, use
> other information to identify the actual protocol on the board. With these
> two defined drivers can now rely on DT phy-mode property.
>
> Signed-off-by: Alex
On Mon, Nov 25, 2019 at 9:17 AM Alex Marginean
wrote:
>
> Uses the new dm_eth_phy_connect helper to connect to the PHY to simplify
> the code.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
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On Mon, Nov 25, 2019 at 9:17 AM Alex Marginean
wrote:
>
> The function connects an ethernet device to a PHY using DT information.
> This API is only available for eth devices with an associated device tree
> node.
>
> Signed-off-by: Alex Marginean
Acked-by: Joe Hershberger
On Mon, Nov 25, 2019 at 9:17 AM Alex Marginean
wrote:
>
> Renamed dm_mdio_phy_connect arguments dev to mdiodev and addr to phyaddr
> for a bit more clarity and consistency with the following patches.
> Also use NULL instead of 0 on error return path.
>
> Signed-off-by: Alex Marginean
Acked-by:
On 11/30/19 12:25 AM, Lukasz Majewski wrote:
> Dear Marek,
Hi,
> The following changes since commit
> dbcbdad92caf4b42a6279da6e65180532bc45620:
>
> sandbox: enable USB_KEYBOARD_FN_KEYS (2019-11-25 13:28:53 +0100)
>
> are available in the Git repository at:
>
>
Dear Marek,
The following changes since commit
dbcbdad92caf4b42a6279da6e65180532bc45620:
sandbox: enable USB_KEYBOARD_FN_KEYS (2019-11-25 13:28:53 +0100)
are available in the Git repository at:
g...@gitlab.denx.de:u-boot/custodians/u-boot-dfu.git
BRANCH: master
On Fri, Nov 29, 2019 at 09:29:51PM +0100, Simon Goldschmidt wrote:
>
> [bringing this back to the list, seems like I accidentally hit the single
> reply button before]
>
> On 29.11.19 21:02, Andy Shevchenko wrote:
> > On Fri, Nov 29, 2019 at 06:56:44PM +0100, Simon Goldschmidt wrote:
> > > Andy
[bringing this back to the list, seems like I accidentally hit the
single reply button before]
On 29.11.19 21:02, Andy Shevchenko wrote:
On Fri, Nov 29, 2019 at 06:56:44PM +0100, Simon Goldschmidt wrote:
Andy Shevchenko schrieb am Fr., 29.
Nov. 2019, 18:48:
GCC 9.x starts complaining
Currently, it is only possible to get the ${index}'s entry of a DTB/DTBO
image [*]. The "dtimg" command is agnostic on the "id" and "rev" fields
and is unable to take them as input for a more fine-grained DTB/DTBO
search/retrieval.
This is a major limitation, as users would like [**] to employ
Unlike dtimg, U-Boot commands like part [1], fstype [2] and uuid [3]
accept an _optional_ parameter, which means that they will
output the result to console whenever is skipped. This is
extremely useful during development.
Allow "dtimg" to behave in a similar fashion [4]. In addition:
-
Getting DTB/DTBO header address happens twice (in do_dtimg_dump and
in dtimg_get_fdt) with duplicating below error messages:
- Error: Wrong image address
- Error: DT image header is incorrect
Reduce the duplication and improve the error message by appending
the faulty address value:
- Error:
Being user-friendly is paramount to make any product likeable and
easy to use. Hence, instead of [1], print [2].
[1] dtimg start 0x4800 not-a-number myvar
Error: Wrong index
[2] dtimg start 0x4800 not-a-number myvar
Error: Wrong index 'not-a-number'
Signed-off-by: Eugeniu Rosca
---
Dear U-Boot community,
As summarized in the title, the motivation behind the series is to
primarly allow the Android "dtimg" command (credits to Sam for having
it) to actually leverage the specification described in [*].
There are a few collateral improvements and optimizations added as well.
On Fri, Nov 29, 2019 at 07:47:59PM +0200, Andy Shevchenko wrote:
> GCC 9.x starts complaining about potential misalignment of the pointer to
> the array (in this case alignment=2) in the packed (alignment=1) structures.
>
> Repeating Linus' Torvalds commit 6f303d60534c in the Linux kernel.
>
>
On 11/29/19 11:16 AM, Michal Simek wrote:
Hi,
I tried to boot latest debian and fedora rootfs via distro boot and
getting errors.
I have tried to run just one command and it is failing.
ZynqMP> bootefi bootmgr ${fdtcontroladdr}
BootOrder not defined
EFI boot manager: Cannot load any image
How
GCC 9.x starts complaining about potential misalignment of the pointer to
the array (in this case alignment=2) in the packed (alignment=1) structures.
Repeating Linus' Torvalds commit 6f303d60534c in the Linux kernel.
Original commit message:
We already did this for clang, but now gcc has
I've done some more digging, and have made a bit of progress (I think).
After fiddling with the device-tree, I've managed to get the serial port to
show up when running `dm tree`. I appended this block to the end of
bcm2835-rpi-b.dts:
{
pinctrl-names = "default";
pinctrl-0 =
From: Heiko Stuebner
serial# is one of the vendor properties and thus protected from being
overwritten if already set. If env_set is called anyway this result in
some nasty warnings, so check for presence before trying that.
In the same direction check for the presence of cpuid# and compare it
From: Heiko Stuebner
rockchip_setup_macaddr() runs from an initcall, so returning an error
code will make that initcall fail thus breaking the boot process.
And if an ethernet address is already set this is definitly not a
cause for that, so just return success in that case.
Fixes:
On Fri, Nov 29, 2019 at 06:46:40AM +, Priyanka Jain wrote:
>
>
> >-Original Message-
> >From: U-Boot-Custodians On
> >Behalf Of Heinrich Schuchardt
> >Sent: Tuesday, November 26, 2019 4:46 AM
> >To: u-boot-custodi...@lists.denx.de; u-boot-board-
> >maintain...@lists.denx.de; U-Boot
Hi,
I'm trying to run mainline u-boot on amlogic a96mini device but before
I try to flash it does anybody have an idea if it will work on
mainline. As I have limited number of devices and I know that after
flashing I can brick the board so would like to ask if anybody have
experience with this
Hi,
I tried to boot latest debian and fedora rootfs via distro boot and
getting errors.
I have tried to run just one command and it is failing.
ZynqMP> bootefi bootmgr ${fdtcontroladdr}
BootOrder not defined
EFI boot manager: Cannot load any image
How to define BootOrder?
Thanks,
Michal
--
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1043A
Signed-off-by: Biwen Li
---
Changes in v2:
- merge some patches to one patch
arch/arm/include/asm/gpio.h | 2 +-
board/freescale/ls1043aqds/ls1043aqds.c | 97 +--
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1012A
Signed-off-by: Biwen Li
---
Changes in v2:
- merge some patches to one patch
arch/arm/include/asm/gpio.h | 1 +
board/freescale/ls1012aqds/ls1012aqds.c | 20 ++-
board/freescale/ls1012ardb/eth.c
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1046A
Signed-off-by: Biwen Li
---
Changes in v2:
- merge some patches to one patch
arch/arm/dts/fsl-ls1046a-frwy.dts | 3 ++
arch/arm/dts/fsl-ls1046a-qds.dtsi | 4 ++
arch/arm/dts/fsl-ls1046a-rdb.dts
This is used to fix build error
as follows:
- arch/arm/cpu/armv8/built-in.o: In function `board_init_f:
arch/arm/cpu/armv8/fsl-layerscape/spl.c:74: undefined reference to
`i2c_init_all'
arch/arm/cpu/armv8/fsl-layerscape/spl.c:74:(.text.board_init_f+0x30):
relocation truncated to fit:
This supports i2c DM and enables CONFIG_DM_I2C
for SoC LS1021A
Signed-off-by: Biwen Li
---
Changes in v2:
- merge some patches to one patch
board/freescale/common/dcu_sii9022a.c | 94 +++
board/freescale/common/diu_ch7301.c | 79
The default value of CONFIG_SYS_MALLOC_F_LEN (0x400)
leaves U-Boot with not enough memory to do this,
causing it to hang.
Fix this problem by providing a convenient default value
for CONFIG_SYS_MALLOC_F_LEN.
Relative SoC:
- LS1012A
- LS1021A
- LS1043A
- LS1046A
Signed-off-by: Biwen Li
---
This adds DM_FLAG_PRE_RELOC flag to probe i2c driver
before relocation
Signed-off-by: Biwen Li
---
Changes in v2:
- none
drivers/i2c/mxc_i2c.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index 786b5a2226..6b7ce985b3 100644
---
This supports driver model to
drop warning as follows:
- drivers/rtc/pcf8563.c: In function rtc_read:
drivers/rtc/pcf8563.c:111:10: warning: implicit declaration of function
i2c_reg_read; did you mean dm_i2c_reg_read? [-Wimplicit-function-declaration
drivers/rtc/pcf8563.c: In function
Hi Robert,
On 28/11/2019 17.17, Robert Hancock wrote:
> On 2019-11-28 6:34 a.m., Harald Seiler wrote:
>> Hello Claudius,
>>
>> On Thu, 2019-11-28 at 13:06 +0100, Claudius Heine wrote:
>>> Hi,
>>>
>>> currently the reset on the DHCOM i.MX6 board is brocken in u-boot.
>>>
>>> This patchset fixes
The SPL does not have DM enabled and therefor still needs to use the
hardware watchdog interface provided by the imx-watchdog driver.
Fixes: broken reset command after f2929d11a639 ("watchdog: imx: Use
immediate reset bits for expire_now")
Signed-off-by: Claudius Heine
---
Hi,
here the second version of those patches.
regards,
Claudius
Changes from v1:
- u-boot specific wdt-reboot device node now in separate dtsi
- Squashed patch 2 to 4, because possible bisecting issues in certain
configurations (when SPL needs to use do_reset)
- Improved patch description:
The wdt-reboot node is needed for the sysreset_watchdog driver to
register a watchdog as a reset handler in case 'CONFIG_SYSRESET' is
enabled.
Signed-off-by: Claudius Heine
---
arch/arm/dts/imx6q-dhcom-pdk2-u-boot.dtsi | 11 +++
1 file changed, 11 insertions(+)
create mode 100644
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