[PATCH 1/1] doc: board: qemu-mips.rst: fix code examples

Code sections should be syntax highlighted as bash. Comment lines in code should start with a hash sign ('#') but code lines should not. Most commands can be executed as normal users. Prepend those commands requiring elevated authorization with 'sudo'. dd does not have a parameter cout. sfdisk

[PATCH 11/11] riscv: Add option to disable writes to mcounteren

On the kendryte k210, writes to mcounteren result in an illegal instruction exception. Signed-off-by: Sean Anderson --- arch/riscv/cpu/cpu.c| 2 ++ board/sipeed/maix/Kconfig | 1 + configs/sipeed_maix_bitm_config | 1 + 3 files changed, 4 insertions(+) diff --git

[PATCH 10/11] riscv: Add K210 clock support

Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. A common pattern is to create a composite clock composed of several component clocks. For these component clocks, the clk_register_* functions are not used, since they will be

[PATCH 09/11] riscv: Add K210 pll support

This pll code is primarily based on the code from the kendryte standalone sdk in lib/drivers/sysctl.c. k210_pll_calc_params is roughly analogous to the algorithm used to set the pll frequency, but it has been completely rewritten to be fixed-point based. Signed-off-by: Sean Anderson ---

[PATCH 08/11] riscv: Add K210 sysctl support

This driver does nothing but load its children for the moment. Should it be using regmap? I'm not sure how that fits into everything. Signed-off-by: Sean Anderson --- arch/riscv/Kconfig | 11 +++ arch/riscv/Makefile | 6

[PATCH 07/11] riscv: Add device tree for K210

There is a mirror of ram located at 0x400 which is un-cached. This is probably useful for DMA, but I am unsure of how to describe it in this device tree. The cache-line size is undocumented. Emphirical tests suggest that it is 32 bytes, but I've used 64-bytes to be on the safe side. Where

[PATCH 06/11] riscv: Add initial Sipeed Maix support

The Sipeed Maix series is a collection of boards built around the RISC-V Kendryte K210 processor. This processor contains several peripherals to accelerate neural network processing and other "ai" tasks. This includes a "KPU" neural network processor, an audio processor supporting beamforming

[PATCH 05/11] riscv: Enable SiFive UART support pre-relocation

Many other serial drivers are enabled pre-relocation to allow printing of console messages before relocating. This should also be enabled for the SiFive serial driver. Signed-off-by: Sean Anderson --- drivers/serial/serial_sifive.c | 1 + 1 file changed, 1 insertion(+) diff --git

[PATCH 04/11] riscv: Add an option to default to RV64I

This allows 64-bit boards to default to the 64-bit instruction set without changing the current default of 32-bit. Signed-off-by: Sean Anderson --- arch/riscv/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 85e15ebffa..9a7b0334c2

[PATCH 03/11] riscv: Add headers for asm/global_data.h

This header depended on bd_t and ulong, but did not include the appropriate headers. Signed-off-by: Sean Anderson --- arch/riscv/include/asm/global_data.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h index

[PATCH 02/11] clk: Check that ops of composite clock components exist, before calling

clk_composite_ops was shared between all devices in the composite clock driver. If one clock had a feature (such as supporting set_parent) which another clock did not, it could call a null pointer dereference. This patch does three things 1. It adds null-pointer checks to all composite clock

[PATCH 01/11] clk: Always use the supplied struct clk

CCF clocks should always use the struct clock passed to their methods for extracting the driver-specific clock information struct. Previously, many functions would use the clk->dev->priv if the device was bound. This could cause problems with composite clocks. The individual clocks in a composite

[PATCH 00/11] riscv: Add Sipeed Maix support

This patch series adds support for Sipeed Maix boards and the Kendryte K210 CPU. Currently, only the Maix Bit V2.0 is supported, however other models are similar. This series depends on and . (log: Include

Re: [PATCH] arm: dts: bcm283x: Allow UARTs to work before relocation

Hi Matthias, On Tue, 10 Dec 2019 at 02:43, Matthias Brugger wrote: > > Hi Simon, > > On 02/12/2019 16:45, Tom Rini wrote: > > On Sun, Dec 01, 2019 at 07:33:56PM -0700, Simon Glass wrote: > > > >> At present the pinctrl nodes are not enabled in pre-relocation U-Boot so > >> the UARTs do not

Re: [PATCH 3/3] riscv: sifive: fu540: add SPL configuration

Hi Pragnesh, Minor comments regarding coding style, see below. > + // Probably don't need to do this, since > + // all the other stuff has been happening. > + // But it is on the wave form. U-boot is mostly implemented in C, we should *not* use C++ style comments(//). is this

[PATCH] lib: ignore oid_registry_data.c file

The file is generated by scripts/build_OID_registry based on the include/linux/oid_registry.h file. Signed-off-by: Dario Binacchi --- lib/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 lib/.gitignore diff --git a/lib/.gitignore b/lib/.gitignore new file mode 100644 index

[PATCH] video: add wrappers for ttf type files to .gitignore

The scripts/Makefile.lib generates an assembler file (*.S) to wrap the font data for each file of type ttf defined in Kconfig. Signed-off-by: Dario Binacchi --- drivers/video/fonts/.gitignore | 1 + 1 file changed, 1 insertion(+) create mode 100644 drivers/video/fonts/.gitignore diff --git

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

On 12/31/19 4:49 PM, Sughosh Ganu wrote: On Tue, 31 Dec 2019 at 20:38, Heinrich Schuchardt mailto:xypron.g...@gmx.de>> wrote: On 12/31/19 2:31 PM, Sughosh Ganu wrote: > Scan the pci bus in board_init routine before scanning the virtio > devices. This enumerates all the virtio

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

On Tue, 31 Dec 2019 at 20:38, Heinrich Schuchardt wrote: > On 12/31/19 2:31 PM, Sughosh Ganu wrote: > > Scan the pci bus in board_init routine before scanning the virtio > > devices. This enumerates all the virtio devices, including devices > > found on the pci bus. > > > > Signed-off-by:

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

On Tue, Dec 31, 2019 at 11:18 PM Heinrich Schuchardt wrote: > > CC Bin Meng > > On 12/31/19 4:08 PM, Heinrich Schuchardt wrote: > > On 12/31/19 2:31 PM, Sughosh Ganu wrote: > >> Scan the pci bus in board_init routine before scanning the virtio > >> devices. This enumerates all the virtio devices,

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

CC Bin Meng On 12/31/19 4:08 PM, Heinrich Schuchardt wrote: > On 12/31/19 2:31 PM, Sughosh Ganu wrote: >> Scan the pci bus in board_init routine before scanning the virtio >> devices. This enumerates all the virtio devices, including devices >> found on the pci bus. >> >> Signed-off-by: Sughosh

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

On 12/31/19 2:31 PM, Sughosh Ganu wrote: > Scan the pci bus in board_init routine before scanning the virtio > devices. This enumerates all the virtio devices, including devices > found on the pci bus. > > Signed-off-by: Sughosh Ganu > --- > board/emulation/qemu-arm/qemu-arm.c | 7 +++ > 1

Re: [PATCH] qemu: arm: Scan the pci bus in board_init

On Tue, Dec 31, 2019 at 9:31 PM Sughosh Ganu wrote: > > Scan the pci bus in board_init routine before scanning the virtio > devices. This enumerates all the virtio devices, including devices > found on the pci bus. > > Signed-off-by: Sughosh Ganu > --- > board/emulation/qemu-arm/qemu-arm.c | 7

[PATCH 2/3] riscv: Add FU540 specific includes

Added headers needed by upcoming SPL support of FU540. This headers are leveraged from FSBL (https://github.com/sifive/freedom-u540-c000-bootloader.git) Signed-off-by: Pragnesh Patel --- arch/riscv/include/asm/arch-fu540/cache.h | 43 arch/riscv/include/asm/arch-fu540/clint.h | 20

[PATCH 0/3] RISC-V SiFive FU540 support SPL

This series add support for SPL to FU540. This series depends on https://patchwork.ozlabs.org/patch/1196703/ (riscv: dts: Add hifive-unleashed-a00 dts from Linux) U-Boot SPL can boot from L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and U-Boot proper from MMC devices. How to

[PATCH 1/3] riscv: Add place-holder for FU540 clk and gpio

Added FU540 place-holder so that SoC specific values will be kept here. Signed-off-by: Pragnesh Patel --- arch/riscv/include/asm/arch-fu540/clk.h| 14 arch/riscv/include/asm/arch-fu540/gpio.h | 42 ++ arch/riscv/include/asm/arch-generic/gpio.h | 32

[PATCH] qemu: arm: Scan the pci bus in board_init

Scan the pci bus in board_init routine before scanning the virtio devices. This enumerates all the virtio devices, including devices found on the pci bus. Signed-off-by: Sughosh Ganu --- board/emulation/qemu-arm/qemu-arm.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

Re: [PATCH v3 2/3] efi: qemu: arm64: Add efi_rng_protocol implementation for the platform

On Sat, 28 Dec 2019 at 21:09, Tuomas Tynkkynen wrote: > Hi, > > On Sat, 28 Dec 2019 at 17:19, Heinrich Schuchardt > wrote: > > > > On 12/28/19 4:03 PM, Sughosh Ganu wrote: > > > > > > On Sat, 28 Dec 2019 at 20:01, Heinrich Schuchardt > > > wrote: > > > > > > On

CONFIG_AUTOBOOT_KEYED_CTRLC default yes?

Hi, I have a pi4 running u-boot 2019.01. When I use the following config options ``` CONFIG_AUTOBOOT=y # CONFIG_AUTOBOOT_KEYED is not set ``` CTRL-C would continue to interrupt autoboot. Was quite surprised to see that. Took a look at the code.

Re: [PATCH v2 1/1] travis-ci: provide env__efi_fit_tftp_file

On Tue, Dec 31, 2019 at 12:42:36PM +0200, Cristian Ciocaltea wrote: > On Mon, Dec 30, 2019 at 09:03:38PM +0100, Heinrich Schuchardt wrote: > > On 12/30/19 8:32 PM, Stephen Warren wrote: > > > On 12/30/19 12:05 PM, Heinrich Schuchardt wrote: > > > > On 12/30/19 5:38 PM, Stephen Warren wrote: > > >

Re: [PATCH v2 1/1] travis-ci: provide env__efi_fit_tftp_file

On Mon, Dec 30, 2019 at 09:03:38PM +0100, Heinrich Schuchardt wrote: > On 12/30/19 8:32 PM, Stephen Warren wrote: > > On 12/30/19 12:05 PM, Heinrich Schuchardt wrote: > > > On 12/30/19 5:38 PM, Stephen Warren wrote: > > > > On 12/30/19 3:52 AM, Heinrich Schuchardt wrote: > > > > > Provide

[PATCH] arm: mach-k3: Enable WA for R5F deadlock

On K3 devices there are 2 conditions where R5F can deadlock: 1.When software is performing series of store operations to cacheable write back/write allocate memory region and later on software execute barrier operation (DSB or DMB). R5F may hang at the barrier instruction. 2.When software is

[PATCH] arm: dts: k3-j721e: ddr: Update to 0.2 version of DDR config tool

Update the ddr settings to use the DDR reg config tool rev 0.2.0. This reduces the aging count(in DDRSS_CTL_274_DATA reg) to 15 in-order to avoid DSS underflow errors. Signed-off-by: Lokesh Vutla Signed-off-by: Kevin Scholz --- arch/arm/dts/k3-j721e-ddr-evm-lp4-3733.dtsi | 6 +++--- 1 file

[PATCH 3/3] rockchip: evb-rk3328: Enable support ATF in SPL

Enable the ATF in SPL and adjust the SPL STACK/HEAD at the same time to support ATF entry at 0x4. Signed-off-by: Kever Yang --- configs/evb-rk3328_defconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig

[PATCH 2/3] rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc

Since mmc to sram can't do dma, add patch to prevent aborts transfering TF-A parts. Signed-off-by: Kever Yang --- arch/arm/dts/rk3328-u-boot.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/dts/rk3328-u-boot.dtsi b/arch/arm/dts/rk3328-u-boot.dtsi index

[PATCH 1/3] rockchip: rk3328: add COUNTER_FREQUENCY definition

The arch timer needs COUNTER_FREQUENCY to get correct counter, add it to make the timer works correct. Signed-off-by: Kever Yang --- include/configs/rk3328_common.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index

Re: [PATCH v6 0/8] Add a random number generator uclass

On Tue, 31 Dec 2019 at 12:38, Heinrich Schuchardt wrote: > On 12/31/19 3:56 AM, Sughosh Ganu wrote: > > > > On Sat, 28 Dec 2019 at 13:22, Heinrich Schuchardt > > wrote: > > > > On 12/27/19 3:23 PM, Sughosh Ganu wrote: > > > Add a random number generator(rng)

Re: [PATCH v5 6/7] rockchip: Add Single boot image (with binman, pad_cat)

вт, 31 дек. 2019 г. в 10:54, Matwey V. Kornilov : > > пн, 30 дек. 2019 г. в 11:28, Jagan Teki : > > > > All rockchip platforms support TPL or SPL-based bootloader > > in mainline with U-Boot proper as final stage. For each > > stage we need to burn the image on to flash with respective > >