On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
wrote:
>
> With sifive_fu540_spl_defconfig:
>
> U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
> u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
> image u-boot.itb from 1st partition of SD card (replace
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
wrote:
>
> For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
>
> Signed-off-by: Pragnesh Patel
> Reviewed-by: Anup Patel
> ---
> arch/riscv/cpu/u-boot-spl.lds | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
wrote:
>
> Added a misc driver to handle OTP memory in FU540.
>
> Signed-off-by: Pragnesh Patel
> Reviewed-by: Anup Patel
> ---
> arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
> .../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
>
Hello Vignesh,
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Friday, January 24, 2020 10:24 AM
> To: Sagar Kadam ; u-boot@lists.denx.de
> Cc: Paul Walmsley ( Sifive) ;
> anup.pa...@wdc.com; i...@andestech.com; atish.pa...@wdc.com;
> ja...@amarulasolutions.com
> Subject: Re:
On Fri, Jan 24, 2020 at 11:21 AM Pragnesh Patel
wrote:
>
> When build U-boot SPL, meet an issue of undefined reference to
> 'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
> CONFIG_MMC_SPI selected.
>
> Signed-off-by: Pragnesh Patel
> Reviewed-by: Anup Patel
> ---
> lib/Makefile
Hello All,
> -Original Message-
> From: Sagar Kadam
> Sent: Friday, January 24, 2020 1:46 AM
> To: u-boot@lists.denx.de
> Cc: Paul Walmsley ( Sifive) ;
> anup.pa...@wdc.com; i...@andestech.com; atish.pa...@wdc.com;
> ja...@amarulasolutions.com; vigne...@ti.com; Sagar Kadam
>
> Subject:
On Tue, Jan 21, 2020 at 1:11 PM Chen-Yu Tsai wrote:
>
> On Tue, Jan 21, 2020 at 3:29 PM Jagan Teki wrote:
> >
> > On Sun, Jan 12, 2020 at 9:06 PM Chen-Yu Tsai wrote:
> > >
> > > From: Chen-Yu Tsai
> > >
> > > The Libre Computer ALL-H3-IT board is a small single board computer that
> > > is
Lokesh,
On 24/01/20 9:07 am, Lokesh Vutla wrote:
>
>
> On 23/01/20 8:54 PM, Faiz Abbas wrote:
>> The following patches add support for eMMC boot in TI's Am65x and J721e
>> devices.
>
> Can you re order the series something like below?
> - Bring all mmc related driver changes in the beginning
>
Hi Andre,
On Tue, Jan 21, 2020 at 4:03 PM Andre Przywara wrote:
>
> On Tue, 21 Jan 2020 14:05:12 +0530
> Jagan Teki wrote:
>
> Hi Jagan,
>
> thanks for taking care of this.
>
> > Sync R40 dts(i) files from linux-next v5.4 tag.
>
> Why this tag? Shouldn't it be just the v5.4 release tag?
> But
Hello Vignesh,
> -Original Message-
> From: Vignesh Raghavendra
> Sent: Friday, January 24, 2020 10:25 AM
> To: Sagar Kadam ; u-boot@lists.denx.de
> Cc: Paul Walmsley ( Sifive) ;
> anup.pa...@wdc.com; i...@andestech.com; atish.pa...@wdc.com;
> ja...@amarulasolutions.com
> Subject: Re:
Add descriptions about U-Boot SPL feature and how to build and run.
Signed-off-by: Pragnesh Patel
---
doc/board/sifive/fu540.rst | 376 +
1 file changed, 376 insertions(+)
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index
With sifive_fu540_spl_defconfig:
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin) and runs in L2 LIM in machine mode and then load FIT
image u-boot.itb from 1st partition of SD card (replace fw_payload.bin
with u-boot.itb) into RAM.
U-boot SPL expects
This patch enables all cache ways from u-boot proper.
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/Makefile | 1 +
board/sifive/fu540/cache.c | 30 ++
board/sifive/fu540/cache.h | 13 +
board/sifive/fu540/fu540.c | 6 --
4 files changed,
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then boot U-boot FIT image including OpenSBI FW_DYNAMIC firmware
and U-Boot proper images from 1st partition of MMC boot devices.
SPL related code is leverage from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Fix Palmer's email address and add sifive_fu540_spl_defconfig
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
index 702d803ad8..909a1bf300
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these u-boot in FU540 would also require
some u-boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain u-boot specific changes separately without
When build U-boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
---
lib/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/lib/Makefile
This series add support for SPL to FU540.U-Boot SPL can boot from
L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
How to test this patch:
1) Go to OpenSBI-dir : make PLATFORM=sifive/fu540 O=build_dir I=install_dir
FW_DYNAMIC=y install
2) cp
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-boot-spl.lds b/arch/riscv/cpu/u-boot-spl.lds
index
Added a misc driver to handle OTP memory in FU540.
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 13 ++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 6 +
board/sifive/fu540/fu540.c| 113 --
Hello Fabio, Peng,
I have here an imx6ull based board from DH electronics [1]
which has the IMX_THERMAL driver enabled in U-Boot and Linux. We
see on Linux boot random crashes (random means not on every boot,
also not even the same crash dump/reason in linux). My first
suggestion was instable
Hi Tom,
On 16/01/20 2:23 pm, Vignesh Raghavendra wrote:
> Drivers (especially frameworks ported from Linux such as USB) expect
> dma_{un}map_single() APIs to take care of cache maintenance. But this is
> not the case in U-Boot and few drivers take care of flushing caches
> locally. Instead add
There is a typo in meerkat96 MAINTAINERS email address. Fix it.
Reported-by: Carl Gelfand
Signed-off-by: Shawn Guo
---
board/novtech/meerkat96/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/novtech/meerkat96/MAINTAINERS
On 24/01/20 1:46 am, Sagar Shrikant Kadam wrote:
> This patch adds a workaround to change the read/write opcodes
> from QUAD to single bit mode. Idea here is to enable usage of
> spi-flash on the board.
>
> TODO:
> -Enable QUAD mode for spi-flash on HiFive Unleashed A00 board.
>
>
Hi,
On 24/01/20 1:46 am, Sagar Shrikant Kadam wrote:
> Update vendor id for ISSI flash, enable SFDP as ISSI flash
> supports it and add support for spi_nor_fixups similar to
> that done in linux. Flash vendor specific fixups can be
> registered in spi_nor_ids, and will be called after BFPT
>
+ Stefano, who will pick up the patch, I think.
On Thu, Jan 23, 2020 at 7:56 AM Carl Gelfand wrote:
>
> When the board was originally submitted, it was attempting to use the
> ESDHC driver. The board uses the USDHC driver.
>
> Signed-off-by: Carl Gelfand
> Cc: Shawn Guo (maintainer:MEERKAT96
Fix obvious coding style problems, no functional change.
Signed-off-by: Marek Vasut
Cc: Grygorii Strashko
Cc: Sam Protsenko
Cc: Suniel Mahesh
---
drivers/watchdog/omap_wdt.c | 44 ++---
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git
The watchdog timer value was never updated in the hardware by this
driver, so the watchdog triggered on some random stale value that
was left in the hardware. The TI SPRUH37C says, quote:
20.4.3.9 Modifying Timer Count/Load Values and Prescaler Setting
...
After a write access, the load
The timeout parameter of omap3_wdt_start() is in miliseconds, while
GET_WLDR_VAL() expects parameter in seconds. Fix this so the WDT
driver is actually usable.
Signed-off-by: Marek Vasut
Cc: Grygorii Strashko
Cc: Sam Protsenko
Cc: Suniel Mahesh
---
drivers/watchdog/omap_wdt.c | 2 +-
1 file
On 24/01/20 9:07 AM, Lokesh Vutla wrote:
>
>
> On 23/01/20 8:54 PM, Faiz Abbas wrote:
>> The following patches add support for eMMC boot in TI's Am65x and J721e
>> devices.
>
> Can you re order the series something like below?
> - Bring all mmc related driver changes in the beginning
> -
On 23/01/20 8:54 PM, Faiz Abbas wrote:
> The following patches add support for eMMC boot in TI's Am65x and J721e
> devices.
Can you re order the series something like below?
- Bring all mmc related driver changes in the beginning
- Then introduce SoC related changes(arch/arm/*)
Also please
Hi Simon,
On 24/01/20 12:18 AM, Simon Glass wrote:
> Update this driver to use the new standard enums for speed.
>
> Note: This driver needs to move to driver model.
omap24xx_i2c is already converted to DM. The following commits has those
changes. Not sure what you meant here.
commit
On Wed, Jan 22, 2020 at 9:54 PM Baruch Siach wrote:
>
> genboardscfg.py requires python 3.x since commit 3bc14098d8fb
> ("genboardscfg.py: Convert to Python 3").
>
> Cc: Masahiro Yamada
Acked-by: Masahiro Yamada
> Signed-off-by: Baruch Siach
> ---
> v2: Remove the comment entirely
The HF/QSPI flash layout permits up to 1 MiB large bootloader blob,
set CONFIG_BOARD_SIZE_LIMIT to enforce this limit and set the
monitor size to match accordingly.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
include/configs/rcar-gen3-common.h | 5 -
1 file changed, 4
On 23/01/2020 19:37, Matthias Brugger wrote:
Hi,
> On 23/01/2020 12:29, Andre Przywara wrote:
>> On Wed, 22 Jan 2020 19:05:10 +0100
>> Matthias Brugger wrote:
>>
>> Hi,
>>
>> Matthias, many thanks for looking at this and giving it a try!
>>
>>> On 22/01/2020 18:34, Andre Przywara wrote:
On
On 1/23/20 10:57 AM, Patrick DELAUNAY wrote:
> Hi Marek,
Hi,
>> From: Marek Vasut
>> Sent: mardi 21 janvier 2020 22:39
>>
>> Add support for DH Electronics DHCOM SoM and PDK2 rev. 400 carrier board.
>> This is an SoM with STM32MP157C and an evaluation kit. The baseboard
>> provides Ethernet,
This adds support for clock stretching to the i2c-gpio driver. This is
accomplished by switching the GPIO used for the SCL line to an input
when it should be driven high, and polling on the SCL line value until
it goes high (indicating that the I2C slave is no longer pulling it
low).
Hi Igor
BTW: Enjoy your well deserved vacation. I will pick it up and send a v2
don't worry (;-p).
On Thu, 2020-01-23 at 13:31 +0200, Igor Opaniuk wrote:
> This add initial minimal support for the Toradex Verdin iMX8MM 2GB WB
> IT
> V1.0A module.
We just got the final SKU naming update and this
On Mon, Jan 13, 2020 at 03:34:03PM +0100, Holger Brunck wrote:
> This target is out of maintenance and can be removed.
>
> Signed-off-by: Holger Brunck
> CC: Valentin Longchamp
> CC: Stefan Roese
> Reviewed-by: Stefan Roese
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Jan 16, 2020 at 08:36:58PM +0100, Heinrich Schuchardt wrote:
> div_by is a misleading parameter name, when we are doing >> div_by.
> Rename it to right_shift.
>
> Reported-by: Simon Glass
> Signed-off-by: Heinrich Schuchardt
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Mon, Jan 13, 2020 at 03:34:01PM +0100, Holger Brunck wrote:
> This board is similar to SUV31, but the FPGA is reset concept is quite
> different.
>
> Signed-off-by: Holger Brunck
> CC: Valentin Longchamp
> CC: Stefan Roese
> Reviewed-by: Stefan Roese
Applied to u-boot/master, thanks!
--
On Tue, Jan 14, 2020 at 05:41:41PM -0800, Dhananjay Phadke wrote:
> FIT image contents can be larger than default bootm limit 8M
> with initrd. Raise limit to 64MB which is commonly used
> elsewhere.
>
> Signed-off-by: Dhananjay Phadke
> Reviewed-by: Bin Meng
Applied to u-boot/master, thanks!
On Mon, Jan 13, 2020 at 03:34:02PM +0100, Holger Brunck wrote:
> This target is out of maintenance and can be removed.
>
> Signed-off-by: Holger Brunck
> CC: Valentin Longchamp
> CC: Stefan Roese
> Reviewed-by: Stefan Roese
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Fri, Jan 10, 2020 at 12:47:43PM +0100, Holger Brunck wrote:
> From: Rainer Boschung
>
> The CPUWD reset reason is used for kmp204x.
> And the qrio cpu reset request is configured to operate in
> core reset mode.
> But for the evaluation of the qrio's reset reason register
> the CPUWD figures
On Fri, Jan 10, 2020 at 12:55:42PM +0100, Holger Brunck wrote:
> This patch adds the possibility in both debug and ramfs modes to
> optionally load an env file from /tftpboot/$tftppath (this is ignored if
> not present, so the change is backward compatible). This gives the debug
> and ramfs
On Fri, Jan 10, 2020 at 12:55:41PM +0100, Holger Brunck wrote:
> The tftppath was not set in case of run ramfs. It worked only by chance
> if was already set before.
>
> Also check the boardname before setting the tftppath for COGE5.
>
> Signed-off-by: Holger Brunck
> CC: Tom Rini
Applied to
On Sat, Jan 11, 2020 at 09:09:34AM -0700, Joel Johnson wrote:
> Remove unused variable to silence compiler warning
>
> Signed-off-by: Joel Johnson
Applied to u-boot/master, thanks!
--
Tom
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On Fri, Jan 10, 2020 at 12:47:42PM +0100, Holger Brunck wrote:
> This patch moves the qrio and i2c deblocking code to
> keymile/common as it will also be used by the upcoming CENT2 board.
>
> Signed-off-by: Holger Brunck
> CC: Priyanka Jain
Applied to u-boot/master, thanks!
--
Tom
On Fri, Jan 10, 2020 at 12:47:41PM +0100, Holger Brunck wrote:
> This prevents the board from booting which is not the expected behavior.
>
> Signed-off-by: Valentin Longchamp
> Signed-off-by: Holger Brunck
> CC: Priyanka Jain
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Jan 08, 2020 at 08:21:17PM +0900, Masahiro Yamada wrote:
> The base is not used in the code that follows this increment.
>
> Signed-off-by: Masahiro Yamada
Applied to u-boot/master, thanks!
--
Tom
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On Fri, Jan 10, 2020 at 03:53:51PM +0530, Sughosh Ganu wrote:
> Take up maintainership of random number generator drivers with
> Heinrich Schuchardt as the reviewer.
>
> Signed-off-by: Sughosh Ganu
> Reviewed-by: Heinrich Schuchardt
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Jan 09, 2020 at 04:53:32PM +0100, Matthias Schoepfer wrote:
> When using fitImage in AARCH64, the fdt is only 4 byte aligned.
> According to linux kernel -> Documentation/arm64/booting.txt, the
> fdt *must* be 8 byte aligned. Therefore, it is somewhat random,
> if you build a kernel that
On Tue, Jan 07, 2020 at 08:14:17PM +0100, Philippe Reynes wrote:
> This add the initial support of the broadcom reference
> board bcm968360bg with a bcm68360 SoC.
>
> This board has 512 MB of RAM, 256 MB of flash (nand),
> 2 USB port, 1 UART, and 4 ethernet ports.
>
> Signed-off-by: Philippe
On Tue, Jan 07, 2020 at 08:14:16PM +0100, Philippe Reynes wrote:
> As no gpio.h is defined for this architecture, to avoid
> compilation failure, do not include for
> arch bcm68360.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:12PM +0100, Philippe Reynes wrote:
> This IP is also used on some arm SoC, so we allow to
> use it on arm bcm68360 too.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:13PM +0100, Philippe Reynes wrote:
> This adds the nand support for chipset bcm68360.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:15PM +0100, Philippe Reynes wrote:
> This IP is also used on some arm SoC, so we allow to
> use it on arm bcm68360 too.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:14PM +0100, Philippe Reynes wrote:
> This IP is also used on some arm SoC, so we allow to
> use it on arm bcm68360 too.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:11PM +0100, Philippe Reynes wrote:
> This IP is also used on some arm SoC, so we allow to
> use it on arm bcm68360 too.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 08:14:10PM +0100, Philippe Reynes wrote:
> This add the initial support of the broadcom bcm68360 SoC family.
>
> Signed-off-by: Philippe Reynes
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Jan 07, 2020 at 03:50:32PM -0300, Fabio Estevam wrote:
> In order to generate a bootable U-Boot binary for i.MX8QXP MEK
> we need to run:
>
> $ make imx8qxp_mek_defconfig
> $ make flash.bin
>
> The resultant flash.bin and flash.log are not removed after
> running 'make mrproper'.
>
>
On Sat, Jan 04, 2020 at 06:45:18PM +0100, Stephan Gerhold wrote:
> Add myself as maintainer for ST-Ericsson U8500 SoC to MAINTAINERS.
> Linus Walleij usually reviews all Ux500 related patches,
> so add him as a reviewer.
>
> Cc: Linus Walleij
> Signed-off-by: Stephan Gerhold
> Reviewed-by:
On Sat, Jan 04, 2020 at 06:45:17PM +0100, Stephan Gerhold wrote:
> The NovaThor U8500 SoC was released by ST-Ericsson in 2011.
> It was used for some development boards like the CALAO Systems
> Snowball SBC, but mass production was primarily for Android
> smartphones like the Samsung Galaxy S III
On Sat, Jan 04, 2020 at 06:45:19PM +0100, Stephan Gerhold wrote:
> The ST-Ericsson U8500 SoC has been used in mass-production for
> some Android smartphones released around 2012.
> In particular, Samsung has released more than 5 different
> smartphones based on U8500, e.g.
>
> - Samsung Galaxy
On Sat, Jan 04, 2020 at 06:45:15PM +0100, Stephan Gerhold wrote:
> The Nomadik Multi Timer Unit (MTU) provides 4 decrementing
> free-running timers. It is used in ST-Ericsson Ux500 SoCs.
>
> The driver uses the first timer to implement UCLASS_TIMER.
>
> Signed-off-by: Stephan Gerhold
>
On Sun, Dec 15, 2019 at 10:29:39PM +, Rasmus Villemoes wrote:
> I'm also seeing the build failure that commit
>
> 7d4776545b env: solve compilation error in SPL
>
> tried to fix, namely that the reference to env_flags_validate from
> env_htab cannot be satisfied when flags.o is not built
On Sat, Jan 04, 2020 at 06:45:16PM +0100, Stephan Gerhold wrote:
> from
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git/
> tag "ux500-armsoc-v5.6-2"
> commit 224bf0fe7292 ("ARM: dts: ux500: samsung-golden: Add Bluetooth")
>
> (queued for merge in Linux 5.6)
>
>
On Wed, Dec 11, 2019 at 11:03:33AM +, Rasmus Villemoes wrote:
> From: "Klaus H. Sorensen"
>
> Allow reading compressed content from fit image, even if
> CONFIG_SPL_OS_BOOT is not set.
>
> This allow booting compressed 2nd stage u-boot from fit image.
>
> Additionally, do not print warning
On Wed, Jan 01, 2020 at 03:52:31PM +0100, Heinrich Schuchardt wrote:
> Correct some function comments. Convert to Sphinx style.
>
> Signed-off-by: Heinrich Schuchardt
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Dec 31, 2019 at 06:18:22PM +0100, Dario Binacchi wrote:
> The file is generated by scripts/build_OID_registry based on the
> include/linux/oid_registry.h file.
>
> Signed-off-by: Dario Binacchi
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Dec 03, 2019 at 09:38:35AM +0100, Patrick Delaunay wrote:
> Execute the command cls (for clear screen), when the "menu background"
> keyword is present in extlinux.conf file, only if the command is supported.
>
> This patch avoid the warning "Unknown command 'cls'"
> with "menu
On Fri, Nov 29, 2019 at 09:59:26AM +0800, Ley Foon Tan wrote:
> Add an option for building cache drivers in SPL.
>
> Signed-off-by: Ley Foon Tan
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Goldschmidt
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Jan 23, 2020 at 10:04:05PM +0100, Luka Kovačič wrote:
> Hello Tom,
>
> thank you for feedback and review. I understand the implications.
> Would it make sense to document this somewhere to avoid any future confusion?
Yes, along with a standalone patch to update the document to use
Hello Tom,
thank you for feedback and review. I understand the implications.
Would it make sense to document this somewhere to avoid any future confusion?
Thanks,
Luka
On Thu, Jan 23, 2020 at 1:31 PM Tom Rini wrote:
>
> On Sun, Jan 05, 2020 at 08:10:56PM +0100, Luka Kovacic wrote:
>
> > Use
Add fdt->gd info to bdinfo so that it is useful for debugging
and easily use it with fdt util.
Signed-off-by: Sagar Shrikant Kadam
---
cmd/bdinfo.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index d6a7175..96892b3 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
Add number of chip select information to spi nodes which
can be used by spi-uclass for error handling if invlaid cs
number passed from command.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/fu540-c000.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git
This patch adds a workaround to change the read/write opcodes
from QUAD to single bit mode. Idea here is to enable usage of
spi-flash on the board.
TODO:
-Enable QUAD mode for spi-flash on HiFive Unleashed A00 board.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/mtd/spi/spi-nor-core.c | 15
Currently device ID for flash mounted on HiFive Unleashed is added to
U-Boot. Also there are few patches to go mainline (Thanks to Jagan Tekki
and Bin Meng).
This series addresses few issues discussed there:
Patch 1: Includes hifive-unleashed-a00-u-boot.dts for building DTB
Patch 2: Prints fdt
Update vendor id for ISSI flash, enable SFDP as ISSI flash
supports it and add support for spi_nor_fixups similar to
that done in linux. Flash vendor specific fixups can be
registered in spi_nor_ids, and will be called after BFPT
parsing to fix any wrong parameter read from SFDP.
Signed-off-by:
Use bitlen passed by dm_spi_ops rather than using spi-tx/
rx-bus-width from the device tree, to set the mode bits in
format register of spi controller present in FU540-C000 SoC
on HiFive Unleashed board.
This patch handles a case where controller mode in format
register (0x40) is configured as
Add missing bus claim/release method to spi driver for HiFive
Unleashed, and handle num_cs generously so that it generates
error if invalid cs number is passed to sf probe.
Signed-off-by: Sagar Shrikant Kadam
---
drivers/spi/spi-sifive.c | 36
1 file
Include hifive-unleashed-a00-u-boot.dtsi introduced earlier
so that it gets compiled within the dt-blob.
Signed-off-by: Sagar Shrikant Kadam
---
arch/riscv/dts/hifive-unleashed-a00.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts
On 23/01/2020 12:29, Andre Przywara wrote:
> On Wed, 22 Jan 2020 19:05:10 +0100
> Matthias Brugger wrote:
>
> Hi,
>
> Matthias, many thanks for looking at this and giving it a try!
>
>> On 22/01/2020 18:34, Andre Przywara wrote:
>>> On Wed, 22 Jan 2020 18:18:39 +0100
>>> Matthias Brugger
If a different input clock is required then the correct way to do this is
with a clock driver. Don't allow boards to override IC_CLK.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/designware_i2c.h | 2 --
1 file changed, 2
Some SoCs support a higher speed than what is currently called 'max' in
this driver. Rename it to 'high' speed, which is the official name of the
3.4MHz speed.
Signed-off-by: Simon Glass
Reviewed-by: Jun Chen
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
Group these #defines into an enum to make it easier to understand the
relationship between them.
Signed-off-by: Simon Glass
Reviewed-by: Jun Chen
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/designware_i2c.c | 2 +-
drivers/i2c/designware_i2c.h | 10
Some versions of this peripherals provide more control of the bus
behaviour. Add definitions for these registers.
Signed-off-by: Simon Glass
Reviewed-by: Ley Foon Tan
Reviewed-by: Jun Chen
Reviewed-by: Heiko Schocher
---
Changes in v3:
- Fix the address of comp_param1 by adding a gap
Currently watchdog tries to use dev_read_u32_default to get timeout
configuration in case OF_CONTROL is enabled. However, if SPL is
built with OF_PLATDATA this has no sense as there is no device tree.
This patch fixes this issue by only use dev_read_u32_default if OF_CONTROL
is enabled but
Some drivers define their own speed enums and use their own constants for
speed. It makes sense to have a unified defition of the different speeds.
Since many controllers have to do different things for fast/high speed, it
is a good idea to have an enum for the mode.
Add these as well as an enum
At present the driver uses an approximation for the bus clock, e.g. 166MHz
instead of 166 2/3 MHz.
This can result in small errors in the resulting I2C speed, perhaps 0.5%
or so.
Adjust the existing code to start from the accurate figure, even if later
rounding reduces this accuracy.
Update the
Move some of the code currently in the ofdata_to_platdata() method to
probe() so that it is not executed when generating ACPI tables.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to do more in the probe() method
Changes in v2: None
drivers/i2c/designware_i2c.c | 16
We want to be able to calculate the speed separately from actually setting
the speed, so we can generate the required ACPI tables. Split out the
calculation into its own function.
Drop the double underscore on __dw_i2c_set_bus_speed while we are here.
That is reserved for compiler internals.
This is used to store the speed information for a bus. We want to provide
this to ACPI so that it can tell the kernel. Move this struct to the
header file so it can be accessed by the ACPI i2c implementation being
added later.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch to
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/omap24xx_i2c.c | 2 +-
drivers/i2c/omap24xx_i2c.h | 4
2 files
Fast-plus runs at 1MHz and is used by some devices. Add support for this.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add new patch with support for fast-plus speed
Changes in v2: None
drivers/i2c/designware_i2c.c | 12 ++--
drivers/i2c/designware_i2c.h | 2 ++
2 files changed,
At present the driver can end up with timing parameters which are slightly
faster than those expected. It is possible to optimise the parameters to
get the best possible result.
Create a new function to handle the timing calculation. This uses a table
of defaults for each speed mode rather than
Update this driver to use the new standard enums for speed.
Note: This driver needs to move to driver model.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/kona_i2c.c | 28 +++-
1 file changed, 11
Create a struct to hold the three timing parameters. This will make it
easier to move these calculations into a separate function in a later
patch.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/designware_i2c.c | 82
Some versions of this peripheral include a spike-suppression phase of the
bus. Add support for this.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2:
- Add a few more clean-up patches for i2c
drivers/i2c/designware_i2c.c | 10 +-
Update this driver to use the new standard enums for speed.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
---
Changes in v3: None
Changes in v2: None
drivers/i2c/ast_i2c.c | 2 +-
drivers/i2c/ast_i2c.h | 2 --
2 files changed, 1 insertion(+), 3 deletions(-)
diff --git
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