On Wed, 5 Feb 2020 at 05:53, Heinrich Schuchardt wrote:
>
> RISC-V booting currently is based on a per boot stage lottery to determine
> the active CPU. The Hart State Management (HSM) SBI extension replaces
> this lottery by using a dedicated primary CPU.
>
> Cf. Hart State Management Extension,
Hi Peng,
On 05/02/20 12:58 pm, Peng Fan wrote:
>> Subject: Re: [PATCH v2 04/10] mmc: sdhci: Expose sdhci_init() as non-static
>>
>> Hi,
>>
>> On 31/01/20 3:55 am, Simon Goldschmidt wrote:
>>> Am 30.01.2020 um 23:21 schrieb Jaehoon Chung:
Hi Simon,
On 1/29/20 11:16 PM, Simon
> Subject: Re: [PATCH v2 04/10] mmc: sdhci: Expose sdhci_init() as non-static
>
> Hi,
>
> On 31/01/20 3:55 am, Simon Goldschmidt wrote:
> > Am 30.01.2020 um 23:21 schrieb Jaehoon Chung:
> >> Hi Simon,
> >>
> >> On 1/29/20 11:16 PM, Simon Goldschmidt wrote:
> >>> On Wed, Jan 29, 2020 at 12:00 AM
> Subject: [PATCH] mx6ullevk: Enable Ethernet support
>
> Add Ethernet support using DM_ETH.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Peng Fan
> ---
> board/freescale/mx6ullevk/mx6ullevk.c | 47
> +++
> configs/mx6ull_14x14_evk_defconfig| 8 +
>
> Subject: [PATCH 1/2] mx6ul_evk: Move CONFIG_FEC_MXC to defconfig
>
> CONFIG_FEC_MXC is supported in Kconfig, so it is preferred to move it to
> defconfig file.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Peng Fan
> ---
> configs/mx6ul_14x14_evk_defconfig | 1 +
>
> Subject: [PATCH 2/2] mx6ul_evk: Remove FEC related board code
>
> mx6ul_evk uses DM_ETH, so there is no need to have board code to setup the
> FEC IOMUX and to register the network ports via the old board_eth_init()
> method.
>
> Remove these FEC related pieces of code.
>
> Signed-off-by:
> Subject: [PATCH v2] mx6sxsabresd: Keep only one target
>
> Currently there are two targets for the i.MX6SX SabreSD board:
> mx6sxsabresd_defconfig and mx6sxsabresd_spl_defconfig.
>
> This brings additional maintainance effort without a clear advantage.
>
> Keep only the mx6sxsabresd_defconfig
> Subject: [PATCH] mmc: fsl_esdhc: actually enable cache snooping on mpc830x
+ Y.b
Are you ok with this patch?
Thanks,
Peng.
>
> The reference manuals for MPC8308 and MPC8309 both say that the esdhcctl
> aka DMA Control Register "is implemented as SDHCCR" in the System
> configuration
The following changes since commit 31a790bee939e227dfc7e6a6a323b2b13180707f:
Merge branch 'master' of git://git.denx.de/u-boot-usb (2020-02-02
15:26:53 -0500)
are available in the Git repository at:
git://git.denx.de/u-boot-socfpga.git master
for you to fetch changes up to
clear_bss is already used by 3 arches (x86, arc, xtensa), so make it generic
and provide a weak nop stub for it. This also removes arch-specific ifdef
duplications around clear_bss.
Signed-off-by: Ovidiu Panait
---
common/board_f.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
>-Original Message-
>From: U-Boot On Behalf Of Heinrich Schuchardt
>Sent: Sunday, January 26, 2020 1:10 AM
>To: Prabhakar Kushwaha
>Cc: Sumit Garg ; u-boot@lists.denx.de; Bhaskar
>Upadhaya ; Heinrich Schuchardt
>
>Subject: [PATCH 1/1] board: ls1012ardb: do not use imply CONFIG_
>
>Inside
>-Original Message-
>From: U-Boot On Behalf Of Priyanka Singh
>Sent: Wednesday, January 22, 2020 4:03 PM
>To: u-boot@lists.denx.de
>Cc: Udit Agarwal ; Ruchika Gupta
>; Arun Pathak
>Subject: [PATCH 1/2] armv8: ls1088a: Updates secure boot headers offset
>
>Updates the secure boot headers
>-Original Message-
>From: U-Boot On Behalf Of Priyanka Singh
>Sent: Wednesday, January 22, 2020 4:01 PM
>To: u-boot@lists.denx.de
>Cc: Udit Agarwal ; Ruchika Gupta
>; Arun Pathak
>Subject: [PATCH 1/1] armv8: lx2160a: Updates secure boot headers offset
>
>Updates the secure boot headers
>-Original Message-
>From: U-Boot On Behalf Of Alison Wang
>Sent: Tuesday, January 21, 2020 1:03 PM
>To: Priyanka Jain ; u-boot@lists.denx.de
>Cc: Alison Wang ; Peng Ma
>Subject: [PATCH] configs: ls1021a: Reserve low memory for CMA
>
>The default reserved memory for CMA is high memory.
>-Original Message-
>From: Biwen Li
>Sent: Wednesday, February 5, 2020 7:39 AM
>To: Biwen Li ; Jagdish Gediya ;
>Priyanka Jain ; h...@denx.de;
>ja...@amarulasolutions.com; aford...@gmail.com; Alison Wang
>; jh80.ch...@samsung.com; Pramod Kumar
>; Rajesh Bhagat ;
>Ruchika Gupta ;
>-Original Message-
>From: Kuldeep Singh
>Sent: Wednesday, November 6, 2019 4:38 PM
>To: u-boot@lists.denx.de
>Cc: Priyanka Jain ; Kuldeep Singh
>
>Subject: [PATCH 1/4] arm: dts: ls1028a: Add FSPI node properties
>
>Align flexspi node properties with linux device-tree properties Tested on
>-Original Message-
>From: U-Boot On Behalf Of Meenakshi
>Aggarwal
>Sent: Thursday, January 23, 2020 5:55 PM
>To: u-boot@lists.denx.de; Priyanka Jain
>Subject: [PATCH v4] board: fsl: lx2160a: Add support to reset to eMMC
>
>Add support of "qixis_reset emmc" command for lx2160a based
>-Original Message-
>From: Michael Walle
>Sent: Wednesday, December 18, 2019 4:40 AM
>To: u-boot@lists.denx.de
>Cc: Vignesh R ; Prabhakar X
>; Kuldeep Singh ;
>Priyanka Jain ; Michael Walle
>Subject: [PATCH v4 2/3] arm: ls1028a: use the new flexspi driver
>
>Also align the fspi node with
>-Original Message-
>From: Kuldeep Singh
>Sent: Thursday, December 12, 2019 2:46 PM
>To: u-boot@lists.denx.de
>Cc: Priyanka Jain ; tr...@konsulko.com; Kuldeep
>Singh
>Subject: [PATCH] configs: ls1012ardb: Enable
>CONFIG_SYS_RELOC_GD_ENV_ADDR
>
>Enable the config for ls1012ardb as the
>-Original Message-
>From: Biwen Li
>Sent: Tuesday, December 31, 2019 1:04 PM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>jh80.ch...@samsung.com; Pramod Kumar ;
>Rajesh Bhagat ; Ruchika Gupta
>; olte...@gmail.com
>-Original Message-
>From: Biwen Li
>Sent: Tuesday, December 31, 2019 1:04 PM
>To: Jagdish Gediya ; Priyanka Jain
>; h...@denx.de; ja...@amarulasolutions.com;
>aford...@gmail.com; Alison Wang ;
>jh80.ch...@samsung.com; Pramod Kumar ;
>Rajesh Bhagat ; Ruchika Gupta
>; olte...@gmail.com
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on
search for gpio label if gpio name from bankname is not found.
This makes sense on boards with different hardware verions. You
can now search for the gpio label name, and can give the gpio
a unique name. The real gpio pin number is not needed in board
code anymore.
while at it add basic gpio hog
currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher
---
Changes in v3: None
Dear Tom,
Please find my pull-request for u-boot-fsl-qoriq/master
https://travis-ci.org/p-priyanka-jain/u-boot/builds/645892188
Summary
Bug fixes on ls1012a, ls1021a, ls1028ardb platforms
Integrate fspi for ls1028a , add DM-I2C support,
update secure boot header offset
priyankajain
On 2/5/20 1:28 AM, Atish Patra wrote:
On Sat, Feb 1, 2020 at 8:55 AM Heinrich Schuchardt wrote:
RISC-V patches are developed for OpenSBI and Linux to replace random boot
by sequential CPU bring-up.
In this scenario the id of the active hart has to be passed from boot stage
to boot stage.
RISC-V booting currently is based on a per boot stage lottery to determine
the active CPU. The Hart State Management (HSM) SBI extension replaces
this lottery by using a dedicated primary CPU.
Cf. Hart State Management Extension, Extension ID: 0x48534D (HSM)
On Fri, Jan 24, 2020 at 4:32 PM Chen-Yu Tsai wrote:
>
> On Fri, Jan 24, 2020 at 2:24 PM Jagan Teki wrote:
> >
> > On Tue, Jan 21, 2020 at 1:11 PM Chen-Yu Tsai wrote:
> > >
> > > On Tue, Jan 21, 2020 at 3:29 PM Jagan Teki
> > > wrote:
> > > >
> > > > On Sun, Jan 12, 2020 at 9:06 PM Chen-Yu
On 2/4/20 2:16 PM, Patrick DELAUNAY wrote:
> Hi Marek
Hello Patrick,
[...]
What I think you are missing is that not everyone will update
ATF/U-Boot/Linux in lockstep. That is the problem you need to deal with
here.
>>>
>>> I understood the possible issue and I hope that I will
This function name conflicts with our desire to #define free() to
something else on sandbox. Since it deals with resources, rename it to
rfree().
Signed-off-by: Simon Glass
---
Changes in v3:
- Update microblaze manual relocation
Changes in v2: None
drivers/gpio/gpio-rcar.c | 2 +-
> Subject: [v8 1/8] rtc: pcf8563: Add driver model support
>
> Add support of driver model of pcf8563
>
> Signed-off-by: Biwen Li
> ---
> Changes in v8:
> - none
>
> Changes in v7:
> - none
>
> Changes in v6:
> - none
>
> Changes in v5:
> - none
>
> Changes in v4:
>
H1 is a Google security chip present in recent Chromebooks, Pixel phones
and other devices. Cr50 is the name of the software that runs on H1 in
Chromebooks.
This chip is used to handle TPM-like functionality and also has quite a
few additional features.
Add a driver for this.
Signed-off-by:
Add definitions for access and status.
Need to drop the mixed case.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
include/tpm-v2.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/tpm-v2.h
Enable TPM2 so that we can use cr50.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Update the commit message
- Add new patches to handle requesting interrupts and interrupt state
configs/chromebook_coral_defconfig | 3 ++-
1 file changed, 2
ACPI GPEs are used to signal interrupts from peripherals that are accessed
via ACPI. In U-Boot these are modelled as interrupts using a separate
interrupt controller. Configuration is via the device tree.
Add a simple driver for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Allow this driver to be used in TPL by setting up the interrupt type
correctly.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/cpu/intel_common/itss.c | 10 ++
1 file changed, 10 insertions(+)
diff --git
At present driver model supports the IRQ uclass but there is no way to
request a particular interrupt for a driver.
Add a mechanism, similar to clock and reset, to read the interrupts
required by a device from the device tree and to request those interrupts.
U-Boot itself does not have
Add an IRQ type to each driver and use irq_first_device_type() to find
and probe the correct one.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Move 'success' comment into previous patch
arch/x86/cpu/apollolake/fsp_s.c | 4 ++--
Add nodes to the device tree for Cr50 and other available I2C ports. Also
enable the ACPI interrupt driver.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Move intel-clock.h inclusion to the correct patch
arch/x86/cpu/apollolake/Kconfig | 1 +
There can be different types of interrupt controllers in a system and some
drivers may need to distinguish between these. In general this can be
handled using the device tree by adding the interrupt information to
device nodes.
However on x86 devices we have interrupt controllers which are not
Enable the Intel clock driver and modify coral's device tree to use it.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Move intel-clock.h inclusion to the correct patch
arch/x86/cpu/apollolake/Kconfig | 3 +++
arch/x86/dts/chromebook_coral.dts | 5
This config is not actually used here and in U-Boot it seems better to set
this using the device tree for each individual controller. The monolithic
config of the FSP-S is only necessary if the FSP is actually configuring
something, but here it is not.
The FSP-S does enable/disable the various
These are actually working correctly, so update the status.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
doc/board/google/chromebook_coral.rst | 2 --
1 file changed, 2 deletions(-)
diff --git a/doc/board/google/chromebook_coral.rst
So far we have avoided adding a clock driver for Intel devices. But the
Designware I2C driver needs a different clock (133MHz) on Intel devices
than on others (166MHz). Add a simple driver that provides this
information.
This driver can be expanded later as needed.
Signed-off-by: Simon Glass
Now that we have uclass_first_device_drvdata(), use it from syscon to
reduce code duplication.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Add new patch to change syscon to use helper function
drivers/core/syscon-uclass.c | 15 ---
1
This series adds a driver for the Cr50 security chip and enables it on
coral. This supports the 'tpm' command.
In order to make this work a few other changes are included:
- Additional UCLASS_IRQ operations to support requesting and reading
interrupts, using the device tree
- A driver for ACPI
Now that we have uclass_first_device_drvdata(), use it from the I2C driver
to reduce code duplication.
Signed-off-by: Simon Glass
Reviewed-by: Heiko Schocher
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Add new patch to change tegra driver to use helper function
At present we have uclass_foreach_dev() which requires that uclass_get()
be called beforehand to find the uclass. This is good if we suspect that
that function might fail, but often we know that the uclass is available.
Add a new helper which does this uclass_get() automatically, so that only
the
It is sometimes useful to find a device in a uclass using only its driver
data. The driver data often indicates the 'subtype' of the device, e,g,
via its compatible string.
Add a function to handle this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
-
On Wed, Feb 5, 2020 at 9:11 AM Eric Lin wrote:
>
>
> Hi Bin,
>
> Bin Meng 於 2020年2月4日 週二 下午11:50寫道：
> >
> > On Thu, Jun 6, 2019 at 5:06 PM Eric Lin wrote:
> > >
> > > This patch adds Kconfig entries for the F (Single-Precision)
> > > and D (Double-Precision) floating point instruction-set
Currently, there's no way to fetch the value of an environment
variable whose name is stored in some other variable, or generated from
such - in non-working pseudo-code,
${${varname}}
${array${index}}
This forces some scripts to needlessly duplicate logic and hardcode
assumptions. For
On Tue, Feb 04, 2020 at 02:58:01PM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following changes for v2020.04:
>
> - Various minor fixes for x86
> - Switch to ACPI mode on Intel edison
> - Support run-time configuration for NS16550 driver
> - Update coreboot and slimbootloader
On Tue, Feb 04, 2020 at 09:17:07PM -0300, Fabio Estevam wrote:
> Hi Baruch,
>
> On Tue, Feb 4, 2020 at 1:57 PM Baruch Siach wrote:
> >
> > fdt_high value of 0x disables fdt relocation on boot. We don't
> > need that for Cubox-i/Hummingboard. Rely on generic code to find the
> > optimal
Hi Oliver,
On Mon, Feb 3, 2020 at 1:09 PM Oliver Graute wrote:
> thx, I'll fix that on the congatec cgtqmx8 board dts file. The phy issue here
> was on the advantech imx8qm-rom7720 board.
imx8qm-rom7720-a1.dts seems to properly describe the PHY addresses.
I haven't followed the whole
Hi Baruch,
On Tue, Feb 4, 2020 at 1:57 PM Baruch Siach wrote:
>
> fdt_high value of 0x disables fdt relocation on boot. We don't
> need that for Cubox-i/Hummingboard. Rely on generic code to find the
> optimal fdt location at boot time.
>
> Signed-off-by: Baruch Siach
> ---
>
]Hi Thirupathaiah,
On Tue, 4 Feb 2020 at 10:09, Thirupathaiah Annapureddy
wrote:
>
> Thank You Simon for the review.
>
> May I know what are the next steps in making forward progress on this?
The patch is in my queue but I've had some test failures. Assuming it
is not the culprit I expect it
On Tue, 4 Feb 2020 at 04:09, Masahiro Yamada
wrote:
>
> dma_unmap_single() takes the dma address, not virtual address.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> arch/arm/include/asm/dma-mapping.h | 4 +---
> arch/nds32/include/asm/dma-mapping.h | 4 +---
>
Hi Thirupathaiah,
On Tue, 4 Feb 2020 at 10:08, Thirupathaiah Annapureddy
wrote:
>
> Hi All,
>
> May I know what are the next steps in making forward progress on this?
Can you please add a test for this? We need a sandbox driver of some
sort - see the existing sandbox TPM driver.
Regards,
Simon
On Tue, 4 Feb 2020 at 04:09, Masahiro Yamada
wrote:
>
> Make dma_map_single() return the dma address, and remove the
> pointless volatile.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> arch/arm/include/asm/dma-mapping.h | 5 +++--
> arch/nds32/include/asm/dma-mapping.h | 5 +++--
>
Hi Sean,
On Mon, 3 Feb 2020 at 16:15, Sean Anderson wrote:
>
> > Please can you add a test for this new functionality?
>
> Should this be separate from test/dm/bus.c? As far as I can tell, that
> file tests the concept of busses, and not the bus uclass.
Yes it is fine to add a
On Fri, 2019-11-22 at 18:19 -0800, Atish Patra wrote:
> On Wed, 2019-11-13 at 11:47 -0800, Atish Patra wrote:
> > On Wed, 2019-11-13 at 15:36 +0200, David Abdurachmanov wrote:
> > > On Sat, Nov 9, 2019 at 2:14 AM Atish Patra
> > > wrote:
> > > > Add compressed Image parsing support so that booti
This partially reverts changes by commit 2cc393f32fd9
("video: make BPP and ANSI configs optional") since it
caused issues with other boards (missing LCD console
output on pinebook, x86 platform or sandbox). Enable
all disabled options again and opt out of not supported
color depth in board
From: Igor Opaniuk
Remove 'fdt_high' and 'initrd_high' environment variables (set to 0x)
from default environment which prevents relocation of FDT and initrd.
Rely on 'bootm_size' value instead to safely relocate kernel, device tree and
initrd.
Signed-off-by: Igor Opaniuk
---
From: Igor Opaniuk
Remove 'fdt_high' and 'initrd_high' environment variables (set to 0x)
from default environment which prevents relocation of FDT and initrd.
Rely on 'bootm_size' value instead to safely relocate kernel, device tree and
initrd.
Signed-off-by: Igor Opaniuk
---
From: Igor Opaniuk
Remove 'fdt_high' and 'initrd_high' environment variables (set to 0x)
from default environment which prevents relocation of FDT and initrd.
Rely on 'bootm_size' value instead to safely relocate kernel, device tree and
initrd.
Signed-off-by: Igor Opaniuk
---
From: Igor Opaniuk
Remove 'fdt_high' and 'initrd_high' environment variables (set to 0x)
from default environment which prevents relocation of FDT and initrd.
Rely on 'bootm_size' value instead to safely relocate kernel, device tree and
initrd.
Signed-off-by: Igor Opaniuk
---
From: Igor Opaniuk
Remove 'fdt_high' and 'initrd_high' environment variables (set to 0x)
from default environment which prevents relocation of FDT and initrd.
Rely on 'bootm_size' value instead to safely relocate kernel, device tree and
initrd.
Signed-off-by: Igor Opaniuk
---
Hello Heiko,
thanks a lot for your annotations and suggestions. I will have a look at
them and give you feedback ASAP.
Regards
Stefan
Am 04.02.20 um 07:58 schrieb Heiko Schocher:
Hello Stefan,
Am 03.02.2020 um 21:40 schrieb Stefan Bosch:
Changes in relation to FriendlyARM's U-Boot
On Tue, Feb 04, 2020 at 06:19:39PM +0100, Anatolij Gustschin wrote:
> On Tue, 4 Feb 2020 11:49:59 -0500
> Tom Rini tr...@konsulko.com wrote:
> ...
> > > config VIDEO_BPP32
> > > bool "Support 32-bit-per-pixel displays"
> > > depends on DM_VIDEO
> > > - default y if X86
> > > + default y if
On Tue, 4 Feb 2020 11:49:59 -0500
Tom Rini tr...@konsulko.com wrote:
...
> > config VIDEO_BPP32
> > bool "Support 32-bit-per-pixel displays"
> > depends on DM_VIDEO
> > - default y if X86
> > + default y if DM_VIDEO && !VIDEO_BPP_OPT_OUT
> > help
> > Support drawing text and
Thank You Simon for the review.
May I know what are the next steps in making forward progress on this?
Best Regards,
Thiru
On 1/7/2020 12:33 AM, Simon Goldschmidt wrote:
> On Tue, Jan 7, 2020 at 7:21 AM Thirupathaiah Annapureddy
> wrote:
>>
>> boot_fdt_add_mem_rsv_regions() scans the
Hi All,
May I know what are the next steps in making forward progress on this?
Best Regards,
Thiru
On 1/12/2020 11:34 PM, Thirupathaiah Annapureddy wrote:
> Add a driver for a firmware TPM running inside TEE.
>
> Documentation of the firmware TPM:
>
On Mon, Feb 03, 2020 at 01:59:14PM +, Oliver Graute wrote:
> As proposed here:
>
> https://lists.denx.de/pipermail/u-boot/2020-January/396749.html
>
> Both of my imx8qm boards (Advantech and Congatec) aren't booting
> 2020.01 without this change. Whats the proper way to fix this on my side?
On Mon, Feb 03, 2020 at 02:49:24PM +0530, Jagan Teki wrote:
> Add distro boot command support for SPI flash in Rockchip.
>
> This distro boot will read the boot script at specific
> location at the flash and start sourcing the same.
>
> Included the SF device at the last of the target devices
>
fdt_high value of 0x disables fdt relocation on boot. We don't
need that for Cubox-i/Hummingboard. Rely on generic code to find the
optimal fdt location at boot time.
Signed-off-by: Baruch Siach
---
include/configs/mx6cuboxi.h | 1 -
1 file changed, 1 deletion(-)
diff --git
On Mon, Feb 03, 2020 at 10:48:10PM +0100, Anatolij Gustschin wrote:
> Enable all BPP options by default to avoid empty video console
> output (this was the case before commit 2cc393f32fd9 ("video: make
> BPP and ANSI configs optional")). But also support optional selection
> of only required
On Tue, Feb 04, 2020 at 12:06:30PM +0530, Keerthy wrote:
> Move the generic elf loading/validating functions to lib/
> so that they can be re-used and accessed by code existing
> outside cmd.
>
> While at it remove the duplicate static version of load_elf_image_phdr
> under
On Tue, Feb 04, 2020 at 09:28:38AM +0530, Lokesh Vutla wrote:
> Hi Tom,
>
> Please find the pull request for v2020.04-rc2 containing TI specific changes.
> This PR is a re spin of previous PR[0] without mmc changes and fetched
> few dt changes and watchdog fixes.
>
> [0]
On 2/4/20 11:04 AM, Bin Meng wrote:
> Hi Sean,
>
> On Tue, Feb 4, 2020 at 10:48 PM Sean Anderson wrote:
>> In any case, the errors I get are
>>
>> arch/riscv/cpu/cpu.c: Assembler messages:
>> arch/riscv/cpu/cpu.c:94: Error: unknown CSR `CSR_MSCOUNTEREN'
>> arch/riscv/cpu/cpu.c:94: Error: unknown
Hi Sean,
On Tue, Feb 4, 2020 at 10:48 PM Sean Anderson wrote:
>
> On 2/4/20 9:38 AM, Bin Meng wrote:
> > Hi Sean,
> >
> > On Tue, Feb 4, 2020 at 10:19 PM Sean Anderson wrote:
> >> I believe the macro compiles to "csrs CSR_FOO". At least with my
> >> gcc/binutils (9.2.0/2.33.1) this style is not
On Thu, Jun 6, 2019 at 5:06 PM Eric Lin wrote:
>
> This patch adds Kconfig entries for the F (Single-Precision)
> and D (Double-Precision) floating point instruction-set extensions.
>
> Signed-off-by: Eric Lin
> ---
> Changes for v2:
> - Grammatical correction in commit message "adds"
>
Hi Rick,
When going through all patches in the RISC-V queue, I found this old
patch was not applied. Is it still needed?
Anyway, see my review comments below.
On Mon, Oct 8, 2018 at 1:43 PM Andes wrote:
>
> From: Rick Chen
>
> Add to print board and bit information message.
nits: please
Hi,
On Thu, Dec 19, 2019 at 1:42 PM David Abdurachmanov
wrote:
>
> On Thu, Dec 19, 2019 at 12:18 AM Vagrant Cascadian wrote:
> >
> > On 2019-12-18, David Abdurachmanov wrote:
> > > On Wed, Dec 18, 2019 at 3:13 AM Vagrant Cascadian
> > > wrote:
> > >>
> > >> On 2019-09-25, Vagrant Cascadian
On Tue, Jan 28, 2020 at 2:41 PM Pragnesh Patel
wrote:
>
>
> >-Original Message-
> >From: Jagan Teki
> >Sent: 27 January 2020 13:22
> >To: Pragnesh Patel
> >Cc: U-Boot-Denx ; Atish Patra
> >; palmerdabb...@google.com; Bin Meng
> >; Paul Walmsley ( Sifive)
> >; Troy Benjegerdes ( Sifive)
On Mon, Dec 30, 2019 at 10:29 PM Jagan Teki wrote:
>
> OpenSBI build steps are marked as normal text in
> AX25-AE350 documentation.
>
> Move them into code-block so-that it can show it
> as build steps.
>
> Cc: Heinrich Schuchardt
> Signed-off-by: Jagan Teki
> ---
>
On Sat, Dec 28, 2019 at 2:51 AM Heinrich Schuchardt wrote:
>
> Since commit 04883bf7acca ("doc: update AX25-AE350 RISC-V documentation")
> `make htmldocs` produces a log of warnings like
>
> doc/board/AndesTech/ax25-ae350.rst:373:
> WARNING: Block quote ends without a blank line; unexpected
On 2/4/20 9:42 AM, Bin Meng wrote:
> Hi Sean,
>
> On Tue, Feb 4, 2020 at 10:26 PM Sean Anderson wrote:
>>
>> On 2/4/20 6:38 AM, Bin Meng wrote:
>>> Hi Sean,
>>>
>>> On Mon, Feb 3, 2020 at 4:11 AM Sean Anderson wrote:
The Sipeed Maix series is a collection of boards built around the
On 2/4/20 9:38 AM, Bin Meng wrote:
> Hi Sean,
>
> On Tue, Feb 4, 2020 at 10:19 PM Sean Anderson wrote:
>> I believe the macro compiles to "csrs CSR_FOO". At least with my
>> gcc/binutils (9.2.0/2.33.1) this style is not available for these older
>> CSRs. Perhaps it would work if we switched to
Hi Sean,
On Tue, Feb 4, 2020 at 10:26 PM Sean Anderson wrote:
>
> On 2/4/20 6:38 AM, Bin Meng wrote:
> > Hi Sean,
> >
> > On Mon, Feb 3, 2020 at 4:11 AM Sean Anderson wrote:
> >>
> >> The Sipeed Maix series is a collection of boards built around the RISC-V
> >> Kendryte K210 processor. This
Hi Sean,
On Tue, Feb 4, 2020 at 10:23 PM Sean Anderson wrote:
>
> On 2/4/20 6:32 AM, Bin Meng wrote:
> > Hi Sean,
> >
> > On Mon, Feb 3, 2020 at 4:10 AM Sean Anderson wrote:
> >>
> >> Where possible, I have tried to find compatible drivers based on the
> >> layout of
> >> registers. However, I
Hi Sean,
On Tue, Feb 4, 2020 at 10:19 PM Sean Anderson wrote:
>
>
> On 2/4/20 6:21 AM, Bin Meng wrote:
> > Hi Sean,
> >
> > On Mon, Feb 3, 2020 at 4:05 AM Sean Anderson wrote:
> >>
> >> Some older processors (notably the Kendryte K210) use an older version of
> >> the
> >> RISC-V privileged
On 2/4/20 9:27 AM, Bin Meng wrote:
> Hi Sean,
>
> On Tue, Feb 4, 2020 at 10:06 PM Sean Anderson wrote:
>>
>> On 2/4/20 5:36 AM, Bin Meng wrote:
>>> On Mon, Feb 3, 2020 at 1:40 AM Sean Anderson wrote:
>>> I believe both 2 patches in this series are needed by "riscv: Add
>>> Sipeed Maix support"
Hi Sean,
On Tue, Feb 4, 2020 at 10:06 PM Sean Anderson wrote:
>
> On 2/4/20 5:36 AM, Bin Meng wrote:
> > On Mon, Feb 3, 2020 at 1:40 AM Sean Anderson wrote:
> > I believe both 2 patches in this series are needed by "riscv: Add
> > Sipeed Maix support" series?
> > If yes, I think you can just
On 2/4/20 6:38 AM, Bin Meng wrote:
> Hi Sean,
>
> On Mon, Feb 3, 2020 at 4:11 AM Sean Anderson wrote:
>>
>> The Sipeed Maix series is a collection of boards built around the RISC-V
>> Kendryte K210 processor. This processor contains several peripherals to
>> accelerate neural network processing
On 2/4/20 6:32 AM, Bin Meng wrote:
> Hi Sean,
>
> On Mon, Feb 3, 2020 at 4:10 AM Sean Anderson wrote:
>>
>> Where possible, I have tried to find compatible drivers based on the layout
>> of
>> registers. However, I have not tested most of this functionality, and most
>> devices should be
On 2/4/20 6:21 AM, Bin Meng wrote:
> Hi Sean,
>
> On Mon, Feb 3, 2020 at 4:05 AM Sean Anderson wrote:
>>
>> Some older processors (notably the Kendryte K210) use an older version of the
>> RISC-V privileged specification. The primary changes between the old and new
>> are
>> in virtual
On 2/4/20 6:06 AM, Bin Meng wrote:
> Hi Sean,
>
> On Mon, Feb 3, 2020 at 4:01 AM Sean Anderson wrote:
>> +Required properties:
>> +- compatible: should contain "syscon-reset"
>
> Shouldn't we follow the same generic "syscon-reboot" device bindings
> defined in the Linux kernel?
> See
On 2/4/20 5:49 AM, Bin Meng wrote:
> Hi Sean,
>
> On Mon, Jan 20, 2020 at 7:13 AM Sean Anderson wrote:
>>
>> Currently, the sf command will probe anything attached to an spi bus,
>> regardless
>> of whether it is UCLASS_SPI_FLASH. This came up when testing the mmc_spi
>> driver,
>
> Did you
On 2/4/20 5:36 AM, Bin Meng wrote:
> On Mon, Feb 3, 2020 at 1:40 AM Sean Anderson wrote:
> I believe both 2 patches in this series are needed by "riscv: Add
> Sipeed Maix support" series?
> If yes, I think you can just put 2 patches into the same series, to
> give people a good context next time.
Hi Walter,
Thanks for the patch.
One comment below.
On Wed, Jan 29, 2020 at 10:58:07AM -0300, Walter Lozano wrote:
> Make an additional step to add full DM support to mx6cuboxi, including its
> support for SPL
>
> With this new configuration SPL image is 50 KB, higher than the
> 38 KB from
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