Dear Wolfgang,
> From: Wolfgang Denk
> Sent: mercredi 1 avril 2020 13:19
>
> Dear Patrick,
>
> In message
> <20200331180330.3.I8f6df6d28ce5b4b601ced711af3699d95e1576fb@changeid>
> you wrote:
> > Serial number is first checked and, in case of mismatch, all
> > environment variables are reset to
mt7531 is a 7-ports switch with 5 embedded giga phys, and uses the same
MAC design of mt7530. The cpu port6 supports SGMII only. The cpu port5
supports RGMII or SGMII in different model.
mt7531 is connected to mt7622 via both RGMII and SGMII interfaces.
In this patch, mt7531 cpu port5 or port6 is
On 07. 04. 20 4:40, Simon Glass wrote:
> Move this uncommon header out of the common header.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/arm/cpu/arm1136/mx35/timer.c | 1 +
> arch/arm/cpu/arm926ejs/mx25/timer.c | 1 +
> arch/arm/cpu/arm926ejs/mx27/timer.c | 1 +
> arch/arm/cpu/a
Dear Simon,
In message
<20200406203250.2.Ia0f8528ae0e9e3ead7d99891b46cccaef5859295@changeid> you wrote:
> Move this uncommon header out of the common header.
>
> Fix up some style problems in flash.h while we are here.
Actually your coding style fixes are anywhere else as well.
I think this shou
Hi Michal,
I did not revert b8e25ef16a58 ("mmc: sdhci: Read capabilities register1 and
update host caps") since without those changes, the UHS caps would not disabled
if you forgot to add the "no-1-8-v" property.
I think relying on the voltage configuration instead is worth keeping.
Best Regard
Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes
is not evaluated. This results in the bus width staying at its default
value (4 bit in HS200 mode).
Fix this by calling mmc_of_parse. This function also checks for the
"no-1-8-v" and "max-frequency" entries. Remove the handling of t
On 4/7/20 4:07 PM, Patrick Delaunay wrote:
> Remove the unnecessary inversion on the eth_env_set_enetaddr() result which
> only make complex the code of setup_mac_address() and display an invalid
> value in the associated pr_err.
>
> Signed-off-by: Patrick Delaunay
Reviewed-by: Marek Vasut
Remove the unnecessary inversion on the eth_env_set_enetaddr() result which
only make complex the code of setup_mac_address() and display an invalid
value in the associated pr_err.
Signed-off-by: Patrick Delaunay
---
arch/arm/mach-stm32mp/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 delet
Dear,
> From: Marek Vasut
> Sent: mardi 7 avril 2020 12:04
>
> On 4/7/20 11:49 AM, Patrick DELAUNAY wrote:
> > Dear Marek,
>
> Hi,
>
> > To complete my test and to check the cache management in the driver,
> >
> > I test the sequence (CONFIG_SYS_NONCACHED_MEMORY is activated):
> >
> > 1) ping
Dear Marek,
> From: Marek Vasut
> Sent: mercredi 1 avril 2020 01:48
>
> The DHCOR board does exist in multiple variants with different DDR3 DRAM
> sizes. To cater for all of them, implement DDR3 code handling.
> There are two GPIOs which code the DRAM size populated on the SoM, read
> them out a
Hi Marek,
> From: Marek Vasut
> Sent: mercredi 1 avril 2020 01:48
>
> Add support for multiple DRAM configuration subnodes, while retaining the
> support for a single flat DRAM configuration node. This is useful on systems
> which can be manufactured in multiple configurations and where the DRAM
Dear Marek,
> From: Marek Vasut
> Sent: mercredi 1 avril 2020 01:48
>
> Adjust the DDR configuration dtsi such that they only generate the DRAM
> configuration node, the DDR controller node is moved into the stm32mp157-u-
> boot.dtsi itself. This permits including multiple DDR configuration dts
Hi Tom,
please pull the following changes for v2020.07.
Travis and gitlab look good.
https://travis-ci.org/github/michalsimek/u-boot/builds/671573769
https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze/pipelines/2633
The major change is switch Zynq to single platform as I have done for
Zyn
The eeprom_i2c_bus is not used outside of this file, make it static.
Signed-off-by: Marek Vasut
Cc: Heiko Schocher
Cc: Tom Rini
---
cmd/eeprom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/cmd/eeprom.c b/cmd/eeprom.c
index 667149e2d4..792415ef93 100644
--- a/cmd/eeprom.
The Juno board features a standard compliant EHCI/OHCI USB host
controller pair, which we can just enable.
The platform data is taken from the device tree.
This allows to use USB mass storage (the only storage on a Juno r0)
for loading.
At least on my board USB seems a bit flaky, I need two "usb
So far the Juno board wasn't implementing reset. Let's just use the
already existing PSCI_RESET based method to avoid any extra code.
Signed-off-by: Andre Przywara
Acked-by: Liviu Dudau
---
arch/arm/Kconfig | 2 ++
board/armltd/vexpress64/vexpress64.c | 4 +---
2 files chang
CONFIG_SEMIHOSTING is selected for the VFP target by the means of
Kconfig already, there is no need to check this in the header file.
Signed-off-by: Andre Przywara
---
include/configs/vexpress_aemv8a.h | 6 --
1 file changed, 6 deletions(-)
diff --git a/include/configs/vexpress_aemv8a.h
b/
The Arm Juno board was still somewhat stuck in "hardcoded land", even
though there are stable DTs around, and one happens to actually be on
the memory mapped NOR flash.
Enable the configuration options to let the board use OF_CONTROL, and
add a routine to find the address of the DTB partition in N
Even though the PL011 UART driver claims to be DM compliant, it does not
really a good job with parsing DT nodes. U-Boot seems to adhere to a
non-standard binding, either requiring to have a "skip-init" property in
the node, or to have an extra "clock" property holding the base
*frequency* value fo
The UART base clock rate was typo-ed in the header file, probably because
the reference (the Linux .dts) was also wrong[1].
Fix the number to make the baud rate more correct.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
Hi,
a small update, addressing Tom's comments on patch 1 (which is the only
one changed). This removes fdt_high and initrd_high, to allow U-Boot
moving those images around.
Despite the fix nature of patch 1, this changes some behaviour, so it's
definitely *NOT* 2020.04 material anymore.
Cheers,
The U-Boot documentation explains that variables ending with "_r" hold
addresses in DRAM, while those without that ending point to flash/ROM.
The default variables for the Juno board pointing to the kernel and DTB
load addresses were not complying with this scheme: they lack the
extension, but poin
Hi,
On 06. 04. 20 16:35, Benedikt Grassl wrote:
> Currently, the entry "bus-width = <8>" in the ZynqMP's sdhci nodes
> is not evaluated. This results in the bus width staying at its default
> value (4 bit in HS200 mode).
> Fix this by parsing the device tree while probing.
>
> Signed-off-by: Bene
On Tue, Apr 7, 2020 at 12:46 AM Tom Rini wrote:
>
> Hey all,
>
> As I said in a separate email this morning, I'm pushing back the release
> a week. There's been some regression reports the last week, and fixes
> build-tested last night and pushed this morning. So I'm going to wait a
> week to re
On 4/7/20 11:49 AM, Patrick DELAUNAY wrote:
> Dear Marek,
Hi,
> To complete my test and to check the cache management in the driver,
>
> I test the sequence (CONFIG_SYS_NONCACHED_MEMORY is activated):
>
> 1) ping with dcache ON: Always OK
>
> STM32MP> dhcp
> STM32MP> ping 91.162.57.93
>
> 2)
Dear Marek,
> From: Patrick DELAUNAY
> Sent: lundi 6 avril 2020 17:11
>
> Dear Marek,
>
> > From: Marek Vasut
> > Sent: lundi 23 mars 2020 02:45
> >
> > The RX descriptor field 3 should contain only OWN and BUF1V bits
> > before being used for receiving data by the DMA engine. However, right
>
Hi Pragnesh,
On Sun, Mar 29, 2020 at 10:36 PM Pragnesh Patel
wrote:
>
> This series add support for SPL to FU540.U-Boot SPL can boot from
> L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
> U-Boot proper from MMC devices.
>
> How to test this patch:
> 1) Go to OpenSBI-dir : make
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki
---
Note: On top of https://patchwork.ozl
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
Right now the board doesn't support the environment,
so the U-Boot environment and ESP partitions will
add in future.
partition layout:
PartStart LBA End LBA
On Tue, Apr 7, 2020 at 1:40 PM Pragnesh Patel wrote:
>
> Hi Jagan,
>
> >-Original Message-
> >From: Jagan Teki
> >Sent: 07 April 2020 13:32
> >To: Pragnesh Patel
> >Cc: U-Boot-Denx ; Atish Patra
> >; palmerdabb...@google.com; Bin Meng
> >; Paul Walmsley ; Troy
> >Benjegerdes ; Anup Patel
On 07. 04. 20 11:16, Matwey V. Kornilov wrote:
> вт, 7 апр. 2020 г. в 12:01, Michal Simek :
>>
>> On 07. 04. 20 9:58, Matwey V. Kornilov wrote:
>>> пн, 6 апр. 2020 г. в 12:41, Michal Simek :
Hi,
On 06. 04. 20 10:14, Matwey V. Kornilov wrote:
> 06.04.2020 11:12, Matwey V. Kor
вт, 7 апр. 2020 г. в 12:01, Michal Simek :
>
> On 07. 04. 20 9:58, Matwey V. Kornilov wrote:
> > пн, 6 апр. 2020 г. в 12:41, Michal Simek :
> >>
> >> Hi,
> >>
> >> On 06. 04. 20 10:14, Matwey V. Kornilov wrote:
> >>> 06.04.2020 11:12, Matwey V. Kornilov пишет:
> Hello,
>
> I am runni
On 4/7/20 8:29 AM, Rayagonda Kokatanur wrote:
[...]
> +static int xhci_brcm_probe(struct udevice *dev)
> +{
> + struct xhci_hccr *hcd;
> + struct xhci_hcor *hcor;
> + struct brcm_xhci_platdata *plat = dev_get_platdata(dev);
> + uintptr_t hc_base;
> + int len, ret = 0;
Reverse x
Adjust the DDR configuration dtsi such that they only generate the
DRAM configuration node, the DDR controller node is moved into the
stm32mp157-u-boot.dtsi itself. This permits including multiple DDR
configuration dtsi files in board DT.
Signed-off-by: Marek Vasut
Cc: Manivannan Sadhasivam
Cc:
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.
Signed-off-by: Marek Vasut
Cc
Add support for multiple DRAM configuration subnodes, while retaining
the support for a single flat DRAM configuration node. This is useful
on systems which can be manufactured in multiple configurations and
where the DRAM configuration can be determined at runtime.
The code is augmented by a func
The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.
Signed-off-by: Marek Vasut
Cc: Manivannan Sadhasivam
Cc
Add weak implementation of board_early_init_f() hook into the
STM32MP1 SPL. This can be used to read out e.g. configuration
straps before initializing the DRAM.
Signed-off-by: Marek Vasut
Cc: Manivannan Sadhasivam
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/mach-stm32mp/spl.c | 11 +
Add default U-Boot configuration for the DHCOR SoM on AV96 board.
Signed-off-by: Marek Vasut
Cc: Manivannan Sadhasivam
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
configs/stm32mp15_dhcor_basic_defconfig | 136
1 file changed, 136 insertions(+)
create mode 100644 con
On 4/7/20 9:51 AM, Patrick DELAUNAY wrote:
> Dear Marek,
Hi,
[...]
>> b/board/dhelectronics/dh_stm32mp1/board.c
>> index a3458a2623..36b8652521 100644
>> --- a/board/dhelectronics/dh_stm32mp1/board.c
>> +++ b/board/dhelectronics/dh_stm32mp1/board.c
>> @@ -133,6 +133,90 @@ int checkboard(void)
>>
On 07. 04. 20 9:58, Matwey V. Kornilov wrote:
> пн, 6 апр. 2020 г. в 12:41, Michal Simek :
>>
>> Hi,
>>
>> On 06. 04. 20 10:14, Matwey V. Kornilov wrote:
>>> 06.04.2020 11:12, Matwey V. Kornilov пишет:
Hello,
I am running u-boot 2020.04-rc4-00100-g74bf17db39 with
zynq_z_turn_def
Hi Jagan,
>-Original Message-
>From: Jagan Teki
>Sent: 07 April 2020 13:32
>To: Pragnesh Patel
>Cc: U-Boot-Denx ; Atish Patra
>; palmerdabb...@google.com; Bin Meng
>; Paul Walmsley ; Troy
>Benjegerdes ; Anup Patel
>; Sagar Kadam ; Rick Chen
>; Palmer Dabbelt
>Subject: Re: [PATCH v6 02/1
On Thu, Apr 2, 2020 at 3:47 PM Pragnesh Patel wrote:
>
> Hi Jagan,
>
> >-Original Message-
> >From: Jagan Teki
> >Sent: 02 April 2020 14:59
> >To: Pragnesh Patel
> >Cc: U-Boot-Denx ; Atish Patra
> >; palmerdabb...@google.com; Bin Meng
> >; Paul Walmsley ; Troy
> >Benjegerdes ; Anup Patel
пн, 6 апр. 2020 г. в 12:41, Michal Simek :
>
> Hi,
>
> On 06. 04. 20 10:14, Matwey V. Kornilov wrote:
> > 06.04.2020 11:12, Matwey V. Kornilov пишет:
> >> Hello,
> >>
> >> I am running u-boot 2020.04-rc4-00100-g74bf17db39 with
> >> zynq_z_turn_defconfig configuration on MYIR Z-Turn board.
> >> And
Dear Marek,
> From: Marek Vasut
> Sent: mercredi 1 avril 2020 01:48
>
> The AV96 board does exist in multiple variants. To cater for all of them,
> implement
> board code handling. There are two GPIOs which code the type of the board,
> read
> them out and use the value to pick the correct dev
Adding "u-boot,dm-pre-reloc" and enable CONFIG_SPL_CACHE
to enable cache driver in SPL.
This fixed error below in SPL:
cache controller driver NOT found!
Signed-off-by: Ley Foon Tan
---
v2: Enable SPL_CACHE in Kconfig instead of defconfig.
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 4
Move Uboot specific properties to *u-boot.dtsi files.
Preparation to sync Arria 10 device tree from Linux.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_arria10-u-boot.dtsi | 123 ++
arch/arm/dts/socfpga_arria10.dtsi | 28
.../arm/dts/socfpga_arria10
This patchset mainly to update Arria 10 dts/dtsi from Linux v5.6.2.
All uboot specific properties are moved to *u-boot.dtsi.
The 3rd patch is to fix missing u-boot,dm-pre-reloc for L2 cache node
and enable cache driver in SPL.
v2:
- Add Linux commit ID in commit description.
- Enable CONFIG_SPL_C
Update these 3 files from Linux:.
- socfpga_arria10.dtsi (Commit ID c1459a9d7e92)
- socfpga_arria10_socdk.dtsi (Commit ID d9b9f805ee2b)
- socfpga_arria10_socdk_sdmmc.dts (Commit ID 17808d445b6f)
Change in socfpga_arria10.dtsi:
- Add clkmgr label, so that can reference to it in u-boot.dtsi.
Change
On 07/04/20 1:02 pm, Lokesh Vutla wrote:
>
>
> On 02/04/20 6:59 PM, Vignesh Raghavendra wrote:
>> In 1 bit mode OSPI can work at upto 50MHz, this provides before write
>> performance. Therefore increase frequency from 40MHz to 50MHz
>>
>> Signed-off-by: Vignesh Raghavendra
>
> Fixed the $com
On 02/04/20 6:59 PM, Vignesh Raghavendra wrote:
> In 1 bit mode OSPI can work at upto 50MHz, this provides before write
> performance. Therefore increase frequency from 40MHz to 50MHz
>
> Signed-off-by: Vignesh Raghavendra
Fixed the $commit in both the patches and applied to u-boot-ti.
Thank
On 26/03/20 8:56 PM, Adam Ford wrote:
> With the converstion of SMC911x to DM, this can facilitate the omap3
> boards from LogicPD (now called Beacon EmbeddedWorks) to be converted.
> There isn't a clean solution to doing this in phases, so the boards are
> all being done together to avoid break
On 25/03/20 12:15 PM, Moses Christopher wrote:
> The following patches ensure that the Bosch Guardian Board is updated with
> the latest feature additions and improvements made in the recent past
>
> On High Level, the following are achieved:
> * Proper handling of USB-ETH Boot in SPL stage
>
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