From: Bin Meng
At present fdtdec_add_reserved_memory() calls fdtdec_get_addr_size()
to get address and size for the subnodes of /reserved-memory node.
We should honor #address-cells and #size-cells properties in the
parent node.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no change
From: Bin Meng
fdtdec_get_addr_size() expects size is of type 'fdt_size_t', and
return value is of type 'fdt_addr_t'. Adjust their types accordingly.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
lib/fdtdec.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(
From: Bin Meng
It should be "writable".
Signed-off-by: Bin Meng
---
(no changes since v1)
test/dm/fdtdec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index c2f7b94..999d712 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -2
From: Bin Meng
This adds a test case to test the functionality of the fdtdec API
fdtdec_add_reserved_memory().
Signed-off-by: Bin Meng
---
Changes in v3:
- correct typo in the comments, and some minor rewording
test/dm/fdtdec.c | 69
1
From: Bin Meng
Add DECLARE_GLOBAL_DATA_PTR since it is referenced in the test codes.
Signed-off-by: Bin Meng
---
(no changes since v1)
test/dm/fdtdec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index b2f75b5..c2f7b94 100644
--- a/test/dm/fdtdec
Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.
After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that
On 6/9/20 11:38 PM, Robin Murphy wrote:
> On 2020-06-09 15:01, Jagan Teki wrote:
>> SDHCI HISPD bits need to be configured based on desired mmc
>> timings mode and some HISPD quirks.
>>
>> So, handle the HISPD bit based on the mmc computed selected
>> mode(timing parameter) rather than fixed mmc ca
Current mxc_gpio DM driver allocates the platdata in bind function to
handle both OF_CONTROL enabled case and disabled case. This implementation
puts the devfdt_get_addr in bind, which introduces much overhead especially
in board_f phase.
Change the driver to a common way for handling the cases by
Remove the child device binding codes for clk and iomux nodes, because
the misc uclass has added such operation in post-bind. If we keep the
codes in scu bind, child devices will be created twices. Find the
problem by "dm uclass" command.
uclass 24: clk
0 * clk @ fce22380, seq 0, (req -1)
1
Current driver calls the devfdt_get_addr to get the base address
of lpi2c controller in each sub-functions. Since the devfdt_get_addr
accesses the DTB and translate the address, it introduces much
overhead.
Improve the codes to use private variable which has recorded the
base address from probe.
S
Current aliases missed gpio0 node, and this node shoud be
aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we
will get below message when running "gpio status" command, and
see the reason by "dm uclass".
=> gpio status
Device 'gpio@5d09': seq 0 is in use by 'gpio@5d08'
Device 'gp
Since the i.MX8 GPIO banks are indexed from 0 not 1 on other i.MX
platforms, so we have to adjust the index accordingly.
Signed-off-by: Adrian Alonso
Signed-off-by: Ye Li
---
drivers/gpio/mxc_gpio.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpio/mxc_gpio.c
From: Bin Meng
This adds a test case to test the functionality of the fdtdec API
fdtdec_add_reserved_memory().
Signed-off-by: Bin Meng
---
(no changes since v1)
test/dm/fdtdec.c | 69
1 file changed, 69 insertions(+)
diff --git a/test
From: Bin Meng
Add DECLARE_GLOBAL_DATA_PTR since it is referenced in the test codes.
Signed-off-by: Bin Meng
---
(no changes since v1)
test/dm/fdtdec.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index b2f75b5..c2f7b94 100644
--- a/test/dm/fdtdec
From: Bin Meng
It should be "writable".
Signed-off-by: Bin Meng
---
(no changes since v1)
test/dm/fdtdec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c
index c2f7b94..999d712 100644
--- a/test/dm/fdtdec.c
+++ b/test/dm/fdtdec.c
@@ -2
From: Bin Meng
At present fdtdec_add_reserved_memory() calls fdtdec_get_addr_size()
to get address and size for the subnodes of /reserved-memory node.
We should honor #address-cells and #size-cells properties in the
parent node.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no change
From: Bin Meng
fdtdec_get_addr_size() expects size is of type 'fdt_size_t', and
return value is of type 'fdt_addr_t'. Adjust their types accordingly.
Signed-off-by: Bin Meng
Reviewed-by: Simon Glass
---
(no changes since v1)
lib/fdtdec.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(
> Subject: [PATCH] Convert CONFIG_MXC_UART to Kconfig
>
> This converts the following to Kconfig:
>CONFIG_MXC_UART
>
> Signed-off-by: Tom Rini
> ---
Acked-by: Peng Fan
Hi Wolfgang,
On Tue, 19 May 2020 at 05:58, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
> > Betreff: [PATCH v2 11/35] acpi: Support generation of I2C descriptor
> >
> > Add a function to write a GPIO descriptor to the generated ACPI code.
> >
> > Signed-off-by: Sim
Hi Wolfgang,
On Thu, 14 May 2020 at 02:32, Wolfgang Wallner
wrote:
>
> Hi Simon,
>
> -"Simon Glass" schrieb: -
> > Betreff: [PATCH v2 05/35] acpi: Support generation of ACPI code
> >
> > Add a new file to handle generating ACPI code programatically. This is
> > used when information must
On HS devices the access to SA2UL is restricted on the non-secure
ARM side, disable the node in DT to prevent firewall violations.
We used to only disable the TRNG but now that we have full SA2UL
support in Linux, in which TRNG is a sub-module, disable both
by disabling the parent SA2UL node.
Sign
Hi Mylene,
Thanks for you patch.
On 5/6/20 05:01, Mylène Josserand wrote:
Add a new error message in case the size of data written
are shorter than the one expected.
Currently, it will lead to the following error message:
"mkimage: Write error on uImage: Success"
This is not explicit when
Hi all
On Tue, Jun 9, 2020 at 6:13 AM Bin Meng wrote:
>
> Hi André,
>
> On Mon, Jun 8, 2020 at 9:52 PM André Przywara wrote:
> >
> > On 07/06/2020 12:22, Jagan Teki wrote:
> >
> > Hi,
> >
> > (CC: ing Mark)
> >
> > Without looking to deep, I think invalidating the cache might be the
> > right th
On 6/9/20 7:14 AM, AKASHI Takahiro wrote:
> In this commit, efi_signature_verify(with_sigdb) will be re-implemented
> using pcks7_verify_one() in order to support certificates chain, where
> the signer's certificate will be signed by an intermediate CA (certificate
> authority) and the latter's cer
On Tue, Jun 9, 2020 at 1:23 PM Otavio Salvador wrote:
>
> We need to change the environment offset to avoid corrupting the U-Boot
> binary when saving it.
>
> Signed-off-by: Otavio Salvador
Reviewed-by: Fabio Estevam
On Tue, Jun 9, 2020 at 1:23 PM Otavio Salvador wrote:
>
> This fixes the boot from USB loader, which is critical to easy the
> manufacture process.
>
> Signed-off-by: Otavio Salvador
Reviewed-by: Fabio Estevam
We need to change the environment offset to avoid corrupting the U-Boot
binary when saving it.
Signed-off-by: Otavio Salvador
---
Changes in v2:
- rework commit log
configs/mx6ul_14x14_evk_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/mx6ul_14x14_evk_def
This fixes the boot from USB loader, which is critical to easy the
manufacture process.
Signed-off-by: Otavio Salvador
---
(no changes since v1)
configs/mx6ul_14x14_evk_defconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/configs/mx6ul_14x14_evk_defconfig
b/configs/mx6ul
Hi Otavio,
On Tue, Jun 9, 2020 at 12:47 PM Otavio Salvador wrote:
Please always include a commit text.
> Signed-off-by: Otavio Salvador
> ---
>
> configs/mx6ul_14x14_evk_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/configs/mx6ul_14x14_evk_defconfig
> b/configs/mx6ul_14x
Hi Otavio,
Thanks for the fix.
Please change the Subject from:
mx6ul_14x14_evk: Change environment offset to overlap with U-Boot
to
mx6ul_14x14_evk: Change environment offset to avoid overlap with U-Boot
as we want to avoid the overlap :-)
On Tue, Jun 9, 2020 at 12:47 PM Otavio Salvador wro
On Tue, Jun 9, 2020 at 12:46 PM Otavio Salvador wrote:
>
> This fixes the boot from USB loader, which is critical to easy the
> manufacture process.
>
> Signed-off-by: Otavio Salvador
Reviewed-by: Fabio Estevam
We need to change the environment offset to avoid corrupting the U-Boot
binary when saving it.
Signed-off-by: Otavio Salvador
---
configs/mx6ul_14x14_evk_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/mx6ul_14x14_evk_defconfig
b/configs/mx6ul_14x14_evk_de
Signed-off-by: Otavio Salvador
---
configs/mx6ul_14x14_evk_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mx6ul_14x14_evk_defconfig
b/configs/mx6ul_14x14_evk_defconfig
index cad766443c2..a2cb3215d44 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_
This fixes the boot from USB loader, which is critical to easy the
manufacture process.
Signed-off-by: Otavio Salvador
---
configs/mx6ul_14x14_evk_defconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/configs/mx6ul_14x14_evk_defconfig
b/configs/mx6ul_14x14_evk_defconfig
in
On Tue, Jun 09, 2020 at 03:50:09AM +0200, Marek Vasut wrote:
> On 6/9/20 12:57 AM, Tom Rini wrote:
> > On Mon, Jun 08, 2020 at 11:45:18PM +0200, Marek Vasut wrote:
> >> On 6/6/20 6:24 PM, Tom Rini wrote:
> >>> On Sat, Jun 06, 2020 at 04:54:52PM +0200, Marek Vasut wrote:
> On 6/5/20 11:11 PM, T
0400)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/u-boot-imx-20200609
>
> for you to fetch changes up to 385429680106f8612386e26564f69dccdd110620:
>
> Revert "imx: rom api: fix image offset com
This converts the following to Kconfig:
CONFIG_MXC_UART
Signed-off-by: Tom Rini
---
configs/apalis_imx6_defconfig | 1 +
configs/apf27_defconfig | 1 +
configs/cgtqmx6eval_defconfig | 1 +
configs/cl-som-imx7_defconfig | 1 +
configs/cm_fx
On 2020-06-09 15:01, Jagan Teki wrote:
SDHCI HISPD bits need to be configured based on desired mmc
timings mode and some HISPD quirks.
So, handle the HISPD bit based on the mmc computed selected
mode(timing parameter) rather than fixed mmc card clock
frequency.
Linux handle the HISPD similar li
On 6/9/20 10:53 AM, Hayes Wang wrote:
> The original rtl_clear_bp() is used to clear the firmware of both
> PLA and USB MCU. The new one could clear the firmware of PLA or
> USB independently. It is unnecessary to clear firmware, if there
> is no one to be updated.
>
> Signed-off-by: Hayes Wang
>
On 6/9/20 10:53 AM, Hayes Wang wrote:
> This is used to support RTL8153B and RTL8154B.
[...]
> + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
> +ocp_data);
> + break;
> +
> + case RTL_VER_08:
> + case RTL_VER_09:
> +
On 6/9/20 10:53 AM, Hayes Wang wrote:
> Some settings of PHY have to work after resetting PHY.
>
> Signed-off-by: Hayes Wang
> ---
> drivers/usb/eth/r8152.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
> index dbb1721
On 6/9/20 10:53 AM, Hayes Wang wrote:
> Reset bmu after disabling Tx/Rx. This is used to clear the FIFO of
> Tx/Rx. The remained data may be transferred after Tx/Rx is re-enabled.
> And it results in garbage data.
>
> Signed-off-by: Hayes Wang
> ---
> drivers/usb/eth/r8152.c | 14 ++
Enable PCI/NVME for M.2 Slot on RockPI-4 boards.
=> nvme info
Device 0: Vendor: 0x144d Rev: 2B2QEXM7 Prod: S4EUNG0MC10012Y
Type: Hard Disk
Capacity: 238475.1 MB = 232.8 GB (488397168 x 512)
Cc: Tom Cubie
Signed-off-by: Jagan Teki
---
configs/rock-pi-4-rk3399_defconfig |
Enable USB3.0 Host support for RockPI-4 boards.
Note that the Upper USB3.0 port is marked as otg and
lower USB3.0 port marked as host, so this below log
capture when USB3.0 mass storage plug in at lower
USB 3.0 port.
Log:
Bus usb@fe38: USB EHCI 1.00
Bus usb@fe3c: USB EHCI 1.00
Bus dwc3: u
Enable DWC3 core, gadget for roc-rk3399-pc board.
This would help to use fastboot by default.
Signed-off-by: Jagan Teki
Tested-by: Suniel Mahesh
---
configs/roc-pc-rk3399_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/roc-pc-rk3399_defconfig b/configs/roc-pc-rk3399_de
SDHCI HISPD bits need to be configured based on desired mmc
timings mode and some HISPD quirks.
So, handle the HISPD bit based on the mmc computed selected
mode(timing parameter) rather than fixed mmc card clock
frequency.
Linux handle the HISPD similar like this in below commit,
commit <501639b
Convert to DM_ETH to avoid board removal from the project.
Signed-off-by: Fabio Estevam
---
configs/mx6ull_14x14_evk_plugin_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig
b/configs/mx6ull_14x14_evk_plugin_defconfig
index 2811d868ac.
Convert to DM_ETH to avoid board removal from the project.
Signed-off-by: Fabio Estevam
---
configs/mx6slevk_spinor_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/mx6slevk_spinor_defconfig
b/configs/mx6slevk_spinor_defconfig
index 4d348df691..67de522dd8 100644
--- a/co
Convert to DM_ETH to avoid board removal from the project.
Signed-off-by: Fabio Estevam
---
configs/mx6slevk_spl_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 3a0ae92bf2..143718a6a7 100644
--- a/configs/mx6s
> On 09.06.2020, at 15:37, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> The vsc8530/8531/8540/8541 phys have a configurable clock output that
> can emit 25, 50 and 125 MHz rates, which in turn may be needed for
> stable network connections.
>
> This follows a similar change introduced
> On 09.06.2020, at 15:37, Heiko Stuebner wrote:
>
> From: Heiko Stuebner
>
> The Linux kernel does set the clock delays to
> - 0.2 ns (their default, and lowest, hardware value) if delays should
> not be enabled
> - 2.0 ns (which causes the data to be sampled at exactly half way between
>
From: Heiko Stuebner
The Linux kernel does set the clock delays to
- 0.2 ns (their default, and lowest, hardware value) if delays should
not be enabled
- 2.0 ns (which causes the data to be sampled at exactly half way between
clock transitions at 1000 Mbps) if delays should be enabled
dependi
From: Heiko Stuebner
The vsc8530/8531/8540/8541 phys have a configurable clock output that
can emit 25, 50 and 125 MHz rates, which in turn may be needed for
stable network connections.
This follows a similar change introduced into the Linux kernel at
https://lore.kernel.org/netdev/20200609133
tags/u-boot-imx-20200609
for you to fetch changes up to 385429680106f8612386e26564f69dccdd110620:
Revert "imx: rom api: fix image offset computation" (2020-06-09
11:19:55 +0200)
Fixes for 2020.07
---
From: Aaron Williams
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../include/mach/cvmx/cvmx-lmcx-defs.h| 4580 +
1 file changed, 4580 inser
W dniu 09.06.2020 o 00:50, Peter Robinson pisze:
> Enable the rng so UEFI can provide entropy for KASLR
>
> Signed-off-by: Peter Robinson
> ---
> arch/arm/dts/rk3399-pinebook-pro-u-boot.dtsi | 4
> arch/arm/dts/rk3399-rockpro64-u-boot.dtsi| 4
> configs/pinebook-pro-rk3399_defconfi
On 6/5/20 6:45 PM, Michal Simek wrote:
> s/booot/boot/g
>
> The first ase is booot instead of boot and second u-booot instead of
> u-boot.
>
> Signed-off-by: Michal Simek
Reviewed-by: Jaehoon Chung
> ---
>
> board/freescale/p1010rdb/README.P1010RDB-PA | 2 +-
> cmd/mmc.c
Hi,
On 6/8/20 10:16 PM, Michal Simek wrote:
> On 27. 05. 20 8:44, Jaehoon Chung wrote:
>> Hi
>>
>> On 5/22/20 7:44 PM, Michal Simek wrote:
>>> From: Ashok Reddy Soma
>>>
>>> This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830.
>>>
>>> This is partial revert of the above commit.
>>>
>>> m
>-Original Message-
>From: Bin Meng
>Sent: 09 June 2020 08:58
>To: Pragnesh Patel ; Rick Chen
>; U-Boot Mailing List
>Cc: Bin Meng
>Subject: [PATCH 2/2] riscv: fu540: dts: Correct reg size of otp and dmc nodes
>
>[External Email] Do not click links or attachments unless you recognize the
The correct setting for the RGMII ports on LS1012ARDB is to
enable delay on both Rx and Tx so the interface mode used should
be PHY_INTERFACE_MODE_RGMII_ID
Signed-off-by: Chaitanya Sakinam
Signed-off-by: Anji J
---
board/freescale/ls1012ardb/eth.c | 2 +-
drivers/net/pfe_eth/pfe_eth.c| 2 +-
Am Dienstag, 9. Juni 2020, 12:22:36 CEST schrieb Heinrich Schuchardt:
> On 09.06.20 12:11, Heiko Stübner wrote:
> > Hi Akashi,
> >
> > Am Dienstag, 9. Juni 2020, 11:22:35 CEST schrieb AKASHI Takahiro:
> >> Heinrich,
> >>
> >> On Tue, Jun 09, 2020 at 03:54:44AM +, Heinrich Schuchardt wrote:
> >>
From: Laurentiu Tudor
Move the pci device related fdt fixup in a function in order to
re-use it in a following patch. While at it, improve the error
handling.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 58 -
1 file changed, 33 insertion
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add an u-boot env var and a device tree property (to be used for
example in more s
From: Laurentiu Tudor
In the current implementation, u-boot creates iommu mappings only
for PCI devices enumarated at boot time thus does not take into
account more dynamic scenarios such as SR-IOV or PCI hot-plug.
Add support for specifying extra IOMMU mappings for PCI
controllers through a spec
From: Laurentiu Tudor
Fix duplication of this code by placing it in a common function.
Furthermore, the resulting function will be re-used in upcoming
patches.
Signed-off-by: Laurentiu Tudor
---
drivers/pci/pcie_layerscape_fixup.c | 87 ++---
1 file changed, 30 insertio
Move the default eMMC boot partition index used for SPL load to a weak
function. So we can override it in iMX8 specified codes.
Because on iMX8 when the emmc regular boot is from boot part0/1, ROM will
switch to the other boot part for secondary boot. So we can't directly
use the boot part index in
On i.MX8QM B0 and i.MX8QXP C0, ROM supports to boot from secondary
container set when either booting from primary container set is failed
or secondary container set has higher SW version.
Add the support to SPL to load u-boot container from secondary set
when ROM boots from the secondary set. Usin
>-Original Message-
>From: Bin Meng
>Sent: 09 June 2020 08:58
>To: Pragnesh Patel ; Rick Chen
>; U-Boot Mailing List
>Cc: Bin Meng
>Subject: [PATCH 1/2] riscv: fu540: dts: Remove the unnecessary space in the
>cpu2_intc node
>
>[External Email] Do not click links or attachments unless you
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
---
arch/arm/include/asm/arch-imx8/sci/rpc.h | 1 +
arch/arm/include/asm/arch-imx8/sci
On 09.06.20 07:14, AKASHI Takahiro wrote:
> In this test case, an image may have a signature with additional
> intermediate certificates. A chain of trust will be followed and all
> the certificates in the middle of chain must be verified before loading.
>
> Signed-off-by: AKASHI Takahiro
> ---
>
On 09.06.20 07:13, AKASHI Takahiro wrote:
> This function will be called from x509_check_for_self_signed() and
> pkcs7_verify_one(), which will be imported from linux in a later patch.
>
> While it does exist in linux code and has a similar functionality of
> rsa_verify(), it calls further linux-sp
On 09.06.20 12:11, Heiko Stübner wrote:
> Hi Akashi,
>
> Am Dienstag, 9. Juni 2020, 11:22:35 CEST schrieb AKASHI Takahiro:
>> Heinrich,
>>
>> On Tue, Jun 09, 2020 at 03:54:44AM +, Heinrich Schuchardt wrote:
>>> Am June 9, 2020 1:42:14 AM UTC schrieb AKASHI Takahiro
>>> :
Heinrich,
>>
On 25.05.20 22:43, Philipp Tomsich wrote:
>
>
>> On 22.05.2020, at 16:19, Heiko Stuebner wrote:
>>
>> From: Heiko Stuebner
>>
>> When calculating rrtmp/rr rsa_gen_key_prop() tries to make
>> (((rlen + 31) >> 5) + 1) steps in the rr uint32_t array and
>> (((rlen + 7) >> 3) + 1) / 4 steps in uint32
Hi Akashi,
Am Dienstag, 9. Juni 2020, 11:22:35 CEST schrieb AKASHI Takahiro:
> Heinrich,
>
> On Tue, Jun 09, 2020 at 03:54:44AM +, Heinrich Schuchardt wrote:
> > Am June 9, 2020 1:42:14 AM UTC schrieb AKASHI Takahiro
> > :
> > >Heinrich,
> > >
> > >On Mon, Jun 08, 2020 at 11:08:53PM +0200, H
On 09.06.20 11:35, Christian Gmeiner wrote:
> Hi
>
> Am Di., 9. Juni 2020 um 09:19 Uhr schrieb Heinrich Schuchardt
> :
>>
>> On 09.06.20 09:09, Christian Gmeiner wrote:
>>> According to the FAT specification it is valid to have files with an
>>> attribute value of 0x0. This fixes a regression where
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, June 9, 2020 5:53 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Ley Foon Tan ; See, Chin Liang
> ; Simon Goldschmidt
> ; Ang, Chee Hong
>
> Subject: Re: [PATCH] arm: dts: socfpga: cyclone5: Update i2c-scl-falling-
> time-ns
On 6/9/20 8:33 AM, Tan, Ley Foon wrote:
[...]
>>> Commit e71b6f6622d6 ("i2c: designware_i2c: Rewrite timing
>>> calculation") change the hcnt and lcnt timing calculation.
>>>
>>> After this new timing calculation, hcnt will have negative value with
>>> i2c-scl-falling-time-ns 5000 that set in socfp
> -Original Message-
> From: Marek Vasut
> Sent: Friday, June 5, 2020 8:53 PM
> To: Tan, Ley Foon ; u-boot@lists.denx.de
> Cc: Ley Foon Tan ; See, Chin Liang
> ; Simon Goldschmidt
> ; Ang, Chee Hong
>
> Subject: Re: [PATCH] arm: socfpga: gen5: Enable cache driver in SPL
>
> On 6/5/20 1
This patch adds the board specific configuration (struct) for the
Octeon 3 EBB7304 EVK. This struct is ported from the 2013er Cavium /
Marvell U-Boot repository. Also, the Octeon RAM driver is enabled in
the board defconfig for its usage.
Tested with one and two DIMMs on the EBB7304 EVK (8 & 16 Gi
From: Aaron Williams
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.
Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integratio
From: Aaron Williams
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.
Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT bas
This patch adds the initialization call for the Octeon RAM driver to
the Octeon platforms code. So if enabled via Kconfig, the DDR driver
will be called and the RAM will be configured and used. If the RAM
driver is not enabled, the L2 cache is still used as RAM.
Signed-off-by: Stefan Roese
---
From: Aaron Williams
This header is used by the upcoming DDR driver and potentially by other
drivers ported from the 2013 Cavium / Marvell U-Boot repository.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/octeon-model.h | 449 ++
From: Aaron Williams
This header will be used by the DDR driver (lmc). Its ported from the
2013 Cavium / Marvell U-Boot repository.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
---
.../mach-octeon/include/mach/octeon_ddr.h | 988 ++
1 file changed, 988 insert
This patch adds the memory controller (LMC) DT node to the Octeon 3 dtsi
file. It also adds the L2C DT node, as this is referenced by the DDR
driver.
Signed-off-by: Stefan Roese
---
arch/mips/dts/mrvl,cn73xx.dtsi | 17 +
1 file changed, 17 insertions(+)
diff --git a/arch/mips/d
This patch adds the DDR4 init code. It is ported from the 2013 Cavium /
Marvell U-Boot version with no functional change. This was done
intentionally, as this code is very large and complex and is known to
work on many boards "as-is". So any functional change might have
introduced (hidden) incomp
Hi
Am Di., 9. Juni 2020 um 09:19 Uhr schrieb Heinrich Schuchardt
:
>
> On 09.06.20 09:09, Christian Gmeiner wrote:
> > According to the FAT specification it is valid to have files with an
> > attribute value of 0x0. This fixes a regression where different U-Boot
> > versions are showing different
Heinrich,
On Tue, Jun 09, 2020 at 03:54:44AM +, Heinrich Schuchardt wrote:
> Am June 9, 2020 1:42:14 AM UTC schrieb AKASHI Takahiro
> :
> >Heinrich,
> >
> >On Mon, Jun 08, 2020 at 11:08:53PM +0200, Heinrich Schuchardt wrote:
> >> Hello Takahiro,
> >>
> >> when trying to execute command
> >>
On 09.06.20 10:31, Sébastien Szymanski wrote:
> Hi,
>
> On 6/9/20 6:03 AM, Ye Li wrote:
>> Hi Sébastien,
>>
>>> -Original Message-
>>> From: U-Boot On Behalf Of
>>> sba...@denx.de
>>> Sent: 2020年6月9日 1:22
>>> To: Sébastien Szymanski ; u-
>>> b...@lists.denx.de
>>> Subject: [EXT] [PATCH v2
The original rtl_clear_bp() is used to clear the firmware of both
PLA and USB MCU. The new one could clear the firmware of PLA or
USB independently. It is unnecessary to clear firmware, if there
is no one to be updated.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.h| 20 ++--
This is used to support RTL8153B and RTL8154B.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c| 207 -
drivers/usb/eth/r8152.h| 46 -
drivers/usb/eth/r8152_fw.c | 176 +++
3 files changed, 425 insertions(+), 4
The first two patched are some improvements. And the last two patches
are used to support RTL8153B and RTL8154B.
Hayes Wang (4):
eth/r8152: reset bmu after disabling Tx/Rx
eth/r8152: reset PHY after setting it
eth/r8152: modify rtl_clear_bp function
eth/r8152: support RTL8153B/RTL8154B
d
Reset bmu after disabling Tx/Rx. This is used to clear the FIFO of
Tx/Rx. The remained data may be transferred after Tx/Rx is re-enabled.
And it results in garbage data.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 14 ++
drivers/usb/eth/r8152.h | 7 ++-
2 files chang
Some settings of PHY have to work after resetting PHY.
Signed-off-by: Hayes Wang
---
drivers/usb/eth/r8152.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c
index dbb1721882..d774a0fa63 100644
--- a/drivers/usb/eth/r8152.c
+++
Hi,
On 6/9/20 6:03 AM, Ye Li wrote:
> Hi Sébastien,
>
>> -Original Message-
>> From: U-Boot On Behalf Of
>> sba...@denx.de
>> Sent: 2020年6月9日 1:22
>> To: Sébastien Szymanski ; u-
>> b...@lists.denx.de
>> Subject: [EXT] [PATCH v2 1/1] imx: rom api: fix image offset computation
>>
>> Cauti
i.MX platforms provide large AHB mapped space for QSPI, each
controller has 256MB. However, current driver only maps small
size (AHB buffer size) of AHB space, this implementation
causes i.MX failed to boot M4 with QSPI XIP image.
Add config CONFIG_FSL_QSPI_AHB_FULL_MAP (default enabled for i.MX)
Add compatible string and driver data for i.MX7ULP.
Meanwhile, the address set to SFA1AD/SFA2AD/SFB1AD/SFB2AD should
align with 1KB, because the lowest 10 bits are reserved by the
registers definition.
For i.MX7ULP which has only 128Bytes AHB buffer, must align it
when setting the registers and sel
On 09.06.20 09:09, Christian Gmeiner wrote:
> According to the FAT specification it is valid to have files with an
> attribute value of 0x0. This fixes a regression where different U-Boot
> versions are showing different amount of files on the same storage
> device. With this change U-Boot shows th
On 09.06.20 07:09, AKASHI Takahiro wrote:
> A signed image may have multiple signatures in
> - each WIN_CERTIFICATE in authenticode, and/or
> - each SignerInfo in pkcs7 SignedData (of WIN_CERTIFICATE)
>
> In the initial implementation of efi_image_authenticate(), the criteria
> of verification
According to the FAT specification it is valid to have files with an
attribute value of 0x0. This fixes a regression where different U-Boot
versions are showing different amount of files on the same storage
device. With this change U-Boot shows the same number of files and folders
as Linux and Wind
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