Hi Andy,
On Fri, 4 Sep 2020 at 03:46, Andy Shevchenko
wrote:
>
> On Thu, Sep 03, 2020 at 07:28:51PM -0600, Simon Glass wrote:
> > At present it is painful to put Edison in a hardware lab because it has
> > two separate recovery modes. When the board has a functioning U-Boot, DFU
> > can be used.
Implement the 'getprisec' subcommand of 'bmode' command for i.MX53 and
also the primary/secondary bootmode switching.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: NXP i.MX U-Boot Team
Cc: Peng Fan
Cc: Stefano Babic
---
arch/arm/mach-imx/mx5/soc.c | 21 -
1 file
On Fri, Sep 04, 2020 at 09:05:51PM +0200, Marek Bykowski wrote:
> Hi Patrick,
>
> First of all thanks for your feedback...
>
> > >-|
> > >|| Read-Only
> > > Cacheable | Code |Not-Executable
> >
>
> Will check but after MMU is turned off the pages are no matter anymore so
> should be good. With MMU off for armv8 all data accesses are Device_nGnRnE,
> all instruction fetches are cacheable, all addresses are RW, XN=1
> (Executable).
XN=0 (Executable) meant. Thought would correct not to
Hi Patrick,
First of all thanks for your feedback...
> >-|
> >|| Read-Only
> > Cacheable | Code |Not-Executable
>
> Code is executable I think...
>
Good catch, copy/paste error from a rectangle
On 9/4/20 3:07 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Linking a U-boot larger than 1MB fails with PIE enabled:
> u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
> truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
> defined in .bss_start
On 9/4/20 3:07 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> PIE requires a 4K aligned load address. If this is not met, trap
> the startup sequence in a WFI loop rather than running into obscure
> failures.
> diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
>
On 9/4/20 3:07 AM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Mention the requirement of 4K aligned load addresses in the
> help section for the POSITION_INDEPENDENT option.
>
> Suggested-by: Michal Simek
> Signed-off-by: Edgar E. Iglesias
> ---
> arch/arm/Kconfig | 3 +++
> 1
Ported from Linux driver - drivers/net/usb9601.c
Signed-off-by: hyyoxhk
---
drivers/usb/eth/Kconfig | 8 +
drivers/usb/eth/Makefile | 1 +
drivers/usb/eth/dm9601.c | 521 +++
3 files changed, 530 insertions(+)
create mode 100644 drivers/usb/eth/dm9601.c
On Fri, Sep 04, 2020 at 04:04:05PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the next batch of Marvell MVEBU updates. Here the summary
> log:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Chris,
On 04/09/20 09:04PM, Pratyush Yadav wrote:
> The SPI NOR core will get Octal DTR in following commits. This has
> presented a significant challenge of keeping the SPL size in check on
> the x530 platform.
>
> On a previous iteration of the series, adding a set of compile-time
> switches
The Cypress Semper flash is an xSPI compliant octal DTR flash. Add
support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. Switch to uniform
sector mode on boot. Use the default 20 dummy cycles for a read fast
command.
The SFDP programming on some older
On 04/09/2020 14:40, Stefan Roese wrote:
Hi Andre,
On 04.09.20 14:35, Andre Heider wrote:
First I though that you have been syncing the file with the Linux kernel
version. But now I see that its sync'ed with downstream U-Boot most
likely. As for the license of the file: The Linux kernel
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
The flash supports the soft
When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
difficult to detect the mode the flash is in. One option is to read SFDP
in all modes and see which one gives the correct "SFDP" signature, but
not all flashes support SFDP in 8D-8D-8D mode.
Further, even if you detect the
On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
supports it. But Linux as of now expects to get the flash in 1S-1S-1S
mode. Handing the flash to Linux in Octal DTR mode means the kernel will
fail to detect the flash.
So, we need to reset to Power-on-Reset (POR) state before
A Soft Reset sequence will return the flash to Power-on-Reset (POR)
state. It consists of two commands: Soft Reset Enable and Soft Reset.
Find out if the sequence is supported from BFPT DWORD 16.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 6 ++
The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort
BFPT parsing.
The xSPI Profile 1.0 table specifies how many dummy cycles and address
bytes are needed for the Read Status Register command in Octal DTR mode.
Use that information to send the correct Read SR command.
Some controllers might have trouble reading just 1 byte in DTR mode. So,
when we are in DTR
Allow flashes to specify a hook to enable octal DTR mode. Use this hook
whenever possible to get optimal transfer speeds.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 31 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 33
This table is indication that the flash is xSPI compliant and hence
supports octal DTR mode. Extract information like the fast read opcode,
the number of dummy cycles needed for a Read Status Register command,
and the number of address bytes needed for a Read Status Register
command.
The default
The spi-mem layer provides a spi_mem_supports_op() function to check
whether a specific operation is supported by the controller or not.
This is much more accurate than the hwcaps selection logic based on
SPI_{RX,TX}_ flags.
Rework the hwcaps selection logic to use spi_mem_supports_op().
To make
Some devices in DTR mode expect an extra command byte called the
extension. The extension can either be same as the opcode, bitwise
inverse of the opcode, or another additional byte forming a 16-byte
opcode. Get the extension type from the BFPT. For now, only flashes with
"repeat" and "inverse"
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. These
allow tweaking
Double Transfer Rate (DTR) is SPI protocol in which data is transferred
on each clock edge as opposed to on each clock cycle. Make
framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode
like 4S-4D-4D will not work. All
JESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to
reflect that.
The check for rev A or later compared the BFPT header length with the
maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so
was the BFPT length for both rev A and B, this check worked fine. But
The SPI NOR core will get Octal DTR in following commits. This has
presented a significant challenge of keeping the SPL size in check on
the x530 platform.
On a previous iteration of the series, adding a set of compile-time
switches got the build working. But rebasing on the latest master breaks
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move related declarations to
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
drivers/mtd/spi/spi-nor-core.c | 224
Hi,
This series adds support for octal DTR flashes in the SPI NOR framework,
and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
flashes.
The Cadence QSPI controller driver is also updated to run in Octal DTR
mode.
Tested on TI J721E EVM.
The Travis CI build can be found here
Each phase is given a separate 'dtr' field so mixed protocols like
4S-4D-4D can be supported.
Signed-off-by: Pratyush Yadav
---
drivers/spi/spi-mem.c | 3 +++
include/spi-mem.h | 8
2 files changed, 11 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index
Set up opcode extension and enable/disable DTR mode based on whether the
command is DTR or not.
xSPI flashes can have a 4-byte dummy address associated with some
commands like the Read Status Register command in octal DTR mode. Since
the flash does not support sending the dummy address, we can
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called
the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same
opcode is sent twice. When it is "invert", the second byte is the
inverse of the
If the device tree provides a read delay value, use that directly and do
not perform the calibration procedure.
This allows the device tree to over-ride the read delay value in cases
where the read delay value obtained via calibration is incorrect. One
such example is the Cypress Semper flash. It
Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.
Signed-off-by: Andre Heider
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/armada-3720-espressobin-emmc.dts | 44
Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.
The dts itself is imported from Linux.
Signed-off-by: Andre Heider
---
arch/arm/dts/armada-3720-espressobin.dts | 190 ++
Fix the actual board vendor and ease synching dts files from Linux.
Signed-off-by: Andre Heider
---
arch/arm/dts/armada-3720-espressobin.dts | 4 ++--
board/Marvell/mvebu_armada-37xx/board.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
For SPL flow without specifying address for DT loading DTB is automatically
appended behind U-Boot code. Specifically _end symbol is used. Just behind
it there is place for bss section.
It means if early code is using static variable and there is a write to
this variable DTB file is corrupted if
Hi Simon, Bin,
-"Simon Glass" schrieb: -
> Betreff: [PATCH v2 08/57] x86: acpi: Support external GNVS tables
>
> At present U-Boot puts a magic number in the ASL for the GNVS table and
> searches for it later.
>
> Add a Kconfig option to use a different approach, where the ASL files
>
The I2C EEPROM is present on Tinker Board S as well. Move the i2c node
to the shared, U-Boot specific rk3288-tinker-u-boot.dtsi device tree.
Cc: Jonas Karlman
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker-u-boot.dtsi | 7 +++
arch/arm/dts/rk3288-tinker.dts | 7 ---
The property reg-shift with the same value is present in the base
device tree already. Remove unnecessary node from rk3288-tinker.dts.
Signed-off-by: Stefan Agner
---
arch/arm/dts/rk3288-tinker.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/dts/rk3288-tinker.dts
Hi Tom,
please pull the next batch of Marvell MVEBU updates. Here the summary
log:
- Fix SATA issue on Armada 3720
- Enable more SPI NOR chips in espressobin defconfig
On 04.09.20 10:57, Stefan Roese wrote:
On 28.08.20 16:56, Andre Heider wrote:
From: zachary
- This patch moves sata phy powerup from dedicate phy to compphy
and adds invert option for sata powerup routine.
Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90
Signed-off-by: zachary
On 04.09.20 11:00, Stefan Roese wrote:
On 31.08.20 08:48, Andre Heider wrote:
From: Konstantin Porotchkin
Enable support of ISSI SPI flashes found on EspressoBIN boards
Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5
Signed-off-by: Konstantin Porotchkin
Reviewed-on:
On 04.09.20 11:00, Stefan Roese wrote:
On 31.08.20 08:48, Andre Heider wrote:
From: Konstantin Porotchkin
Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting
newly produces EspressoBin boards (v7)
Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b
Signed-off-by: Konstantin
On Fri, Sep 04, 2020 at 03:04:02PM +0200, Michal Simek wrote:
>
>
> On 04. 09. 20 11:07, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Linking a U-boot larger than 1MB fails with PIE enabled:
> > u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
> > truncated to
On 04. 09. 20 11:07, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Linking a U-boot larger than 1MB fails with PIE enabled:
> u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
> truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
> defined in
Hi Andre,
On 04.09.20 14:35, Andre Heider wrote:
First I though that you have been syncing the file with the Linux kernel
version. But now I see that its sync'ed with downstream U-Boot most
likely. As for the license of the file: The Linux kernel version has
this SPDX tag:
//
Hi Stefan,
On 04/09/2020 14:02, Stefan Roese wrote:
Hi Andre,
On 31.08.20 09:53, Pali Rohár wrote:
On Monday 31 August 2020 05:34:07 Andre Heider wrote:
This adds the disabled eMMC node.
Signed-off-by: Andre Heider
---
arch/arm/dts/armada-3720-espressobin.dts | 63
On Fri, 4 Sep 2020 at 13:51, Patrick Delaunay wrote:
>
> arm: cache: cp15: don't map reserved region with no-map property
>
> Hi,
>
> On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region protected
> by a firewall. This region is reserved in device with "no-map" property.
>
> But
Hi Andre,
On 31.08.20 09:53, Pali Rohár wrote:
On Monday 31 August 2020 05:34:07 Andre Heider wrote:
This adds the disabled eMMC node.
Signed-off-by: Andre Heider
---
arch/arm/dts/armada-3720-espressobin.dts | 63 +---
1 file changed, 23 insertions(+), 40 deletions(-)
On Fri, Sep 04, 2020 at 06:01:44PM +1200, Chris Packham wrote:
> On Fri, 4 Sep 2020, 12:16 AM Tom Rini, wrote:
>
> > On Thu, Sep 03, 2020 at 12:02:06PM +1200, Chris Packham wrote:
> >
> > > Setting CONFIG_ENV_ADDR to something other than 0 stops gd->env_addr
> > > from being allocated
Hi Marek,
> From: U-Boot On Behalf Of Marek Bykowski
> Sent: jeudi 3 septembre 2020 02:01
> To: tr...@konsulko.com; s...@chromium.org; u-boot@lists.denx.de
> Cc: Marek Bykowski
> Subject: [PATCH v1] armv8: MMU: Fix the memory map for RAM
>
> From: Marek Bykowski
>
> The objective of this
From: "Edgar E. Iglesias"
PIE requires a 4K aligned load address. If this is not met, trap
the startup sequence in a WFI loop rather than running into obscure
failures.
Tested-by: Michal Simek
Suggested-by: André Przywara
Signed-off-by: Edgar E. Iglesias
---
arch/arm/cpu/armv8/start.S | 17
From: "Edgar E. Iglesias"
Linking a U-boot larger than 1MB fails with PIE enabled:
u-boot/arch/arm/cpu/armv8/start.S:71:(.text+0x3c): relocation
truncated to fit: R_AARCH64_ADR_PREL_LO21 against symbol `__rel_dyn_end'
defined in .bss_start section in u-boot.
This extends the supported range by
From: "Edgar E. Iglesias"
Mention the requirement of 4K aligned load addresses in the
help section for the POSITION_INDEPENDENT option.
Suggested-by: Michal Simek
Signed-off-by: Edgar E. Iglesias
---
arch/arm/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/Kconfig
From: "Edgar E. Iglesias"
This fixes some builds issues with large (> 1MB) PIE U-boot setups.
We also document the 4K aligned load address requirement and
add an early run-time check for it.
Thanks,
Edgar
ChangeLog:
v1 -> v2:
* Fix adr of _start in arch/arm/lib/crt0_64.S
* Add early check and
In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.
This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE +
arm: cache: cp15: don't map reserved region with no-map property
Hi,
On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region protected
by a firewall. This region is reserved in device with "no-map" property.
But sometime the platform boot failed in U-boot on a Cortex A7 access to
Save the no-map information present in reserve-memory node to allow
correct handling when the MMU is configured in board to avoid
speculative access.
Signed-off-by: Patrick Delaunay
---
common/image-fdt.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff
Add "flags" in lmp_property to save the "no-map" property of reserved region
and a new function lmb_reserve_flags() to check this flag.
The default allocation use flags = LMB_NONE.
The adjacent reserved memory region are merged only when they have
the same flags value.
This patch is partially
Remove the unused field size of struct lmb_region as it is initialized to 0
and never used after in lmb library.
See Linux kernel commit 4734b594c6ca ("memblock: Remove memblock_type.size
and add memblock.memory_size instead")
Signed-off-by: Patrick Delaunay
---
include/lmb.h | 1 -
lib/lmb.c
Add lmb_dump_region() function, to simplify lmb_dump_all_force().
This patch is based on Linux memblock dump function.
A example of bdinfo output is:
.
fdt_size= 0x000146a0
FB base = 0xfdd0
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0xc000-0x], 0x4000 bytes
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
This patch fixes an issue on STM32MP15x where predictive read access
on secure DDR area are caught by OP-TEE.
Signed-off-by: Patrick Delaunay
---
Add a new function lmb_is_reserved_flags to check is a
address is reserved with a specific flags.
This function can be used to check if an address had be
reserved with no-map flags with:
lmb_is_reserved_flags(lmb, addr, LMB_NOMAP);
Signed-off-by: Patrick Delaunay
---
include/lmb.h | 1 +
Add a test to check the management of reserved region with flags.
Signed-off-by: Patrick Delaunay
---
test/lib/lmb.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 644ee78758..d7bd826190 100644
---
On Thu, Sep 03, 2020 at 07:28:51PM -0600, Simon Glass wrote:
> At present it is painful to put Edison in a hardware lab because it has
> two separate recovery modes. When the board has a functioning U-Boot, DFU
> can be used. Otherwise an xFSTK image must be used.
>
> This series converts Andy's
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 12, 2020 9:56 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1
On Thu, Sep 03, 2020 at 07:28:56PM -0600, Simon Glass wrote:
> Add a description of how to flash Edison using the XFSTK tool.
Switch to OSIP and mentioned DnX may affect the wording here, though I didn't
see if it really the case. Also, please update with using clean U-Boot version
(no Git hash,
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 12, 2020 9:56 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1
On Thu, Sep 03, 2020 at 07:28:55PM -0600, Simon Glass wrote:
> It is useful to be able to flash Edison directly without relying on the
> installed U-Boot being functional.
>
> Add a binman image for this. It includes a master-boot record, U-Boot
> binary and an environment.
master-boot record ->
> -Original Message-
> From: Ang, Chee Hong
> Sent: Wednesday, August 12, 2020 9:56 AM
> To: u-boot@lists.denx.de
> Cc: Marek Vasut ; Simon Goldschmidt
> ; Tom Rini ; See,
> Chin Liang ; Tan, Ley Foon
> ; Ang, Chee Hong ;
> Chee, Tien Fong ; Lim, Elly Siew Chin
>
> Subject: [PATCH v1
On Thu, Sep 03, 2020 at 07:28:54PM -0600, Simon Glass wrote:
> In some cases it is useful to include a U-Boot environment region in an
> image. This allows the board to start up with an environment ready to go.
>
> Add a new entry type for this. The input is a text file containing the
>
On Thu, Sep 03, 2020 at 07:28:53PM -0600, Simon Glass wrote:
> The recent support for missing external binaries does not show an error
> message when a file is genuinely missing (i.e. it is missing but not
> marked as 'external'). This means that when -m is passed to binman, it
> will never report
On Thu, Sep 03, 2020 at 07:28:52PM -0600, Simon Glass wrote:
> We already use binman's 'multiple-images' feature with Chrome OS and we
> want to use it for Edison. There is no real down-side.
>
> Adjust x86 to always use multiple-images.
Acked-by: Andy Shevchenko
> Signed-off-by: Simon Glass
On Wed, Sep 2, 2020 at 2:14 PM Frank Wunderlich wrote:
>
> From: Chunfeng Yun
>
> Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
>
> Signed-off-by: Chunfeng Yun
> ---
> drivers/usb/host/xhci-mem.c | 3 +--
> drivers/usb/host/xhci-ring.c | 11 +--
> include/usb/xhci.h |
On 01.09.20 09:03, Andre Heider wrote:
From: Konstantin Porotchkin
Add support for additional EspressoBIN board with installed
eMMC device (U11).
EspressoBIN boards with eMMC installed should use the DTS named
armada-3720-espressobin-emmc.
Update build documentation accordingly.
Change-Id:
On 31.08.20 05:34, Andre Heider wrote:
This adds the disabled eMMC node.
Signed-off-by: Andre Heider
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-3720-espressobin.dts | 63 +---
1 file changed, 23 insertions(+), 40 deletions(-)
diff --git
On 31.08.20 08:48, Andre Heider wrote:
From: Konstantin Porotchkin
Enable support of ISSI SPI flashes found on EspressoBIN boards
Change-Id: I6de61c48f108fb4f410f321b9db45887d23212e5
Signed-off-by: Konstantin Porotchkin
Reviewed-on: http://vgitil04.il.marvell.com:8080/61455
Tested-by: iSoC
On 31.08.20 08:48, Andre Heider wrote:
From: Konstantin Porotchkin
Include support for CONFIG_SPI_FLASH_GIGADEVICE for supporting
newly produces EspressoBin boards (v7)
Change-Id: I5d4b972cbe2ee5a9d52ce9908794ad4e1b59ee3b
Signed-off-by: Konstantin Porotchkin
Reviewed-on:
On 28.08.20 16:56, Andre Heider wrote:
From: zachary
- This patch moves sata phy powerup from dedicate phy to compphy
and adds invert option for sata powerup routine.
Change-Id: I1b4e8753e2b2c14c6efa97bca2ffc7d2553d8a90
Signed-off-by: zachary
Signed-off-by: Ken Ma
Reviewed-on:
> To make the button command useful in a shell script it should return the
> status of the button:
>
> * 0 (true) - pressed, on
> * 1 (false) - not pressed, off
>
> The button command takes only one argument. Correct maxargs.
>
> Signed-off-by: Heinrich Schuchardt
Reviewed-by: Philippe
Hi,
> From: U-Boot On Behalf Of Guillermo Rodriguez
> Sent: mercredi 2 septembre 2020 13:06
> To: u-boot@lists.denx.de
> Cc: Guillermo Rodriguez ; Lukasz Majewski
>
> Subject: [PATCH] dfu: Fix handling of UBI partitions in MTD backend
>
> For UBI partitions ("partubi" in dfu_alt_info),
On Fri, 2020-09-04 at 09:05 +0200, Marek Vasut wrote:
> On 9/4/20 8:54 AM, Bin Meng wrote:
> > On Wed, Aug 26, 2020 at 5:31 PM Chunfeng Yun
> > wrote:
> >>
> >> Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
> >>
> >> Signed-off-by: Chunfeng Yun
> >> ---
> >> v2: no changes
> >> ---
> >>
Hello Heinrich,
On Tue, 25 Aug 2020 at 16:50, Heinrich Schuchardt wrote:
>
> On 25.08.20 13:42, Patrice Chotard wrote:
> > From: Etienne Carriere
> >
> > Add boolean input argument @no_map to helper function
> > fdtdec_add_reserved_memory() to add "no-map" property for an added
> > reserved
Hi Marek,
On Fri, Sep 4, 2020 at 3:05 PM Marek Vasut wrote:
>
> On 9/4/20 8:54 AM, Bin Meng wrote:
> > On Wed, Aug 26, 2020 at 5:31 PM Chunfeng Yun
> > wrote:
> >>
> >> Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
> >>
> >> Signed-off-by: Chunfeng Yun
> >> ---
> >> v2: no changes
> >>
On 9/4/20 8:54 AM, Bin Meng wrote:
> On Wed, Aug 26, 2020 at 5:31 PM Chunfeng Yun
> wrote:
>>
>> Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
>>
>> Signed-off-by: Chunfeng Yun
>> ---
>> v2: no changes
>> ---
>> drivers/usb/host/xhci-mem.c | 3 +--
>> drivers/usb/host/xhci-ring.c | 11
On Wed, Aug 26, 2020 at 5:31 PM Chunfeng Yun wrote:
>
> There some vendor quirks for MTK xHCI 0.96 host controller:
> 1. It defines some extra SW scheduling parameters for HW
>to minimize the scheduling effort for synchronous and
>interrupt endpoints. The parameters are put into reseved
On Wed, Sep 2, 2020 at 2:15 PM Frank Wunderlich wrote:
>
> From: Chunfeng Yun
>
> Use HCS_MAX_PORTS(p) instead of
> ((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT)
>
> Signed-off-by: Chunfeng Yun
> ---
> drivers/usb/host/xhci.c | 3 +--
> include/usb/xhci.h | 2 --
> 2 files changed, 1
On Wed, Aug 26, 2020 at 5:31 PM Chunfeng Yun wrote:
>
> Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT)
>
> Signed-off-by: Chunfeng Yun
> ---
> v2: no changes
> ---
> drivers/usb/host/xhci-mem.c | 3 +--
> drivers/usb/host/xhci-ring.c | 11 +--
> include/usb/xhci.h | 1 -
On Fri, 4 Sep 2020, 12:16 AM Tom Rini, wrote:
> On Thu, Sep 03, 2020 at 12:02:06PM +1200, Chris Packham wrote:
>
> > Setting CONFIG_ENV_ADDR to something other than 0 stops gd->env_addr
> > from being allocated dynamically. When the environment is in SPI we need
> > it to be allocated as we
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