Hi Bin,
On Tuesday, November 10, 2020 3:47 PM Bin Meng wrote:
>
> Hi Ran,
> > > > > send request in more than 1 Transfer TRB by chaining them, but
> > > > > then handle only 1 event TRB to mark request completed.
> > > > >
> > > > > However, on Layerscape platforms (LS1028A, LS1088A, etc), we
>
On 09/11/2020 23:19, Jaehoon Chung wrote:
> On 11/9/20 11:23 PM, Neil Armstrong wrote:
>> On 09/11/2020 15:10, Mark Kettenis wrote:
From: Neil Armstrong
Date: Mon, 9 Nov 2020 14:37:09 +0100
Hi,
On 09/11/2020 04:12, Jaehoon Chung wrote:
> Core clock phase value is
On 10/11/2020 08:50, Jaehoon Chung wrote:
> EMMC_CFG register has a cfg_ddr bit(BIT[2]).
> It needs to set when mmc is running to ddr mode.
> Otherwise, its bit should be cleared.
> CFG_DDR[2] - 1: DDR mode, 0: SDR mode
>
> Signed-off-by: Jaehoon Chung
> ---
> arch/arm/include/asm/arch-meson/sd_
Hi Bin,
On Tuesday, November 10, 2020 4:06 PM Ran Wang wrote:
> Hi Bin,
>
> On Tuesday, November 10, 2020 3:47 PM Bin Meng wrote:
> >
> > Hi Ran,
>
> > > > > > send request in more than 1 Transfer TRB by chaining them, but
> > > > > > then handle only 1 event TRB to mark request completed.
> >
On 11/10/20 5:05 PM, Neil Armstrong wrote:
> On 09/11/2020 23:19, Jaehoon Chung wrote:
>> On 11/9/20 11:23 PM, Neil Armstrong wrote:
>>> On 09/11/2020 15:10, Mark Kettenis wrote:
> From: Neil Armstrong
> Date: Mon, 9 Nov 2020 14:37:09 +0100
>
> Hi,
>
> On 09/11/2020 04:12,
On 11/10/20 5:15 PM, Neil Armstrong wrote:
> On 10/11/2020 08:50, Jaehoon Chung wrote:
>> EMMC_CFG register has a cfg_ddr bit(BIT[2]).
>> It needs to set when mmc is running to ddr mode.
>> Otherwise, its bit should be cleared.
>> CFG_DDR[2] - 1: DDR mode, 0: SDR mode
>>
>> Signed-off-by: Jaehoon C
> From: Neil Armstrong
> Date: Tue, 10 Nov 2020 09:15:14 +0100
>
> On 10/11/2020 08:50, Jaehoon Chung wrote:
> > EMMC_CFG register has a cfg_ddr bit(BIT[2]).
> > It needs to set when mmc is running to ddr mode.
> > Otherwise, its bit should be cleared.
> > CFG_DDR[2] - 1: DDR mode, 0: SDR mode
>
On 10/11/2020 09:36, Jaehoon Chung wrote:
> On 11/10/20 5:05 PM, Neil Armstrong wrote:
>> On 09/11/2020 23:19, Jaehoon Chung wrote:
>>> On 11/9/20 11:23 PM, Neil Armstrong wrote:
On 09/11/2020 15:10, Mark Kettenis wrote:
>> From: Neil Armstrong
>> Date: Mon, 9 Nov 2020 14:37:09 +0100
On 11/10/20 5:50 PM, Mark Kettenis wrote:
>> From: Neil Armstrong
>> Date: Tue, 10 Nov 2020 09:15:14 +0100
>>
>> On 10/11/2020 08:50, Jaehoon Chung wrote:
>>> EMMC_CFG register has a cfg_ddr bit(BIT[2]).
>>> It needs to set when mmc is running to ddr mode.
>>> Otherwise, its bit should be cleared.
Hi Ran,
On Tue, Nov 10, 2020 at 4:31 PM Ran Wang wrote:
>
> Hi Bin,
>
> On Tuesday, November 10, 2020 4:06 PM Ran Wang wrote:
> > Hi Bin,
> >
> > On Tuesday, November 10, 2020 3:47 PM Bin Meng wrote:
> > >
> > > Hi Ran,
> >
> > > > > > > send request in more than 1 Transfer TRB by chaining them,
Hello,
On TI J7 SoCs the device manager firmware is now split into two
portions instead of the existing one which supported all services via a
single firmware image running on DMSC core. Now, the existing DMSC core
is dedicated for secure services only, and the PM and RM functionality
is moved und
From: Lokesh Vutla
board_fit_image_post_process() passes only start and size of the image,
but type of the image is not passed. So pass fit and node_offset, to
derive information about image to be processed.
Signed-off-by: Lokesh Vutla
---
arch/arm/mach-k3/security.c | 3 ++-
arch/arm/mach-ke
clk_set_rate returns the new clock rate for the clock, not 0 in success.
Fix the error checks to reflect proper API usage.
Signed-off-by: Tero Kristo
---
drivers/ram/k3-j721e/k3-j721e-ddrss.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/k3-j721e/k3-j721e-
Copy the best rational approximation calculation routines from Linux.
Typical usecase for these routines is to calculate the M/N divider
values for PLLs to reach a specific clock rate.
Signed-off-by: Tero Kristo
---
include/linux/rational.h | 20
lib/Kconfig | 7 +++
lib/M
With the sysfw rearch, sysfw PM calls are no longer available from SPL
level. To properly support this, remove the is_on checks and the reset
assertion from the R5 remoteproc driver as these are not supported.
Attempting to access unavailable services will cause the device to hang.
Signed-off-by:
Bail out early if device returned for the parent clock is null.
This avoids warning prints like this when doing clk dump:
dev_get_uclass_priv: null device
Signed-off-by: Tero Kristo
---
drivers/clk/clk-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk-uclass.c b/d
Current driver only supports registering fixed rate clocks from DT. Add
new API which makes it possible to register fixed rate clocks directly
from e.g. platform specific clock drivers.
Signed-off-by: Tero Kristo
---
drivers/clk/clk_fixed_rate.c | 45 +++-
include
Set rate should return the new clock rate on success, and negative error
value on failure. Fix this, as currently set_rate returns 0 on success.
Signed-off-by: Tero Kristo
---
drivers/clk/clk-ti-sci.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-ti-sc
Add new clk subcommand "clk setfreq", for setting up a clock rate
directly from u-boot cmdline. This is handy for any debugging purposes
towards clocks.
Signed-off-by: Tero Kristo
---
cmd/clk.c | 49 +++--
1 file changed, 47 insertions(+), 2 deletions(
Add support for TI K3 SoC PLLs. This clock type supports
enabling/disabling/setting and querying the clock rate for the PLL. The
euclidean library routine is used to calculate divider/multiplier rates
for the PLLs.
Signed-off-by: Tero Kristo
---
drivers/clk/Kconfig | 12 ++
drivers/clk/Mak
Some clocks are not associated to a DM node, so just parsing the DM is not
enough. This is especially true for root clocks, which typically don't have
any parents. Instead, fetch every registered UCLASS_CLK instance, and dump
these out.
Signed-off-by: Tero Kristo
---
cmd/clk.c | 27 +
Add driver to support TI K3 generation SoC clocks. This driver registers
the clocks provided via platform data, and adds support for controlling
the clocks via DT handles.
Signed-off-by: Tero Kristo
---
drivers/clk/Kconfig | 10 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-k3.c | 340 +
If a clock provider is not ready for assigning default rates/parents
during its probe, it may return -EPROBE_DEFER directly from xlate.
Handle this special case properly by skipping the entry and adjusting the
return value to pass. The defaults will be handled properly in post probe
phase then.
Si
Add support command for debugging K3 power domains. This is useful with
the HSM rearch setup, where power domains are directly controlled by SPL
instead of going through the TI SCI layer. The debugging support is only
available in the u-boot codebase though, so the raw register access
power domain
Normally, power domains are handled via TI-SCI in K3 SoCs. However,
SPL is not going to have access to sysfw resources, so it must control
them directly. Add driver for supporting this.
Signed-off-by: Tero Kristo
---
drivers/power/domain/Kconfig | 7 +
drivers/power/domain/Makefile
Add DM (device manager) firmware image to the fit image that is loaded by
R5 SPL. This is needed with the HSM rearch where the firmware allocation
has been changed slightly.
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/config.mk | 4
tools/k3_fit_atf.sh| 19 ++-
If the raw PM support is built in, we are operating in the split
firmware approach mode where RM and PM support is not available. In this
case, skip the board config for these two.
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 4
1 file changed, 4 insertions(+)
diff --gi
Clock rates are cached within the individual clock nodes, and right now
if one changes a clock rate somewhere in the middle of the tree, none
of its child clocks notice the change. To fix this, clear up all the
cached rates for us and our child clocks.
Signed-off-by: Tero Kristo
---
drivers/clk/
With the new raw register mode access PM drivers, A72 core is not
enabled via ti-sci services, leading into bad usecounts for the core.
This effectively shuts down the A72 core when SPL goes down. Prevent the
problem by force enabling the A72 core once, which increases the use
count.
Signed-off-by
From: Dave Gerlach
Only start-up the non-linux remote cores if we are running in legacy
boot mode. HSM rearch is not yet supporting this.
Signed-off-by: Dave Gerlach
---
arch/arm/mach-k3/common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3
From: Dave Gerlach
Add platform clock and powerdomain data for J721e and J7200. This data
is used by the corresponding drivers to register all the required device
clocks and powerdomains.
Signed-off-by: Dave Gerlach
---
arch/arm/mach-k3/Makefile | 2 +-
arch/arm/mach-k3/j7200/Makefil
Add callback routines for parsing the firmware info from FIT image, and
use the data to boot up ATF and the MCU R5 firmware.
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/common.c | 80 +
arch/arm/mach-k3/common.h | 1 +
arch/arm/mach-k3/security.c | 3
This is used to parse the images from FIT, and to determine image types.
Signed-off-by: Tero Kristo
---
configs/j721e_evm_r5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 62586b2f3b..f2c047f8e8 100644
--- a/con
With the sysfw rearch, PM services are no longer available for R5 SPL to
use. Instead, we will be using the raw PM register level access drivers
for any PM. Thus, disable the SCI PM drivers to reflect this.
Signed-off-by: Tero Kristo
---
configs/j721e_evm_r5_defconfig | 4 ++--
1 file changed, 2
Copy the contents of the board config loaded from sysfw.itb into an
EXTBOOT shared memory buffer that gets passed to sciserver. This only
needs to be done if EXTBOOT area has not been populated by ROM code yet.
Signed-off-by: Tero Kristo
---
arch/arm/mach-k3/sysfw-loader.c | 98 +
From: Dave Gerlach
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Dave Gerlach
---
configs/j7200_evm_r5_defconfig | 13 +
Sysfw is not going to provide access to power management features in the
new architecture, so SPL must implement these itself. Enable all the raw
register access based clock + power domain drivers.
Signed-off-by: Tero Kristo
---
configs/j721e_evm_r5_defconfig | 6 ++
1 file changed, 6 insert
> From: Jaehoon Chung
> Date: Tue, 10 Nov 2020 18:02:02 +0900
>
> On 11/10/20 5:50 PM, Mark Kettenis wrote:
> >> From: Neil Armstrong
> >> Date: Tue, 10 Nov 2020 09:15:14 +0100
> >>
> >> On 10/11/2020 08:50, Jaehoon Chung wrote:
> >>> EMMC_CFG register has a cfg_ddr bit(BIT[2]).
> >>> It needs t
Hi Bin,
On Tuesday, November 10, 2020 5:03 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Nov 10, 2020 at 4:31 PM Ran Wang wrote:
> >
> > Hi Bin,
> >
> > On Tuesday, November 10, 2020 4:06 PM Ran Wang wrote:
> > > Hi Bin,
> >
>
> Based on your log, it matches what I suspected and we are getting
Hi Ran,
On Tue, Nov 10, 2020 at 5:41 PM Ran Wang wrote:
>
> Hi Bin,
>
> On Tuesday, November 10, 2020 5:03 PM Bin Meng wrote:
> >
> > Hi Ran,
> >
> > On Tue, Nov 10, 2020 at 4:31 PM Ran Wang wrote:
> > >
> > > Hi Bin,
> > >
> > > On Tuesday, November 10, 2020 4:06 PM Ran Wang wrote:
> > > > Hi B
Hi Bin,
On Tuesday, November 10, 2020 5:47 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Nov 10, 2020 at 5:41 PM Ran Wang wrote:
> >
> > Hi Bin,
> >
> > On Tuesday, November 10, 2020 5:03 PM Bin Meng wrote:
> > >
> > > Hi Ran,
> > >
> > > On Tue, Nov 10, 2020 at 4:31 PM Ran Wang
> wrote:
> > > >
Improve USB config so keyboard and USB-A ports work.
Signed-off-by: Peter Robinson
---
configs/pinebook-pro-rk3399_defconfig | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/configs/pinebook-pro-rk3399_defconfig
b/configs/pinebook-pro-rk3399_defconfig
index 1ed54ad0ed..8f
On Tue, Nov 10, 2020 at 12:22 AM Tom Rini wrote:
>
> Hey all,
>
> It's regular release day and I'm back on schedule, so here's -rc2.
>
> There's a few small'ish things outstanding in my queue, and a queue of
> things building up for -next already. I'm going to try and make sure
> what I pull in,
On Tue, Nov 10, 2020 at 12:40 PM Andy Shevchenko
wrote:
>
> On Tue, Nov 10, 2020 at 12:22 AM Tom Rini wrote:
> >
> > Hey all,
> >
> > It's regular release day and I'm back on schedule, so here's -rc2.
> >
> > There's a few small'ish things outstanding in my queue, and a queue of
> > things buildi
When copying a string with must allocate a byte for the terminating '\0' in
the target buffer.
Fixes: fbe4c7df0087 ("efi_loader: enable file SetInfo()")
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_file.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/efi_lo
I just fixed one bug in EFI_FILE_PROTOCOL.SetInfo(), cf.
[PATCH 1/1] efi_loader: incorrect buffer size in efi_file_setinfo()
https://lists.denx.de/pipermail/u-boot/2020-November/432480.html
With this patch applied when running the UEFI SCT test GetInfoFunction
on sandbox_defconfig on aarch64 a c
On 11/10/20 11:41 AM, Andy Shevchenko wrote:
On Tue, Nov 10, 2020 at 12:40 PM Andy Shevchenko
wrote:
On Tue, Nov 10, 2020 at 12:22 AM Tom Rini wrote:
Hey all,
It's regular release day and I'm back on schedule, so here's -rc2.
There's a few small'ish things outstanding in my queue, and a q
There is no reason to have these macros. But record offsets of missing
register in the structure for future use.
Signed-off-by: Michal Simek
---
arch/arm/mach-zynqmp/include/mach/hardware.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-zynqmp/include/ma
TPMs are becoming popular that's why enable drivers and command for it.
Signed-off-by: Michal Simek
---
configs/xilinx_zynqmp_virt_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/xilinx_zynqmp_virt_defconfig
b/configs/xilinx_zynqmp_virt_defconfig
index 0c816de707ac..ba
On Tue, Nov 10, 2020 at 01:00:06PM +0100, Heinrich Schuchardt wrote:
> On 11/10/20 11:41 AM, Andy Shevchenko wrote:
> > On Tue, Nov 10, 2020 at 12:40 PM Andy Shevchenko
> > wrote:
> > >
> > > On Tue, Nov 10, 2020 at 12:22 AM Tom Rini wrote:
> > > >
> > > > Hey all,
> > > >
> > > > It's regular
On 11/10/20 1:16 PM, Tom Rini wrote:
On Tue, Nov 10, 2020 at 01:00:06PM +0100, Heinrich Schuchardt wrote:
On 11/10/20 11:41 AM, Andy Shevchenko wrote:
On Tue, Nov 10, 2020 at 12:40 PM Andy Shevchenko
wrote:
On Tue, Nov 10, 2020 at 12:22 AM Tom Rini wrote:
Hey all,
It's regular release da
Hi,
I am sending 3 more patches for fru code. Especially the second patch is
important because it ensures that data in .data section is not overwritten
based on parsed structures.
Thanks,
Michal
Michal Simek (3):
fru: common: Switch capture variable with the rest
fru: ops: Do not let parser
capture variable is bool which is just one byte and it is just causing
unaligned accesses. Better to have it as last entry in the structure.
It also simplify offset calculation for initial header copy.
Signed-off-by: Michal Simek
---
board/xilinx/common/fru.h | 2 +-
board/xilinx/common/fr
If customs fields in board area are used it will likely go over allocated
space in struct fru_board_data. That's why calculate limit of this
structure to make sure that different data is not rewritten by accident.
When limit is reached stop to record fields.
Signed-off-by: Michal Simek
---
boar
Add additional fields. They will be just recorded and filled but not shown.
Signed-off-by: Michal Simek
---
board/xilinx/common/fru.h | 4
1 file changed, 4 insertions(+)
diff --git a/board/xilinx/common/fru.h b/board/xilinx/common/fru.h
index e85dde45314f..e7284709ddea 100644
--- a/board
On Tue, Nov 10, 2020 at 01:18:41PM +0100, Heinrich Schuchardt wrote:
> On 11/10/20 1:16 PM, Tom Rini wrote:
> > On Tue, Nov 10, 2020 at 01:00:06PM +0100, Heinrich Schuchardt wrote:
> > > On 11/10/20 11:41 AM, Andy Shevchenko wrote:
> > > > On Tue, Nov 10, 2020 at 12:40 PM Andy Shevchenko
> > > > w
On Sun, Nov 08, 2020 at 03:48:23PM +, André Przywara wrote:
> On 08/11/2020 14:59, Peter Robinson wrote:
>
> Hi,
>
> > On Sun, Nov 8, 2020 at 1:14 PM Andre Przywara
> > wrote:
> >>
> >> The eMMC standard describes the concept of boot partitions, consisting
> >> of two storage areas separate
On Tue, Nov 10, 2020 at 11:38:58AM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following x86 changes for v2021.01 release:
>
> - Avoid using hardcoded number of variable range MTRRs in mtrr_commit()
> - coral: Correct max98357 file
> - coral: Update smbios tables to latest definiti
On Tue, Nov 10, 2020 at 11:05:37AM +0200, Tero Kristo wrote:
> Copy the best rational approximation calculation routines from Linux.
> Typical usecase for these routines is to calculate the M/N divider
> values for PLLs to reach a specific clock rate.
>
> Signed-off-by: Tero Kristo
Please say w
On 10/11/2020 12:38, Tom Rini wrote:
Hi Tom,
> On Sun, Nov 08, 2020 at 03:48:23PM +, André Przywara wrote:
>> On 08/11/2020 14:59, Peter Robinson wrote:
>>
>> Hi,
>>
>>> On Sun, Nov 8, 2020 at 1:14 PM Andre Przywara
>>> wrote:
The eMMC standard describes the concept of boot partit
On Tue, Nov 10, 2020 at 12:57:09PM +, André Przywara wrote:
> On 10/11/2020 12:38, Tom Rini wrote:
>
> Hi Tom,
>
> > On Sun, Nov 08, 2020 at 03:48:23PM +, André Przywara wrote:
> >> On 08/11/2020 14:59, Peter Robinson wrote:
> >>
> >> Hi,
> >>
> >>> On Sun, Nov 8, 2020 at 1:14 PM Andre Pr
Hello Patrick,
Am 06.11.2020 um 19:01 schrieb Patrick Delaunay:
Change debug to dev_dbg macro and define LOG_CATEGORY.
Remove the "%s:" __func__ header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).
Signed-off-by: Patrick Delaunay
Reviewed-by: Patrice
On Tue, Nov 10, 2020 at 6:46 PM Padmarao Begari
wrote:
>
> Add device tree for Microchip PolarFire SoC Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Anup Patel
> ---
> arch/riscv/dts/Makefile | 1 +
> .../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 15 +
Since commit 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this
command, but the sandbox EC emulator does not recognize it and
continuously prints:
** Unknown EC command 0x67
This patch makes the sandbox driver send ba
On 09/11/2020 17:45, Simon Glass wrote:
> At present if CROSS_COMPILE contains a tilde, such as
> ~/.buildman-toolchains/gcc-7.3.0-nolibc/i386-linux/bin/i386-linux-gcc
> then binman gives a confusing error:
>
>binman: Error 255 running '~/..buildman-toolchains/gcc-7.3.0- ...
>
> Fix this by e
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2 files changed, 8 insertio
This patch set adds Microchip PolarFire SoC Icicle Kit support
to RISC-V U-Boot.
The patches are based upon latest U-Boot tree
(https://gitlab.denx.de/u-boot/u-boot.git) at commit id
1ae955e3a58f46918ef99b0b6c562967ba1bf39e
All drivers namely: NS16550 Serial, Microchip clock,
Cadence eMMC and Cad
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 827 ++
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 15 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
Enable 32-bit or 64-bit DMA in the macb driver based on the design
config debug6 register of MACB hardware which supports 32-bit or
64-bit DMA.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 121 +++--
drivers/net/macb.h | 6 +++
2 files changed
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS +
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
---
drivers/net/macb.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
On Tue, Nov 10, 2020 at 2:35 PM Tom Rini wrote:
> On Tue, Nov 10, 2020 at 01:18:41PM +0100, Heinrich Schuchardt wrote:
> > On 11/10/20 1:16 PM, Tom Rini wrote:
> > > On Tue, Nov 10, 2020 at 01:00:06PM +0100, Heinrich Schuchardt wrote:
> > > > On 11/10/20 11:41 AM, Andy Shevchenko wrote:
> > > > >
On 2020-11-04 15:05, Stefan Agner wrote:
> On 2020-10-16 03:28, Ricardo Salveti wrote:
>> On Tue, Oct 13, 2020 at 11:04 AM Peter Robinson wrote:
>>>
>>> > >> Hello Matthias,
>>> > >>
>>> > >> I have upgraded the Raspberry 3 firmware from raspi3-firmware
>>> > >> (1.20190215-1+deb10u4) to raspi-fir
On 10.11.20 15:00, Alper Nebi Yasak wrote:
> Since commit 690079767803 ("cros_ec: Support keyboard scanning with
> EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this
> command, but the sandbox EC emulator does not recognize it and
> continuously prints:
>
> ** Unknown EC com
Hi,
> On 10 Nov 2020, at 07:34, Kever Yang wrote:
>
> Hi Peter,
>
> On 2020/11/9 上午7:02, Peter Robinson wrote:
>> Move the bits that are device specific to the -u-boot.dtsi as the
>> bits may be different on other devices and hence breaks SPI on
>> those devices such as the Pinebook Pro.
>>
>>
Alper Nebi Yasak writes:
> Something else you can test:
> - Remove the aliases block from rk3399-rockpro64-u-boot.dtsi
> - Add "spi[0-5] = &spi[0-5];" aliases to rk3399-u-boot.dtsi
> - Add CONFIG_SF_DEFAULT_BUS=1 to configs/rockpro64-rk3399_defconfig
This fixed for me the same issue on my Pineboo
On 11/10/20 8:49 AM, Ilias Apalodimas wrote:
> A following patch introduces EFI_TCG2_PROTOCOL.
> Add the required TPMv2 headers to support it.
>
> Signed-off-by: Ilias Apalodimas
> ---
> changes since v2:
> - Added description and pointers to TCG specs
> - updated copyright info
> include/tpm-v2.
Add a wrapper for retrieving a given property from the /config node as
a (blob, length) pair. A later patch will need the length of the
property and thus cannot just use fdtdec_get_config_string(). Rewrite
that to use the new wrapper.
Signed-off-by: Rasmus Villemoes
---
include/fdtdec.h | 14 +++
It can be useful to use the same U-Boot binary for multiple purposes,
say the normal one, one for developers that allow breaking into the
U-Boot shell, and one for use during bootstrapping which runs a
special-purpose bootcmd. To that end, allow the control dtb to contain
a /config/default-envirome
These patches introduce the ability to amend the default environment
baked into the U-Boot binary by a DT property under /config. This is
useful to create a few different images based on the same U-Boot
binary, e.g. one for normal use, one for development and one for
bootstrapping the board. It's a
Nobody should modify the string returned by
fdtdec_get_config_string(), so make it return a const pointer.
Signed-off-by: Rasmus Villemoes
---
arch/arm/mach-exynos/include/mach/mipi_dsim.h | 2 +-
arch/arm/mach-rockchip/rk3188/rk3188.c| 2 +-
board/dhelectronics/dh_stm32mp1/board.c
Unlike most other functions declared in env.h, the return value of
this one also isn't documented. It only has a single caller, which
ignores the return value. And the companion, env_set_default(),
already has void as return type.
Signed-off-by: Rasmus Villemoes
---
env/common.c | 4 ++--
inclu
Signed-off-by: Rasmus Villemoes
---
configs/sandbox64_defconfig | 1 +
configs/sandbox_defconfig | 1 +
include/configs/sandbox.h | 8 ++-
test/env/Makefile | 1 +
test/env/default.c | 102
5 files changed, 112 insertions(+), 1 d
Hi,
I am trying to create a pcie x4 interface using a standard SERDES map on a
Marvell 38x chip (MV88F6828) in Uboot 2019.01. However lane verification
prevents me from enabling the pcie x4 configuration.
The closest example I can find is this slm1363 board from this file:
https://github.com/u-bo
The function mmc_offset_try_partition searches MMC partition to save the
environment data by name. However, it only compares the first word-size
bytes (size of 'const char *'), which may make the function to find
unintended partition.
Correct the function not to partially compare the partition na
Sadly, when we eliminate defects it doesn't say which ones in an email.
-rc2 eliminated one defect and introduced these two new ones.
- Forwarded message from scan-ad...@coverity.com -
Date: Mon, 09 Nov 2020 22:31:55 + (UTC)
From: scan-ad...@coverity.com
To: tom.r...@gmail.com
Subject
Currently if an exception SIGILL, SIGBUS, SIGSEGV occurs the sandbox
stops execution. This does not match the behavior on other architectures.
Instead print the current program counter and if any the involved UEFI
binaries. Then reset the system.
When testing UEFI binaries like the Self Certifica
Implement the commands
* exception undefined - execute an illegal instruction
* exception sigsegv - cause a segment violation
Here is a possible output:
=> exception undefined
Illegal instruction
pc = 0x55eb8d0a7575, pc_reloc = 0x57575
Resetting ...
Signed-off-by: Heinrich Schuc
Add a handler for SIGILL, SIGBUS, SIGSEGV.
When an exception occurs print the program counter and the loaded
UEFI binaries and reset the system.
Signed-off-by: Heinrich Schuchardt
---
arch/sandbox/cpu/os.c | 31 +++
arch/sandbox/cpu/start.c | 4
ar
Provide a unit test that causes an illegal instruction to occur.
The test can be run with the following commands:
=> setenv efi_selftest exception
=> bootefi selftest
This might be the output:
Executing 'exception'
EFI application triggers exception.
Illegal instruction
On 10/11/2020 20:08, Heinrich Schuchardt wrote:
> On 10.11.20 15:00, Alper Nebi Yasak wrote:
>> Since commit 690079767803 ("cros_ec: Support keyboard scanning with
>> EC_CMD_GET_NEXT_EVENT") the cros-ec-keyb driver has started using this
>> command, but the sandbox EC emulator does not recognize it
From: Neil Armstrong
Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
working fine over 50MHz on Amlogic SM1 SoCs.
Since Other Amlogic SoCs doens't report an issue, phase value is using
to 180' by default.
To distinguish which value is used adds an u-boot only sm1 compatib
Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's
working fine over 50MHz on Amlogic SM1 SoCs.
To use a proper phase value adds an u-boot only sm1 compatible.
In future, it needs to find what value is a proper about each SoCs.
According to Neil's suggestion, applied code ba
From: Neil Armstrong
In order to enable the Amlogic SM1 MMC controller fix, we need to add a u-boot
specific
MMC controller compatible.
This adds a new meson-sm1-u-boot.dtsi and reworks the other -u-boot.dtsi
to use this for SM1 based boards.
Signed-off-by: Neil Armstrong
---
.../meson-g12b-
From: Neil Armstrong
Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h,
remove the useless if/then and fix the meson_gx_mmc.c include.
Signed-off-by: Neil Armstrong
---
drivers/mmc/meson_gx_mmc.c | 2 +-
.../asm/arch-meson/sd_emmc.h => drivers/mmc/meso
On 10/11/2020 20:18, Hugh Cole-Baker wrote:
> Hi,
>
>> On 10 Nov 2020, at 07:34, Kever Yang wrote:
>>
>> Hi Peter,
>>
>> On 2020/11/9 上午7:02, Peter Robinson wrote:
>>> Move the bits that are device specific to the -u-boot.dtsi as the
>>> bits may be different on other devices and hence breaks SPI
Hi Alper,
On Tue, 10 Nov 2020 at 07:45, Alper Nebi Yasak wrote:
>
> On 09/11/2020 17:45, Simon Glass wrote:
> > At present if CROSS_COMPILE contains a tilde, such as
> > ~/.buildman-toolchains/gcc-7.3.0-nolibc/i386-linux/bin/i386-linux-gcc
> > then binman gives a confusing error:
> >
> >binma
> From: Pragnesh Patel [mailto:pragnesh.pa...@sifive.com]
> Sent: Thursday, October 22, 2020 2:55 PM
> To: u-boot@lists.denx.de
> Cc: atish.pa...@wdc.com; palmerdabb...@google.com; bmeng...@gmail.com;
> paul.walms...@sifive.com; anup.pa...@wdc.com; sagar.ka...@sifive.com; Rick
> Jian-Zhi Chen(陳建志
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