Hi
I compile the master branch u-boot for LicheePi Zero,
it's not working.I'm trying to fix the the issue, it's working
but ugly now.
I didn't figure out why the sunxi_spi_probe function in
drivers/spi/sunxi_spi.c was not called automatically.
Finally, I add code to probe all spi device man
The Armada driver also works on Nedap's ax8008 Kirkwood board with a
Marvell 88F6180 CPU. The original commit of that driver,
704d9a645e1790e568abf43c5eff2de0d7b135ed also mentions that this driver
would be suitable for Kirkwood.
This driver does not completely replace the Kirkwood specific drive
When the tftp server did not send any OACK, the tftp_next_ack variable
was not set to the correct value . As the server was transmitting
blocks we generated a lot of 'Received unexpected block: $n, expected
$n+1' error messages. Depending on the timeout setting the transfer
could still complete
Hi Padmarao,
On 11/27/20 12:04 PM, Padmarao Begari wrote:
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Anup Patel
> ---
> doc/board/index.rst | 1 +
> doc/boar
Am Donnerstag, den 12.11.2020, 16:35 +0800 schrieb Weijie Gao:
> Previous the dts files for gardena-smart-gateway-mt7688 and
> linkit-smart-7688 are set to be built when mtmips is selected.
>
> This can lead to a compilation error if another soc is added to this arch
> with different dtsi files.
>
Hi Padmarao,
On 11/27/20 12:04 PM, Padmarao Begari wrote:
> This patch set adds Microchip PolarFire SoC Icicle Kit support
> to RISC-V U-Boot.
>
> The patches are based upon latest U-Boot tree
> (https://gitlab.denx.de/u-boot/u-boot.git) at commit id
> 7889951d0f56eab746a7c8fde350a022ba0361ca
>
>
On 11/27/20 1:43 PM, Bin Meng wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Padmarao,
>
> On Fri, Nov 27, 2020 at 8:18 PM Padmarao Begari
> wrote:
>> Add device tree for Microchip PolarFire SoC Icicle Kit.
snip
>> --- /dev/null
>> +++
Am Mittwoch, den 28.10.2020, 15:10 +0100 schrieb Stefan Roese:
> Add a tool to update or insert an Octeon specific header into the U-Boot
> image. This is needed e.g. for booting via SPI NOR, eMMC and NAND.
>
> While working on this, move enum cvmx_board_types_enum and
> cvmx_board_type_to_string(
Hi Marek,
> -Original Message-
> From: Marek Vasut
> Sent: 04 November 2020 19:24
> To: Biju Das ; Nobuhiro Iwamatsu
>
> Cc: u-boot@lists.denx.de; Chris Paterson ;
> Prabhakar Mahadev Lad
> Subject: Re: [PATCH v5 1/2] arm: rmobile: Add RZ/G2[HMNE] SoC support
>
> On 11/3/20 11:06 AM, B
On 27/11/2020 17:28, Stefan Agner wrote:
> From: Pascal Vizeli
>
> Add SoC revision to environment. This can be useful to select the
> correct device tree at runtime (N2/N2+).
>
> Signed-off-by: Pascal Vizeli
> Signed-off-by: Stefan Agner
> ---
>
> arch/arm/include/asm/arch-meson/boot.h | 4
On 27/11/2020 17:28, Stefan Agner wrote:
> Move loading of socinfo into a separate function so the value can be
> reused later.
>
> Signed-off-by: Stefan Agner
> ---
>
> arch/arm/mach-meson/board-info.c | 14 +-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arc
In the previous patches we only introduced a minimal subset of the
EFI_TCG2_PROTOCOL protocol implementing GetCapability().
So let's continue adding features to it, introducing the
GetEventLog() and HashLogExtendEvent() functions.
In order to do that we first need to construct the eventlog in memo
A previous commit is adding EFI_TCG2_PROTOCOL, which in it's eventlog
support registers an EFI configuration table.
Let's add the necessary GUID so 'efidebug table' command can display
table names properly.
Signed-off-by: Ilias Apalodimas
---
cmd/efidebug.c | 4
1 file changed, 4 insertions
A following patch introduces support for the EFI_TCG2_PROTOCOL
evenlog management.
Introduce the necessary tpm related headers
Signed-off-by: Ilias Apalodimas
---
include/tpm-v2.h | 59
1 file changed, 59 insertions(+)
diff --git a/include/tpm-v2
A previous patch introduced the basic functionality of the protocol, only
adding support for GetCapability().
In order for the protocol to be useful an eventlog is required.
EFI applications can use the service to extend the TPM PCRs and log the
events on an eventlog, that can be passed into linux
From: Pascal Vizeli
Add SoC revision to environment. This can be useful to select the
correct device tree at runtime (N2/N2+).
Signed-off-by: Pascal Vizeli
Signed-off-by: Stefan Agner
---
arch/arm/include/asm/arch-meson/boot.h | 4
arch/arm/mach-meson/board-info.c | 12 ++
Move loading of socinfo into a separate function so the value can be
reused later.
Signed-off-by: Stefan Agner
---
arch/arm/mach-meson/board-info.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-meson/board-info.c b/arch/arm/mach-meson/board-inf
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
doc/board/index.rst | 1 +
doc/board/microchip/index.rst | 9 +
doc/board/microchip/mpfs_icicle.rst | 8
Read phy address from device tree and use it to find the phy device
if not found then search in the range of 0 to 31.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/net/macb.c b/drivers/net
This patch adds Microchip MPFS Icicle Kit support. For now, only
NS16550 Serial, Microchip clock, Cadence eMMC and MACB drivers are
only enabled. The Microchip MPFS Icicle defconfig by default builds
U-Boot for S-Mode because U-Boot on Microchip PolarFire SoC will run
in S-Mode as payload of HSS +
Add device tree for Microchip PolarFire SoC Icicle Kit.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/dts/Makefile | 1 +
.../dts/microchip-mpfs-icicle-kit-u-boot.dtsi | 14 +
arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 421 ++
Enable 32-bit or 64-bit DMA in the macb driver based on the macb
compatible string of the device tree node.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/net/macb.c | 131 +++--
drivers/net/macb.h | 6 +++
2 files changed, 120 inser
Add clock driver code for the Microchip PolarFire SoC. This driver
handles reset and clock control of the Microchip PolarFire SoC device.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile
This patch set adds Microchip PolarFire SoC Icicle Kit support
to RISC-V U-Boot.
The patches are based upon latest U-Boot tree
(https://gitlab.denx.de/u-boot/u-boot.git) at commit id
7889951d0f56eab746a7c8fde350a022ba0361ca
All drivers namely: NS16550 Serial, Microchip clock,
Cadence eMMC and Cad
dma_addr_t holds any valid DMA address. If the DMA API only uses 32/64-bit
addresses, dma_addr_t need only be 32/64 bits wide.
Signed-off-by: Padmarao Begari
Reviewed-by: Anup Patel
---
arch/riscv/Kconfig | 4
arch/riscv/include/asm/types.h | 4
2 files changed, 8 insertio
Hi,
I did a guess and reverted the following in the actual git from
arch/arm/dts/meson-gxbb.dtsi of the bad commit
and booting from emmc on odroid-c worked again:
@@ -354,11 +381,17 @@
};
emmc_pins: emmc {
- mux {
+ mux-0 {
On Fri, Nov 27, 2020 at 05:46:54PM +0200, Andy Shevchenko wrote:
> xFSTK sources got a new home under Edison Firmware Group on GitHub [1].
> Update Intel Edison documentation accordingly.
>
> While here, fix couple of typos.
Please, discard this. V2 is better.
--
With Best Regards,
Andy Shevche
xFSTK sources got a new home under Edison Firmware Group on GitHub [1].
Update Intel Edison documentation accordingly.
While here, fix couple of typos.
[1]: https://github.com/edison-fw
Signed-off-by: Andy Shevchenko
---
v2: more fixes to have nice looking PDF
doc/board/intel/edison.rst | 49 +
xFSTK sources got a new home under Edison Firmware Group on GitHub [1].
Update Intel Edison documentation accordingly.
While here, fix couple of typos.
[1]: https://github.com/edison-fw
Signed-off-by: Andy Shevchenko
---
doc/board/intel/edison.rst | 32 +---
1 file
Good day,
I ran into a problem with a Raspberry Pi 4 setup and this seems to be a
U-boot issue.
Setup:
RPi 4 - 4GB
Home assistant 5.x / 64 bits
Startech USB SATA
Crucial MX500 SSD
Arduino Mega USB connected
The problem is also mentioned at the hassio github:
https://github.com/home-assistant/o
Synchronize RZ/G2H SoC DTs and HiHope board DTs files with mainline
Linux 5.10-rc5 commit 418baf2c28f34 ("Linux 5.10-rc5")
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v7:
* New patch
---
arch/arm/dts/r8a774e1-hihope-rzg2h-ex.dts |5 +
arch/arm/dts/r8a774e1-hihope-rzg2h.dts|
The HiHope RZ/G2H board from HopeRun consists of main board
(HopeRun HiHope RZ/G2H main board) and sub board(HopeRun
HiHope RZ/G2H sub board). The HiHope RZ/G2H sub board sits
below the HiHope RZ/G2H main board.
DTS files apart from r8a774e1-hihope-rzg2h-u-boot.dts and
r8a774e1-u-boot.dtsi have be
The HiHope RZ/G2M board from HopeRun consists of main board
(HopeRun HiHope RZ/G2M main board) and sub board(HopeRun
HiHope RZ/G2M sub board). The HiHope RZ/G2M sub board sits
below the HiHope RZ/G2M main board.
DTS files apart from r8a774a1-hihope-rzg2m-u-boot.dts and
r8a774a1-u-boot.dtsi have be
The HiHope RZ/G2N board from HopeRun consists of main board
(HopeRun HiHope RZ/G2N main board) and sub board(HopeRun
HiHope RZ/G2N sub board). The HiHope RZ/G2N sub board sits
below the HiHope RZ/G2N main board.
DTS files apart from r8a774b1-hihope-rzg2n-u-boot.dts and
r8a774b1-u-boot.dtsi have be
This patch series adds the required SoC/Board support to boot HopeRun
HiHope RZ/G2[HMN] boards. This patch series depend on [1]
[1]
http://u-boot.10912.n7.nabble.com/PATCH-v7-0-4-Add-CPU-identification-support-for-RZ-G2-SoC-s-td433694.html
v6->v7
*
http://u-boot.10912.n7.nabble.com/PATCH-v6-0-
On 11/27/20 5:20 AM, Patrick Delaunay wrote:
Reorder test on gd value and remove the duplicated test (!gd)
in putc and puts function.
This patch is a preliminary step for rework of this function.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- update gd test in console function puts and
On 11/27/20 5:20 AM, Patrick Delaunay wrote:
Use the console puts functions to output the traces before
the log initialization (when CONFIG_LOG is not activated).
This patch allows to display the first U-Boot traces
(with macro debug) when CONFIG_DEBUG_UART is activated
and not only drop them.
Am Mittwoch, den 28.10.2020, 15:10 +0100 schrieb Stefan Roese:
> Using ram_get_info() is complicated and does not work after relocation.
> Now that gd->ram_size holds the full RAM size, let's use it instead and
> remove the ram_get_size logic completely.
>
> Signed-off-by: Stefan Roese
> Cc: Aaro
Am Mittwoch, den 28.10.2020, 15:10 +0100 schrieb Stefan Roese:
> With this patch, gd->ram_size now holds to full RAM size detected by the
> DDR init code. It introduces the get_effective_memsize() function to
> report the maximum usable RAM size in U-Boot to the system instead.
>
> Signed-off-by:
On 11/27/20 5:20 AM, Patrick Delaunay wrote:
Add a check of the _log function with LOGL_FORCE_DEBUG flags,
used to force the trace display.
The trace should be displayed for all the level when flags
have LOGL_FORCE_DEBUG bit is set, for any filter.
Signed-off-by: Patrick Delaunay
---
Changes
Am Mittwoch, den 28.10.2020, 15:09 +0100 schrieb Stefan Roese:
> Octeon has a specific boot header, when booted via SPI NOR, NAND or MMC.
> Here the only 2 instructions are allowed in the first few bytes of the
> image. And these instructions need to be one branch and a nop. This
> patch adds the n
Add SDHI quirks for R-Car M3-N and RZ/G2N SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v7:
* No Change.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc
Add SDHI quirks for R-Car H3 and RZ/G2H SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v7:
* No Change.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 33 -
1 file changed, 32 insertions(+), 1 deletion(-)
diff -
Add SDHI quirks for R-Car M3-W and RZ/G2M SoC.
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
v7:
* Incorporated Jaehoon Chung's review comments.
* Fixed the build error on Renesas ARM32 platforms.
v6:
* New patch. quirks using soc_device_match.
---
drivers/mmc/renesas-sdhi.c | 117 +
RZ/G2 SoC's are identical to R-Car Gen3 SoC's apart from some
automotive peripherals.
RZ/G2H (R8A774E1) = R-Car H3-N (R8A77951).
RZ/G2M (R8A774A1) = R-Car M3-W (R8A77960).
RZ/G2N (R8A774B1) = R-Car M3-N (R8A77965).
RZ/G2E (R8A774C0) = R-Car E3 (R8A77990).
As the devices are the same they also hav
This patch series aims to add CPU identification support for RZ/G2 SoC's
and adding SDHI quirks using SoC identification driver.
This patch series depend on SoC identification driver[1]
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=214706
Biju Das (4):
arm: rmobile: Add RZ/G2[HMNE
On 11/27/20 5:20 AM, Patrick Delaunay wrote:
Update _log function to drop any traces when log is yet initialized:
vsnprintf is no more executed in this case.
This patch allows to reduce the cost for the dropped early debug trace.
Reviewed-by: Simon Glass
Signed-off-by: Patrick Delaunay
---
(
Am Montag, den 23.11.2020, 15:16 +0200 schrieb Ovidiu Panait:
> In order to remove the arch-specific ifdefs around initr_trap, introduce
> arch_initr_trap weak initcall. Implementations for ppc/m68k/mips have
> been moved to arch//lib/traps.c
>
> Default implementation is a nop stub.
>
> Signed-o
Am 25. November 2020 08:32:08 MEZ schrieb AKASHI Takahiro
:
>Heinrich,
>
>On Wed, Nov 25, 2020 at 07:42:31AM +0100, Heinrich Schuchardt wrote:
>> Am 25. November 2020 02:05:06 MEZ schrieb AKASHI Takahiro
>:
>> >Heinrich,
>> >
>> >On Tue, Nov 24, 2020 at 09:23:50PM +0100, Heinrich Schuchardt wrote:
On 22/11/20 4:37 am, Simon Glass wrote:
> Hi,
>
> On Wed, 18 Nov 2020 at 10:55, Vignesh Raghavendra wrote:
>>
>>
>>
>> On 11/18/20 8:44 PM, Aswath Govindraju wrote:
>>> Hi Simon,
>>>
>>> On 18/11/20 8:07 pm, Simon Glass wrote:
Hi Aswath,
On Mon, 16 Nov 2020 at 07:29, Aswath Govindr
Hi Padmarao,
On Fri, Nov 27, 2020 at 8:18 PM Padmarao Begari
wrote:
>
> Add device tree for Microchip PolarFire SoC Icicle Kit.
>
> Signed-off-by: Padmarao Begari
> Reviewed-by: Anup Patel
> ---
> arch/riscv/dts/Makefile | 1 +
> .../dts/microchip-mpfs-icicle-kit-u-boot
None of the driver for Edison is using DM_PCI_COMPAT, hence drop it.
Signed-off-by: Andy Shevchenko
---
configs/edison_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/edison_defconfig b/configs/edison_defconfig
index c69c3f883c19..ab2811eca9dc 100644
--- a/configs/edison_def
It appears that U-Boot works by luck on Intel Edison board because the amount
of RAM is less than 1 GB and standard way of calculating the top of it work
for this configuration. However, this won't work if the amount of RAM is
different and split differently in address space. We have to fine the su
From: zhengxun
This patch adds an implementation of exec_op, which support octal mode
and quad mode for reading flash and support existing single mode for
reading and writing flash concurrently.
Signed-off-by: zhengxun
---
drivers/spi/renesas_rpc_spi.c | 144 ++
From: zhengxun
Add U-Boot SPI Flash support for the Renesas Draak board and configure
RX and TX bus-width values to support octal I/O mode.
Signed-off-by: zhengxun
---
arch/arm/dts/r8a77995-u-boot.dtsi | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts
From: zhengxun
The spi0 alias is needed by the environment code to retrieve the SPI
flash. This patch provides the spi0 aliases, for Renesas Draak board.
Signed-off-by: zhengxun
---
arch/arm/dts/r8a77995-draak.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/r8a77995-draak.
From: zhengxun
The MX66UW2G345G is Macronix Flash with SINGLE and OCTAL I/O. Hence,
add SPI_NOR_OCTAL_READ flag for this flash.
Signed-off-by: zhengxun
---
drivers/mtd/spi/spi-nor-ids.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-
From: zhengxun
The MX66UW2G345G is Macronix flash with single and octal mode. Hence, for
testing purposes, this patch adds SPI-MEM framework to support the octal mode
on Renesas Draak board. The datasheet can be found in
https://www.macronix.com/zh-tw/products/NOR-Flash/Pages/octaflash.aspx#1.8V.
Nobody interested or is subject formatting wrong so it slips through all
filters?
Am 23.11.2020 um 14:23 schrieb Michael Lawnick:
Hi,
before starting to walk the troublesome way on my own:
Is there any development for EFI_SPI, EFI_I2C and/or EFI_PCI ongoing?
I will have to write an EFI applic
Remove the specific sandbox code in console.c, as the config
CONFIG_DEBUG_UART is already supported in drivers/serial/sandbox.c
and activated by default in all sandbox defconfig
(CONFIG_DEBUG_UART_SANDBOX=y and CONFIG_DEBUG_UART=y).
This patch allows to test the console code under DEBUG_UART in sa
Add CONFIG_DEBUG_UART=y for all sandbox defconfig
as it is already done in sandbox_defconfig.
Signed-off-by: Patrick Delaunay
---
configs/sandbox64_defconfig| 1 +
configs/sandbox_flattree_defconfig | 1 +
configs/sandbox_spl_defconfig | 1 +
3 files changed, 3 insertions(+)
diff
Add test for dropped trace before log_init, displayed by debug uart.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- Add test of displayed messages requested before log_init (NEW)
arch/sandbox/cpu/start.c | 5 +
test/py/tests/test_log.py | 11 +++
2 files changed, 16 inserti
Add a new test to check the dropped messages when LOG is not ready
with log_drop_count and the result of _log().
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- add test to count the dropped messages (NEW)
test/log/log_test.c | 43 +++
1 file change
Allow to record the console output before before U-Boot
has a console ready.
This patch allows to test the console output in sandbox test
based on console record.
It is possible because GD_FLG_RECORD and GD_FLG_SERIAL_READY
are 2 independent flags.
Signed-off-by: Patrick Delaunay
---
Changes i
Add a new test to check the content of the dropped messages
sent to console puts function.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- added test for content of dropped messages (NEW)
test/log/log_test.c | 8
1 file changed, 8 insertions(+)
diff --git a/test/log/log_test.c b
Reduce the log overhead when the traces are filtered,
by moving the vsnprintf call from _log() to log_dispatch().
This patch avoids the printf treatment when LOG features is
activated, but trace is filtered, for example when
MAX_LOG_LEVEL=8 and LOG_DEFAULT_LEVEL=6.
Reviewed-by: Simon Glass
Signe
Reorder test on gd value and remove the duplicated test (!gd)
in putc and puts function.
This patch is a preliminary step for rework of this function.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- update gd test in console function puts and putc (cosmetic)
common/console.c | 16 +++
Use the console puts functions to output the traces before
the log initialization (when CONFIG_LOG is not activated).
This patch allows to display the first U-Boot traces
(with macro debug) when CONFIG_DEBUG_UART is activated
and not only drop them.
For example for traces in board_f.c requested b
It is the V2 of [1], rebased and with added tests.
To allow test (with console record), I replace the debug uart
function used to display the dropped messages printascii() by
the console generic function puts().
This function allows to support all the features defined in
console.c (as DEBUG_UAR
Add a check of the _log function with LOGL_FORCE_DEBUG flags,
used to force the trace display.
The trace should be displayed for all the level when flags
have LOGL_FORCE_DEBUG bit is set, for any filter.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- Add test for LOGL_FORCE_DEBUG (NEW)
Update _log function to drop any traces when log is yet initialized:
vsnprintf is no more executed in this case.
This patch allows to reduce the cost for the dropped early debug trace.
Reviewed-by: Simon Glass
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
common/log.c | 13 ++
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