On 3/8/21 4:35 AM, Ye Li wrote:
[...]
+static int ehci_iaa_cycle(struct ehci_ctrl *ctrl)
+{
+ u32 cmd, status;
+ int ret;
+
+ /* Enable Interrupt on Async Advance Doorbell. */
+ cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
+ cmd |= CMD_IAAD;
+ ehci_writel(&ctrl->h
Hi Jagan,
On 2/26/2021 7:35 PM, Jagan Teki wrote:
> On Fri, Feb 19, 2021 at 7:26 AM wrote:
>>
>> From: Takahiro Kuwano
>>
>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>>
>> https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
>> https://www.cypre
On 2/24/2021 9:40 PM, Pratyush Yadav wrote:
> On 19/02/21 10:56AM, tkuw584...@gmail.com wrote:
>> From: Takahiro Kuwano
>>
>> This patch adds Flash specific fixups and hooks for Cypress
>> S25HL-T/S25HS-T family, based on the features introduced in [0][1][2].
>
> Instead of linking the patches li
On 3/8/21 8:01 AM, Marek BehĂșn wrote:
When compiling with LTO, the compiler fails with an error saying that
`crc_table` causes a section type conflict with `efi_var_buf`.
This is because both are declared to be in the same section (via macro
`__efi_runtime_data`), but one is const while the othe
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> Now that proper DM clock and reset driver exists for Display Engine 2
> and 3, remove all clock and reset related code and use appropriate
> framework instead.
>
> Signed-off-by: Jernej Skrabec
> ---
Reviewed-by: Jagan Teki
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> These clocks and resets are needed for video drivers.
>
> Cc: Lukasz Majewski
> Signed-off-by: Jernej Skrabec
> ---
Reviewed-by: Jagan Teki
On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec wrote:
>
> Video driver currently manages clocks and resets by directly writing to
> registers. This is already a bit messy because each SoC has some
> specifics. It's much better to implement proper clock and reset driver
> which takes information fro
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