于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang 写到:
>Hi Icenowy Zheng,
>
>In my view, it is better to implement this mechanism in phy-uclass
>which
>resemble Linux Kernel have implemented that can avoid do duplication of
>
>work in each SoC's PHY driver.
I'm afraid of breaking existing drivers wh
This patch adds the PCIe host controller driver for MIPS Octeon II/III.
The driver mainly consist of the PCI config functions, as all of the
complex serdes related port / lane setup, is done in the serdes / pcie
code available in the "arch/mips/mach-octeon" directory.
Signed-off-by: Stefan Roese
Hi Icenowy Zheng,
In my view, it is better to implement this mechanism in phy-uclass which
resemble Linux Kernel have implemented that can avoid do duplication of
work in each SoC's PHY driver.
BR.
Frank
On 2021/4/6 23:10, Icenowy Zheng wrote:
The OHCI and EHCI controllers are both bound t
Hi Stefano,
Please pull nxp-imx-2021-4-6.
This PR is based on Tom's master branch.
If you need me rebase on imx/master, I could redo this PR.
This is quite a large PR, since lots stuff in downstream tree.
CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/7046
With of-platdata-inst we want to set up a reference to each devices'
parent device, if there is one. If we find that the device has a parent
(i.e. is not a root node) but it is not in the list of devices being
written, then we cannot create the reference.
Report an error in this case, since it ind
With the new 2021.04 we have a new version of Chromium OS boot, which
supports sandbox, coral and coral-on-coreboot. Add documentation for
this.
Signed-off-by: Simon Glass
---
doc/chromium/run_vboot.rst | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/doc/chro
All the x86 devicetree files are built at once, whichever board is
actually being built. If coreboot is the target build, CONFIG_ROM_SIZE
is not defined and samus cannot build Chromium OS verified boot. Add
this condition to avoid errors about CONFIG_ROM_SIZE being missing.
Signed-off-by: Simon Gl
Add information about memory usage when U-Boot is started from coreboot.
This is useful when debugging. Also, since coreboot takes a chunk of
memory in the middle of SDRAM for use by PCI devices, it can help avoid
overwriting this with a loaded kernel by accident.
Signed-off-by: Simon Glass
---
Enable this by default on coreboot, since it is quite useful there.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index b97c2779041..11385918d83 100644
--- a/arch/x86
Use VENDOR_COREBOOT instead of TARGET_COREBOOT so we can have multiple
coreboot boards, sharing options. Only SYS_CONFIG_NAME needs to be
defined TARGET_COREBOOT.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/Kconfig | 2 +-
board/coreboot/coreboot/Kconfig | 12
2 files c
Add a function comment for get_coreboot_info() and a declaration for
cb_get_sysinfo(), since this may be called from elsewhere.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/cb_sysinfo.h | 16
1 file changed, 16 insertions(+)
diff --git a/arch/x86/include/asm/cb_sysinfo.
Set up coral so that it can boot from coreboot, even though it is a
bare-metal build. This helps with testing since the same image can be used
in both cases.
Signed-off-by: Simon Glass
---
board/google/chromebook_coral/coral.c | 28 +++
1 file changed, 28 insertions(+)
The BIOS version may not be present, e.g. on a Chrome OS build. Add the
BIOS date as well, so we get some sort of indication of coreboot's
vintage.
Signed-off-by: Simon Glass
---
board/coreboot/coreboot/coreboot.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/coreboot/coreboot/co
A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add
When booting from coreboot we may not have a PCH driver available. The
SPI driver can operate without the PCH but currently complains in this
case. Update it to continue to work normally. The only missing feature
is memory-mapping of SPI-flash contents, which is not essential.
Signed-off-by: Simon
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for t
These headers are not actually used. Drop them so that this driver can
be used by other boards, e.g. coreboot.
Signed-off-by: Simon Glass
---
drivers/tpm/cr50_i2c.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c
index 76432bdec1f..7a2b5a4faa
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.
Skip that step in this case.
Signed-off-by: Simon Glass
---
arch/x86/cpu/i386/cpu.c | 2 +-
1 file chang
At present this driver relies on coreboot to provide information about
the console UART. However if coreboot is not compiled with the UART
enabled, the information is left out. This configuration is quite
common, e.g. with shipping x86-based Chrome OS Chromebooks.
Add a way to determine the UART s
At present only bridge devices are bound before relocation, to save space
in pre-relocation memory. In some cases we do actually want to bind a
device, e.g. because it provides the console UART. Add a devicetree
binding to support this.
Use the PCI_VENDEV() macro to encode the cell value. This is
These functions don't modify the device-ID struct that is passed in, so
mark the argument as const, so the data structure can be declared that
way. This allows it to be placed in the rodata section.
Signed-off-by: Simon Glass
---
drivers/pci/pci-uclass.c | 6 +++---
include/pci.h| 4
Various issues were discovered in getting Chromium OS verified boot
running on top of coreboot, booting into U-Boot.
Improvements include:
- enable serial console if even coreboot doesn't
- enable cache always
- show the BIOS date since Chromium OS's coreboot doesn't have a version
- update docs
-
instead using ls and awk to determine file size use stat instead.
This fixes an invalid size reporting for user or group names that have
spaces in them.
This adds a dependency on the stat application which is part of
the coreutils package which also includes ls.
Signed-off-by: Tim Harvey
---
ar
From: Takahiro Kuwano
Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.
Signed-off-by: Takahiro Kuwano
---
Changes in v6:
- Remove spansion_quad_enable_volatile() per comment in
https://patchwork.ozlabs.org/project/uboot/patch/a5c3cf1353d9a621379e2fcfefc51fb44c9680c5.1611729896.git.t
From: Takahiro Kuwano
The nor->ready() and spansion_sr_ready() introduced earlier in this
series are used for multi-die package parts.
The nor->quad_enable() sets the volatile QE bit on each die.
The nor->erase() is hooked if the device is not configured to uniform
sectors, assuming it has 32 x
From: Takahiro Kuwano
Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.
Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).
This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode f
From: Takahiro Kuwano
The spansion_sr_ready() reads status register 1 by Read Any Register
commnad. This function is called from Flash specific hook with die address
and dummy cycles to support multi-die package parts from Spansion/Cypress.
Signed-off-by: Takahiro Kuwano
Reviewed-by: Pratyush Y
From: Takahiro Kuwano
For dual/quad die package devices from Spansion/Cypress, the device's
status needs to be checked by reading status registers in all dies, by
using Read Any Register command. To support this, a Flash specific hook
that can overwrite the legacy status check is needed.
Signed-
From: Takahiro Kuwano
Some of Spansion/Cypress chips support volatile version of configuration
registers and it is recommended to update volatile registers in the field
application due to a risk of the non-volatile registers corruption by
power interrupt. This patch adds a function to set Quad En
From: Takahiro Kuwano
Some of Spansion/Cypress chips support Read/Write Any Register commands.
These commands are mainly used to write volatile registers and access to
the registers in second and subsequent die for multi-die package parts.
The Read Any Register instruction (65h) is followed by r
From: Takahiro Kuwano
Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
bottom, depending on the device configuration, while U-Boot supports
uniform sector layout only.
The spansion_erase_non_uniform() erases overlaid 4KB sectors,
non-overlaid portion of normal sector, and
From: Takahiro Kuwano
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
The full version can be found in the following links (regi
From: Pratyush Yadav
Sometimes the information in a flash's SFDP tables is wrong. Sometimes
some information just can't be expressed in the SFDP table. So,
introduce the fixup hooks to allow tailoring settings for a specific
flash.
Three hooks are added: default_init, post_sfdp, and post_bfpt. T
From: Takahiro Kuwano
This patch adds Cypress manufacturer ID (34h) definition.
Signed-off-by: Takahiro Kuwano
Reviewed-by: Pratyush Yadav
---
include/linux/mtd/spi-nor.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b2e9e0
From: Pratyush Yadav
On devices with non-uniform sector sizes like Spansion S25 or S28 family
of flashes the sector under erase does not necessarily have to be
mtd->erasesize bytes long. For example, on S28 flashes the first 128 KiB
region is composed of 32 4 KiB sectors, then a 128 KiB sector, a
From: Pratyush Yadav
These structures will be used in a later commit inside another structure
definition. Also take the declarations out of the ifdef since they won't
affect the final binary anyway and will be used in a later commit.
Signed-off-by: Pratyush Yadav
---
Taken from Pratyush's seri
From: Pratyush Yadav
nor->setup() can be used by flashes to configure settings in case they
have any peculiarities that can't be easily expressed by the generic
spi-nor framework. This includes things like different opcodes, dummy
cycles, page size, uniform/non-uniform sector sizes, etc.
Move re
From: Takahiro Kuwano
The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
The summary datasheets can be found in the following links.
https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die)
https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)
On 2021/4/3 上午5:47, Peter Robinson wrote:
There's not currently any network support on the rock but
the minor network config still triggers the DM_ETH warning
even though there's no even a USB network interface so lets
disable network support to mitigate the warning.
Signed-off-by: Peter Robin
On 2021/4/3 上午5:48, Peter Robinson wrote:
There's currently no network enabled in the sheep
but we now have all the bits in place so enable the
driver and DM_ETH to fix the warning.
Signed-off-by: Peter Robinson
Cc: Andy Yan
Reviewd-by: Kever Yang
Thanks,
- Kever
---
configs/sheep-rk
On 2021/4/3 上午5:47, Peter Robinson wrote:
There's currently no network enabled in the geekbox
but we now have all the bits in place so enable the
driver and DM_ETH to fix the warning.
Signed-off-by: Peter Robinson
Cc: "Andreas Färber"
Reviewd-by: Kever Yang
Thanks,
- Kever
---
config
I've been using bootstopkeysha256 and, if I want to make it completely
impossible to enter, just setting it to an impossible value. To do this,
I do have an additional patch to common/autoboot.c that calls the password
mechanism one last time after a bootcmd fails and loops until reset if it
isn'
Hi Green,
On Tue, Apr 6, 2021 at 11:34 PM Green Wan wrote:
>
> On Tue, Apr 6, 2021 at 4:57 PM Bin Meng wrote:
> >
> > On Fri, Mar 26, 2021 at 11:54 PM Green Wan wrote:
> > >
> > > Rename fu540_ddr.c to sifive_ddr.c and add fu740 support
> > >
> > > Signed-off-by: Green Wan
> > > ---
> > > dri
Hi Peng,
On 4/6/21 7:02 PM, Peng Fan wrote:
>> Subject: RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there
>> are data"
>>
>> Hi Jaehoon
>>
>>> Did you test on latest u-boot? v2018.01 was too old version.
>>>
>> Yes, we tested on v2020.04, although there is no such issue, but I think
On Tue, Apr 6, 2021 at 2:54 PM Sean Anderson wrote:
>
>
>
> On 4/6/21 4:10 PM, Marek Vasut wrote:
> > On 4/6/21 9:52 PM, Tim Harvey wrote:
> >> On Mon, Apr 5, 2021 at 10:36 AM Marek Vasut wrote:
> >>>
> >>> On 4/5/21 6:27 PM, Tim Harvey wrote:
> On Sat, Apr 3, 2021 at 12:09 PM Marek Vas
On Tue, Apr 6, 2021 at 4:11 PM Icenowy Zheng wrote:
>
> The OHCI and EHCI controllers are both bound to the same PHY. They will
> both do init and power_on operations when the controller is brought up
> and both do power_off and exit when the controller is stopped. However,
> the PHY uclass of U-B
On 4/3/21 6:47 AM, Peter Robinson wrote:
> The odroid has USB ethernet so enable DM Ethernet support.
>
> Signed-off-by: Peter Robinson
> Jaehoon Chung
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> configs/odroid_defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
On 4/5/21 11:44 PM, Aswath Govindraju wrote:
> From: Faiz Abbas
>
> Enable HS400 speed mode by writing to HOST_CONTROL2 register.
>
> Signed-off-by: Faiz Abbas
> Signed-off-by: Aswath Govindraju
Reviewed-by: Jaehoon Chung
Best Regards,
Jaehoon Chung
> ---
> drivers/mmc/sdhci.c | 3 +++
>
On 4/6/21 10:52 PM, Klaus Heinrich Kiwi wrote:
> When building the SPL with MMC config and CONFIG_LOGLEVEL > 7, the
> function mmc_select_mode() at drivers/mmc/mmc.c will call
> mmc_mode_name() which is only defined if CONFIG_IS_ENABLED(MMC_VERBOSE)
> which doesn't have a corresponding CONFIG_SPL_M
On Tue, Apr 6, 2021 at 4:40 AM Manuel Reis wrote:
> in the early SPL boot stage whenever there is a call to udelay,
> dm_timer_init fails to find the pit timer whenever it traverses
> the device tree, if this property is not present
>
> Signed-off-by: Manuel Reis
> CC: Eugen Hristev
> ---
> ar
On 4/6/21 4:10 PM, Marek Vasut wrote:
> On 4/6/21 9:52 PM, Tim Harvey wrote:
>> On Mon, Apr 5, 2021 at 10:36 AM Marek Vasut wrote:
>>>
>>> On 4/5/21 6:27 PM, Tim Harvey wrote:
On Sat, Apr 3, 2021 at 12:09 PM Marek Vasut wrote:
>
> On 4/3/21 6:43 PM, Tim Harvey wrote:
>
>
> Il 06/04/2021 16:26 Rob Herring ha scritto:
>
>
> On Tue, Mar 16, 2021 at 8:26 PM Bin Meng wrote:
> >
> > Hi Dario,
> >
> > On Wed, Mar 17, 2021 at 4:57 AM Dario Binacchi wrote:
> > >
> > > Hi Bin,
> > >
> > > > Il 16/03/2021 02:28 Bin Meng ha scritto:
> > > >
> > > >
> > > > Hi Dario,
>
On 4/6/21 9:52 PM, Tim Harvey wrote:
On Mon, Apr 5, 2021 at 10:36 AM Marek Vasut wrote:
On 4/5/21 6:27 PM, Tim Harvey wrote:
On Sat, Apr 3, 2021 at 12:09 PM Marek Vasut wrote:
On 4/3/21 6:43 PM, Tim Harvey wrote:
Hi,
[...]
And those config options I had enabled in u-boot defconfig:
CO
On 4/6/21 9:34 PM, Harm Berntsen wrote:
[...]
diff --git a/drivers/phy/nop-phy.c b/drivers/phy/nop-phy.c
index 84aac806230..9f12ebc0624 100644
--- a/drivers/phy/nop-phy.c
+++ b/drivers/phy/nop-phy.c
@@ -43,6 +43,7 @@ static int nop_phy_probe(struct udevice *dev)
static const struct udevice_i
On Mon, Apr 5, 2021 at 10:36 AM Marek Vasut wrote:
>
> On 4/5/21 6:27 PM, Tim Harvey wrote:
> > On Sat, Apr 3, 2021 at 12:09 PM Marek Vasut wrote:
> >>
> >> On 4/3/21 6:43 PM, Tim Harvey wrote:
> >>
> >> Hi,
> >>
> >> [...]
> >>
> >> And those config options I had enabled in u-boot defconfig:
On Fri, 2021-04-02 at 14:47 +0200, Marek Vasut wrote:
> The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver
> is
> compatible with USB no-op PHY, so add the compatible string.
>
> Signed-off-by: Marek Vasut
> Cc: Alexey Brodkin
> Cc: Eugeniy Paltsev
> Cc: Fabio Estevam
> Cc:
The following changes since commit 472fd5a35af3308f97de0376a6c25f5368035557:
Merge tag 'rockchip-for-v2021.07' of
https://source.denx.de/u-boot/custodians/u-boot-rockchip (2021-04-05
22:39:10 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git master
for y
t;
> Merge branch 'next' (2021-04-05 11:29:57 -0400)
>
> are available in the Git repository at:
>
> https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
> tags/u-boot-amlogic-20210406
>
> for you to fetch changes up to 2fbd37001c77f0b78d43c578d8e350a6a
On Tue, Apr 06, 2021 at 12:30:41PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Tue, Apr 06, 2021 at 10:45:56AM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following cfi-flash related patches:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Tue, Apr 06, 2021 at 07:14:45PM +1200, Simon Glass wrote:
> Hi Tom,
>
> https://source.denx.de/u-boot/custodians/u-boot-dm/-/pipelines/7013
>
>
> The following changes since commit 90eba245a66aa20589404ba537215faf2012c1a3:
>
> Merge branch 'next' (2021-04-05 11:29:57 -0400)
>
> are avail
Hi Pantelis, Rick,
Sorry I didn't cc you before. I was wondering if you could take
a look at this patch. Your comments would be most welcome. Thanks
for your time!
Best regards,
Tianrui
> This patch enables u-boot support for Openpiton SoC
> of RISC-V architecture
>
> Signed-off-by: Tianrui Wei
The sync of the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2") causes Ethernet to break on some
ODROID-C2.
Meanwhile a fix to increase the reset timing has been added to Linux.
Instead of reverting the offending commit, use the new reset timing
from upstream Linux c
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote:
> The uart nodes already provide property for the driver to
> dynamically calculate the correct clock frequency. There is no need
> to keep the hard-coded property.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/microchip-mpfs-icicle-kit.
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote:
> This driver is needed in the pre-relocation phase as the serial
> driver depends on it.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/clk/microchip/mpfs_clk.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/clk/microchip/mpfs_c
On Wed, Mar 31, 2021 at 12:55 PM Bin Meng wrote:
> The RISC-V architecture default value of CONFIG_SYS_MALLOC_F_LEN
> (0x1000) would not provide enough memory for devices like mpfs
> clock and ns16550 serial to bind well before relocation.
>
> Signed-off-by: Bin Meng
> ---
>
> configs/microchip
k, thanks, will fix it.
On Tue, Apr 6, 2021 at 5:17 PM Bin Meng wrote:
>
> On Tue, Mar 30, 2021 at 1:27 PM Green Wan wrote:
> >
> > Clear feature disable CSR to turn on all features of hart. The detail
> > is specified at section, 'SiFive Feature Disable CSR', in user manual
> >
> > https://sifi
On Tue, Apr 6, 2021 at 4:57 PM Bin Meng wrote:
>
> On Fri, Mar 26, 2021 at 11:54 PM Green Wan wrote:
> >
> > Rename fu540_ddr.c to sifive_ddr.c and add fu740 support
> >
> > Signed-off-by: Green Wan
> > ---
> > drivers/ram/sifive/Kconfig| 8 +-
> > drivers/ram/sifive/Makefi
The OHCI and EHCI controllers are both bound to the same PHY. They will
both do init and power_on operations when the controller is brought up
and both do power_off and exit when the controller is stopped. However,
the PHY uclass of U-Boot is not as sane as we thought -- they won't
maintain a statu
On 4/6/21 12:10 PM, Stefan Roese wrote:
From: Aaron Williams
Add missing endianness conversions to usb_get_port_status(). This
(amongst others) is necessary to enable the use of USB 3 hubs on
big-endian platforms like MIPS Octeon.
Applied all, thanks.
On Tue, Mar 16, 2021 at 8:26 PM Bin Meng wrote:
>
> Hi Dario,
>
> On Wed, Mar 17, 2021 at 4:57 AM Dario Binacchi wrote:
> >
> > Hi Bin,
> >
> > > Il 16/03/2021 02:28 Bin Meng ha scritto:
> > >
> > >
> > > Hi Dario,
> > >
> > > On Tue, Mar 16, 2021 at 6:49 AM Dario Binacchi wrote:
> > > >
> > >
When building the SPL with MMC config and CONFIG_LOGLEVEL > 7, the
function mmc_select_mode() at drivers/mmc/mmc.c will call
mmc_mode_name() which is only defined if CONFIG_IS_ENABLED(MMC_VERBOSE)
which doesn't have a corresponding CONFIG_SPL_MMC_VERBOSE defined in
Kconfig.
Fixes this build error:
Hi,
I also wrote on RPI forums [1] to discuss about this problem.
I'm using a CM4 module on CMIO board, with an image built by Yocto
(dunfell version) and containing u-boot version 2020.01.
When I add some overlays via config.txt file, or I change the original
Linux dts and rebuild its dtb,
> Subject: RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there
> are data"
>
> Hi Jaehoon
>
> > Did you test on latest u-boot? v2018.01 was too old version.
> >
> Yes, we tested on v2020.04, although there is no such issue, but I think it
> just
> depends on call sequence timing.
>
If force_reloc flag is not set and booti is called for an address
ouside RAM (i. e. QSPI NOR flash), we should honor that and not try
to force relocation in a bogus fashion.
Signed-off-by: Vitaly Wool
---
arch/riscv/lib/image.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --
Hi,
We have tried the latest U-Boot v2021.04 with the firmware files [1] at tag
1.20210303.
The firmware files include bcm2711-rpi-4-b.dtb, start4* and fixup4*.
Building config is the configs/rpi_4_defconfig
However, U-Boot hangs and only shows a big rainbow square on RPi 4B if UART
is not enable
The 04/06/2021 09:38, Patrick Delaunay wrote:
Hi Patrick,
I have applied your patches and I have done a basic test on jr2_switch.
It seems to work fine. I got some warnings from the function
'__of_translate_address' which I need to figure out.
But one more important thing is that also luton_swit
On 06/04/21 01:32PM, Heinrich Schuchardt wrote:
> On 06.04.21 12:22, Pratyush Yadav wrote:
> > On 06/04/21 04:30PM, Simon Glass wrote:
> >> Update this code to use IS_ENABLED() instead.
> >>
> >> Signed-off-by: Simon Glass
> >> ---
> >>
> >> cmd/sf.c | 32 ++--
> >> 1
On Tue, Apr 06, 2021 at 08:52:59AM +0800, Kever Yang wrote:
> Hi Tom,
>
> Please pull the rockchip updates/fixes:
> - Fix rk3368 lion board support;
> - Fix px30 odroid-go2 board support;
> - Add rk3399 NanoPi R4s and NanoPi M4B board support;
>
> Gitlab ci:
> https://source.denx.de/u-boot/custo
Hi Bin,
On 25/03/2021 15:49, Neil Armstrong wrote:
> With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in
> the
> Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated.
>
> This introduce a "common" DW PCIe helpers file with common code merged from
> t
t/custodians/u-boot-amlogic.git
tags/u-boot-amlogic-20210406
for you to fetch changes up to 2fbd37001c77f0b78d43c578d8e350a6afa27e24:
arm: meson: remove static ethernet link setup (2021-04-06 11:10:29 +0200)
- Add MMIO MDIO mux driver
In case exit is called in a script without parameter, the command
returns -2 ; in case exit is called with a numerical parameter,
the command returns -2 and lower. This leads to the following problem:
=> setenv foo 'echo bar ; exit 1' ; run foo ; echo $?
bar
0
=> setenv foo 'echo bar ; exit 0' ; ru
Hi Manuel,
Subject should be like this :
ARM: dts: at91: sama5d3: ...
On 4/5/21 8:46 PM, Manuel Reis wrote:
> pit timer node requires u-boot properties to be recognized
could you be more specific, where it's required, like we discussed, in
the early boot process of the SPL , it's not found if t
On 06.04.21 12:22, Pratyush Yadav wrote:
> On 06/04/21 04:30PM, Simon Glass wrote:
>> Update this code to use IS_ENABLED() instead.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> cmd/sf.c | 32 ++--
>> 1 file changed, 14 insertions(+), 18 deletions(-)
>>
>> diff --git a
Hi Peng,
On 4/6/21 7:02 PM, Peng Fan wrote:
>> Subject: RE: [PATCH] Revert "mmc: sdhci: set to INT_DATA_END when there
>> are data"
>>
>> Hi Jaehoon
>>
>>> Did you test on latest u-boot? v2018.01 was too old version.
>>>
>> Yes, we tested on v2020.04, although there is no such issue, but I think
Hi all,
I just reeived a notification from our hoster that our gitlab server
( source.denx.de ) will be offline for approx. 2 hours between now
and 15:45 CEST (urgent maintenance work).
Sorry for the inconvenience, but there is nothing we can do...
Best regards,
Wolfgang Denk
--
DENX Software
On 06/04/21 10:48AM, Takahiro Kuwano wrote:
> On 4/2/2021 4:31 AM, Pratyush Yadav wrote:
> > From: Takahiro Kuwano
> >
> > Some of Spansion/Cypress chips have overlaid 4KB sectors at top and/or
> > bottom, depending on the device configuration, while U-Boot supports
> > uniform sector layout only
Hi Tom,
please pull the following watchdog related patches:
- Enhance WDT handling (starting / stopping) and introduce
CONFIG_WATCHDOG_AUTOSTART to allow disabling of autostart of
the WDT (Pali)
On 09.03.21 14:26, Pali Rohár wrote:
Watchdog is ready after successful call of ops->start() callback in
wdt_start() function. And is stopped after successful call of ops->stop()
callback in wdt_stop function.
So move setting of GD_FLG_WDT_READY flag from initr_watchdog() function to
wdt_start()
On 06/04/21 04:30PM, Simon Glass wrote:
> Update this code to use IS_ENABLED() instead.
>
> Signed-off-by: Simon Glass
> ---
>
> cmd/sf.c | 32 ++--
> 1 file changed, 14 insertions(+), 18 deletions(-)
>
> diff --git a/cmd/sf.c b/cmd/sf.c
> index 46346fb9d43..d4f5ece
From: Aaron Williams
Accessing the xHCI controller registers should be done via the
xhci_readl/writel functions. This patch adds this to a few missing
places.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
Cc: Chandrakala Chavva
Cc: Bin Meng
Cc: Marek Vasut
---
drivers/usb/host/
This change makes debugging a bit easier as the output is better
readable with the added space. The explicit le16_to_cpu() is not
needed in the output. Also this patch moves the strings into one line
to make the patch checkpatch clean.
Signed-off-by: Stefan Roese
Cc: Aaron Williams
Cc: Chandraka
From: Aaron Williams
Add missing endianness conversions to usb_get_port_status(). This
(amongst others) is necessary to enable the use of USB 3 hubs on
big-endian platforms like MIPS Octeon.
Signed-off-by: Aaron Williams
Signed-off-by: Stefan Roese
Cc: Chandrakala Chavva
Cc: Bin Meng
Cc: Mar
Hi Peng,
On 06.04.21 11:34, Peng Fan (OSS) wrote:
Hi Stefano,
Please pull nxp-imx-2021-4-6. This PR is based on Tom's master branch. If you
need
me rebase on imx/master, I could redo this PR. This is quite a large PR, since
lots
stuff in downstream tree.
I ran local buildman test for all boa
> Subject: [PATCH v2] mmc: mtk-sd: increase the minimum bus frequency
Could you please rebase? I am not able to apply this patch.
Thanks,
Peng.
>
> With a 48MHz input clock, the lowest bus frequency can be as low as
> 4800 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause
>
in the early SPL boot stage whenever there is a call to udelay,
dm_timer_init fails to find the pit timer whenever it traverses
the device tree, if this property is not present
Signed-off-by: Manuel Reis
CC: Eugen Hristev
---
arch/arm/dts/sama5d3.dtsi | 1 +
1 file changed, 1 insertion(+)
diff
Hi Stefano,
Please pull nxp-imx-2021-4-6. This PR is based on Tom's master branch. If you
need
me rebase on imx/master, I could redo this PR. This is quite a large PR, since
lots
stuff in downstream tree.
I ran local buildman test for all boards, no issue found.
On Tue, Mar 30, 2021 at 1:27 PM Green Wan wrote:
>
> Clear feature disable CSR to turn on all features of hart. The detail
> is specified at section, 'SiFive Feature Disable CSR', in user manual
>
> https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G
On Sat, Apr 3, 2021 at 6:53 AM Sean Anderson wrote:
>
> On 3/30/21 1:26 AM, Green Wan wrote:
> > Add a callback riscv_hart_early_init() to ./arch/riscv/cpu/start.S to
> > allow different riscv hart perform setup code for each hart as early
> > as possible. Since all the harts enter the callback, t
Hi Aswath,
On 4/6/21 5:26 PM, Aswath Govindraju wrote:
> Hi Jaehoon,
>
> On 06/04/21 10:50 am, Aswath Govindraju wrote:
>> Hi Jaehoon,
>>
>> On 06/04/21 3:48 am, Jaehoon Chung wrote:
>>> Hi,
>>>
>>> On 4/5/21 11:44 PM, Aswath Govindraju wrote:
From: Faiz Abbas
Enable HS400 speed m
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