Hi Tim,
On 28.04.21 17:11, Tim Harvey wrote:
On Mon, Apr 26, 2021 at 10:19 PM Stefan Roese wrote:
Hi Tim,
On 26.03.21 16:55, Tim Harvey wrote:
On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
On 26.03.21 01:07, Tim Harvey wrote:
The fdt node offset is apparently not set properly
Hi,
On Thu, Apr 29, 2021 at 6:53 AM Andre Przywara wrote:
>
> The H616 is our first supported Allwinner SoC which goes beyond the 4GB
> address space "barrier", by having more than 32 address bits.
Nit: I wouldn't say it's the first. The A80 supports up to 8GB address
space with LPAE. It just
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
This will presumably break the
The following changes since commit 79b0f08d6af498e6fda8cd257d62e2095764410c:
configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400)
are available in the Git repository at:
git://source.denx.de/u-boot-usb.git master
for you to fetch changes up to
On Tue, Apr 27, 2021 at 10:50 AM Tim Harvey wrote:
>
> On Mon, Apr 26, 2021, 5:35 PM Marek Vasut wrote:
> >
> > On 4/27/21 2:01 AM, Tim Harvey wrote:
> > [...]
> > >>> Why would the power domain get probed/enabled for the usbotg2
> > >>> bus but not the usbotg1 bus? Here is some debugging:
> >
From: Koji Matsuoka
Init GICv3 for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
board/renesas/falcon/falcon.c | 29 +
include/configs/falcon.h | 11 +++
2 files changed, 40
From: Hai Pham
Enable basic PSCI support for R8A779A0 V3U Falcon
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Makefile| 4 +++
arch/arm/mach-rmobile/psci-r8a779a0.c | 49 +++
configs/r8a779a0_falcon_defconfig | 1 +
3
From: Koji Matsuoka
Init the Generic Timer for V3U Falcon in early phase
Signed-off-by: Koji Matsuoka
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
board/renesas/falcon/falcon.c | 25 +
1 file changed, 25 insertions(+)
diff --git
From: Hai Pham
Add board code for the R8A779A0 V3U Falcon board.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
--
Marek: - various small rebase fixes and clean ups
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/r8a779a0-falcon-u-boot.dts | 32 +
Import R8A779A0 V3U DTs and headers from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0.dtsi| 970 ++
include/dt-bindings/clock/r8a779a0-cpg-mssr.h | 55 +
include/dt-bindings/power/r8a779a0-sysc.h |
From: Hai Pham
Add platform code to support R8A779A0 V3U SoC.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/mach-rmobile/Kconfig.64 | 5 +
arch/arm/mach-rmobile/cpu_info.c | 1 +
arch/arm/mach-rmobile/include/mach/rmobile.h | 1 +
3 files
The R-Car V3U does support RPC interface, however the support for it is
missing in upstream Linux DTs as of commit 9f4ad9e425a1 ("Linux 5.12"),
add the node into u-boot.dtsi to let U-Boot access the SPI NOR or HF.
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-u-boot.dtsi | 13
Import R8A779A0 V3U Falcon DTs from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-falcon-cpu.dtsi | 184 ++
arch/arm/dts/r8a779a0-falcon.dts | 28
2 files changed, 212 insertions(+)
create mode 100644
From: Hai Pham
Add R8A779A0 V3U DT extras for U-Boot.
Based on "ARM: dts: renesas: Add R8A779A0 V3U DTs"
by Hai Pham
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-u-boot.dtsi | 12
1 file changed, 12 insertions(+)
create mode 100644 arch/arm/dts/r8a779a0-u-boot.dtsi
The V3U SoC has several unlock registers, one per register group. They
reside at offset zero in each 0x200 bytes-sized block.
To avoid adding yet another table to the PFC implementation, this
patch adds the option to specify an address mask instead of the fixed
address in
The help text for Gen2 entries had a copy paste error, still containing
the Gen3 string, while the description was correctly listing Gen2. Fix
the help text.
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/Kconfig | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
From: Hai Pham
Add clock tables for R8A779A0 V3U SoC from Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12")
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
--
Marek: - Add .reset_modemr_offset
- Sync tables from Linux 5.12
- Rebase on latest u-boot
---
The help text in the Kconfig file was always a copy of the same thing.
Move single copy into the common PFC driver entry instead. Also fix a
copy-paste error in the PFC help text, which identified PFC as clock.
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/Kconfig | 74
The R8A779A0 V3U GPIO block has additional "General Input Enable" INEN
register. Add new R8A779A0 compatible string with a new quirk and also
a handler for this quirk which toggles the INEN register in the right
place. INEN register handling is based on "gpio: renesas: Add R8A779A0
V3U support" by
Most of the PLLx, MAIN, FIXED clock handlers are calling very similar
code, which determines parent rate and then applies multiplication and
division. The only difference is whether multiplication is fixed factor
or coming from CRx register. Deduplicate the code into a single function.
Pass struct udevice to rcar_gpio_set_direction() in preparation of
quirk handling in rcar_gpio_set_direction(). No functional change.
Signed-off-by: Marek Vasut
---
drivers/gpio/gpio-rcar.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git
On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.
Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham
From: Hai Pham
Base on Linux v5.10-rc2, commit 8b652aa8a1fb by Yoshihiro Shimoda
To support other register layouts in the future, add register pointers
of {control,status,reset,reset_clear}_regs into struct cpg_mssr_info
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
From: Hai Pham
CPG IP in some specific Renesas SoCs (i.e. new R8A779A0 V3U SoC)
requires a different setting procedure. Make struct cpg_mssr_info
accessible to handle the clock setting in that case.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen2.c
Synchronize R-Car Gen3 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 58 ++-
drivers/clk/renesas/r8a7796-cpg-mssr.c | 58 +++
drivers/clk/renesas/r8a77965-cpg-mssr.c | 58
The MODEMR register offset changed on R8A779A0, make the MODEMR offset
configurable. Fill the offset in on all clock drivers. No functional
change.
Based off "clk: renesas: Make CPG Reset MODEMR offset accessible from
struct cpg_mssr_info" by Hai Pham
Signed-off-by: Marek Vasut
---
From: Hai Pham
>From Linux v5.10-rc2, commit ffbf9cf3f946 by Yoshihiro Shimoda
Introduce enum clk_reg_layout to support multiple register layout variants
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/renesas-cpg-mssr.h | 6 ++
1 file changed, 6 insertions(+)
From: Hai Pham
RPC clk_get_rate will return error code instead of expected clock rate.
Fix this.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c
From: Hai Pham
This patch fixes Realtime Module Stop Control Register (RMSTPCR) offsets
based on R-Car Gen3, H2/M2/M2N/E2/E2X hardware user's manual.
The r8a73a4 only has RMSTPCR0 - RMSTPCR5 so this calculation change
doesn't affect it.
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
From: Hai Pham
This supports RPCD2 clock handling. While at it, add the check point
for RPC-IF clock RPCD2 Frequency Division Ratio, since it must be odd
number
Signed-off-by: Hai Pham
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/clk-rcar-gen3.c | 19 ++-
Reinstate RPC clock on D3/E3 after Linux 5.12 synchronization.
The D3 and E3 clock drivers do not contain RPC clock entries
mainline Linux yet.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 +
drivers/clk/renesas/r8a77995-cpg-mssr.c | 9 +
2 files
Synchronize RZ/G2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 14 +-
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 8
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 9 +
3 files
Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7790-cpg-mssr.c | 4 ++--
drivers/clk/renesas/r8a7791-cpg-mssr.c | 2 +-
drivers/clk/renesas/r8a7792-cpg-mssr.c | 2 +-
Hi Tero,
> Il 27/04/2021 09:01 Tero Kristo ha scritto:
>
>
> Hi Dario,
>
> One question below.
>
> On 25/04/2021 17:17, Dario Binacchi wrote:
> > As pointed by [1] and [2], commit
> > d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong:
> > - It makes every 'reg' DT property
> -Original Message-
> From: U-Boot On Behalf Of Peter Bergin
> Sent: Tuesday, April 6, 2021 8:59 AM
> To: u-boot@lists.denx.de
> Subject: Re: [PATCH 7/7] doc: imx8mp-evk: update after using binman
>
>
> Hi,
>
> On 2021-04-06 05:59, Peng Fan (OSS) wrote:
> > Burn the flash.bin to
Hi Michal,
On Thu, Apr 29, 2021 at 12:17 AM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/28/21 5:57 PM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Wed, Apr 28, 2021 at 11:03 PM Michal Simek
> > wrote:
> >>
> >> Hi Bin,
> >>
> >> On 4/28/21 4:37 PM, Bin Meng wrote:
> >>> Hi Michal,
> >>>
> >>> On
Hi Bin,
On 4/28/21 5:57 PM, Bin Meng wrote:
> Hi Michal,
>
> On Wed, Apr 28, 2021 at 11:03 PM Michal Simek wrote:
>>
>> Hi Bin,
>>
>> On 4/28/21 4:37 PM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
>>> wrote:
Hi Bin,
On 4/27/21 7:17
Hi Michal,
On Wed, Apr 28, 2021 at 11:03 PM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/28/21 4:37 PM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Tue, Apr 27, 2021 at 7:22 PM Michal Simek
> > wrote:
> >>
> >> Hi Bin,
> >>
> >> On 4/27/21 7:17 AM, Bin Meng wrote:
> >>> Hi Michal,
> >>>
> >>> On
79b0f08d6af498e6fda8cd257d62e2095764410c:
configs: Resync with savedefconfig (2021-04-27 08:28:38 -0400)
are available in the Git repository at:
https://source.denx.de/u-boot/custodians/u-boot-amlogic.git
tags/u-boot-amlogic-20210428
for you to fetch changes up
Hi!
Dne sreda, 28. april 2021 ob 12:05:55 CEST je Andre Przywara napisal(a):
> The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding,
> so we need to adjust the register value before doing the calculation.
>
> This fixes the MMC clock setup on those SoCs, which could be slightly
On 4/28/21 5:13 PM, Ying-Chun Liu (PaulLiu) wrote:
[...]
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
Marek Vasut 於 2021/4/28 上午12:06 寫道:
> For systems which use generic PHY support and implement USB PHY driver,
> the parsing of PHY properties is unnecessary, disable it.
>
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: Tim Harvey
> Cc: Ye Li
> Cc:
On Mon, Apr 26, 2021 at 10:19 PM Stefan Roese wrote:
>
> Hi Tim,
>
> On 26.03.21 16:55, Tim Harvey wrote:
> > On Thu, Mar 25, 2021 at 11:48 PM Stefan Roese wrote:
> >>
> >> On 26.03.21 01:07, Tim Harvey wrote:
> >>> The fdt node offset is apparently not set properly when probed
> >>> causing no
Hi Bin,
On 4/28/21 4:37 PM, Bin Meng wrote:
> Hi Michal,
>
> On Tue, Apr 27, 2021 at 7:22 PM Michal Simek wrote:
>>
>> Hi Bin,
>>
>> On 4/27/21 7:17 AM, Bin Meng wrote:
>>> Hi Michal,
>>>
>>> On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
>>> wrote:
The commit 6c993815bbea ("net: phy:
On 28.04.21 13:24, Dagan Martinez wrote:
From a45340719110b8a8b5292f6353fda7509be81417 Mon Sep 17 00:00:00 2001
From: Property404
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize the
Hi Michal,
On Tue, Apr 27, 2021 at 7:22 PM Michal Simek wrote:
>
> Hi Bin,
>
> On 4/27/21 7:17 AM, Bin Meng wrote:
> > Hi Michal,
> >
> > On Mon, Apr 26, 2021 at 8:31 PM Michal Simek
> > wrote:
> >>
> >> The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF
> >> tree") change
On 28.04.21 15:54, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
> the supplied buffer is too small, so a
From: Peng Fan
This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.
When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
the supplied buffer is too small, so a use-case is to call
EFI_FILE_PROTOCOL.Read() with
On 28.04.21 14:19, Masahisa Kojima wrote:
> This is preparation for PE/COFF measurement support.
> PE/COFF image hash calculation is same in both
> UEFI Secure Boot image verification and measurement in
> measured boot. PE/COFF image parsing functions are
> gathered into efi_image_loader.c, and
On 28.04.21 14:49, Heinrich Schuchardt wrote:
> On 28.04.21 10:15, Peng Fan (OSS) wrote:
>> From: Peng Fan
>>
>> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
>> but that fix was wrongly partial reverted.
>>
>> To Fedora shim loader, when buffer is NULL, a use-case is
On 28.04.21 10:15, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> To Fedora shim loader, when buffer is NULL, a use-case is to call
> efi_file_read with *buffer_size=0 and
On Wed, Apr 28, 2021 at 8:43 AM Peng Fan (OSS) wrote:
>
> From: Peng Fan
>
> This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
> but that fix was wrongly partial reverted.
>
> To Fedora shim loader, when buffer is NULL, a use-case is to call
> efi_file_read with
"TCG PC Client Platform Firmware Profile Specification"
requires to measure every attempt to load and execute
a OS Loader(a UEFI application) into PCR[4].
This commit adds the PE/COFF image measurement, extends PCR,
and appends measurement into Event Log.
Signed-off-by: Masahisa Kojima
---
(no
This patch series add the PE/COFF measurement support.
Extending PCR and Event Log is tested with fTPM
running as a OP-TEE TA.
Unit test will be added in the separate series.
Masahisa Kojima (2):
efi_loader: expose efi_image_parse() even if UEFI Secure Boot is
disabled
efi_loader: add
This is preparation for PE/COFF measurement support.
PE/COFF image hash calculation is same in both
UEFI Secure Boot image verification and measurement in
measured boot. PE/COFF image parsing functions are
gathered into efi_image_loader.c, and exposed even if
UEFI Secure Boot is not enabled.
This
>From a45340719110b8a8b5292f6353fda7509be81417 Mon Sep 17 00:00:00 2001
From: Property404
Date: Tue, 27 Apr 2021 15:48:31 -0400
Subject: [PATCH] Kirkwood: Fix tv sec/usec normalization in kwboot
`kwboot.c` had an issue where it failed to normalize the `tv` struct in
the case where the `tv_usec`
BITS_PER_LONG is used to represent register's size which is 32.
But when compiled on arch64, BITS_PER_LONG is then equal to 64.
Fix bank and offset computation to make it work on arch32 and
arch64 and ensure that register's size is always equal to 32.
Signed-off-by: Patrice Chotard
Today of_address_to_resource() is called only in
ofnode_read_resource() for livetree support and
fdt_get_resource() is called when livetree is not supported.
The fdt_get_resource() doesn't do the address translation
so when it is required, but the address translation is done
by
Hi,
It it the v3 serie of [1].
This v3 serie is rebased on top of v2021.07-rc1 with integrated previous series:
- [2] for stm32mp parts and added dram_bank_mmu_setup
- [3] for LMB impacts
On STM32MP15x platform we can use OP-TEE, loaded in DDR in a region
protected by a firewall. This region
No more map the reserved region with "no-map" property by marking
the corresponding TLB entries with invalid entry (=0) to avoid
speculative access.
The device tree parsing done in lmb_init_and_reserve() takes a
long time when it is executed without data cache, so it is called in
enable_caches()
Save the no-map information present in 'reserved-memory' node to allow
correct handling when the MMU is configured in board to avoid
speculative access.
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
common/image-fdt.c | 23 +++
1 file changed, 15 insertions(+),
Add lmb_dump_region() function, to simplify lmb_dump_all_force().
This patch is based on Linux memblock dump function.
An example of bdinfo output is:
.
fdt_size= 0x000146a0
FB base = 0xfdd0
lmb_dump_all:
memory.cnt = 0x1
memory[0] [0xc000-0x], 0x4000
Add a test to check the management of reserved region with flags.
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
test/lib/lmb.c | 89 ++
1 file changed, 89 insertions(+)
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index
Add "flags" in lmb_property to save the "no-map" property of
reserved region and a new function lmb_reserve_flags() to check
this flag.
The default allocation use flags = LMB_NONE.
The adjacent reserved memory region are merged only when they have
the same flags value.
This patch is partially
Add 8M for the U-Boot reserved memory (display, fdt, gd, ...).
Without this patch the device tree, located before the MALLOC area
is not tagged cacheable just after relocation, before mmu reconfiguration.
This patch reduces the duration for device tree parsing in
lmb_init_and_reserve.
Add a new function lmb_is_reserved_flags to check is a
address is reserved with a specific flags.
This function can be used to check if an address was
reserved with no-map flags with:
lmb_is_reserved_flags(lmb, addr, LMB_NOMAP);
Signed-off-by: Patrick Delaunay
---
(no changes since v1)
The "n" factor of the PLL_PERIPH0 clock is using the usual +1 encoding,
so we need to adjust the register value before doing the calculation.
This fixes the MMC clock setup on those SoCs, which could be slightly off
due to the wrong parent frequency:
mmc 2 set mod-clk req 5200 parent
From: Peng Fan
This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.
To Fedora shim loader, when buffer is NULL, a use-case is to call
efi_file_read with *buffer_size=0 and buffer=NULL to obtain the needed
size before doing the
On 4/27/2021 7:14 PM, Jagan Teki wrote:
> On Tue, Apr 27, 2021 at 7:54 AM wrote:
>>
>> From: Takahiro Kuwano
>>
>> The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.
>>
>> The summary datasheets can be found in the following links.
>>
2021年4月28日(水) 14:44 AKASHI Takahiro :
>
> On Thu, Apr 08, 2021 at 09:58:17PM +0200, Heinrich Schuchardt wrote:
> > On 4/7/21 1:53 PM, Sughosh Ganu wrote:
> > > Add provision for embedding the public key used for capsule
> > > authentication in the platform's dtb. This is done by invoking the
> > >
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