Hi folks:
I'm working on AST 2600 uboot image and need some direction.
More specifically, I was trying to load SPI flash image for AST 2600 on
qemu and running into an error wherein qemu just hangs while emulating 2600
evb.
Here are the cmds I'm running
Steps to compile AST 2600 u-boot image
1.
I agree, the most generic way to fix this problem would be to ensure memory
alignment inside the general RPMB driver.
the drivers/tee/optee/rpmb.c driver uses `mmc_rpmb_route_frames`, which is a
parallel API used to drive RPMB frames directly into the MMC driver.
I thought that the MMC driver
On Tue, Jun 08, 2021 at 01:34:33PM +0530, Aswath Govindraju wrote:
> + Tom Rini
>
> I saw that this patch is delegated to Tom Rini in patchwork page but I
> did not add him in the cc-list. So, I added him now.
>
> Hi Tom,
>
> On 01/06/21 4:51 pm, Aswath Govindraju wrote:
> > Currently the
From: Timothée Cercueil
OP-TEE OS inserts a 6-byte header before a raw RPMB frame which makes
RPMB data buffer not 32bit aligned. Many RPMB drivers implicitly expect
32bit alignment of the eMMC frame including arm_pl180_mmci.c, sandbox_mmc.c
and stm32_sdmmc2.c
To prevent breaking ABI with
Address and size cells on SOC are set to 1. But gpio nodes are specified
with 2 cells. This fixes the gpio nodes to correct cells.
Signed-off-by: Lasse Klok Mikkelsen
---
arch/arm/dts/ls1021a.dtsi | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
+ Tom Rini
I saw that this patch is delegated to Tom Rini in patchwork page but I
did not add him in the cc-list. So, I added him now.
Hi Tom,
On 01/06/21 4:51 pm, Aswath Govindraju wrote:
> Currently the config options CONFIG_SYS_DFU_DATA_BUF_SIZE and
> CONFIG_SYS_DFU_MAX_FILE_SIZE are being
Hi Fabio,
On 6/9/21 6:47 AM, Fabio Estevam wrote:
> Hi Jaehoon,
>
> On Mon, Jun 7, 2021 at 11:50 PM Jaehoon Chung wrote:
>
>> Is your target success to boot finally after 20sec?
>
> Yes, it boots fine after 20s.
>
>> I didn't have target to use fsl_esdhc_imx driver.
>>
>> If booted after
On 28/05/2021 00.00, Rasmus Villemoes wrote:
> This series is an attempt at expanding the wdt-uclass provided
> watchdog_reset() to handle all DM watchdogs, not just the first
> one. As a sort of nice side effect, it turns out that doing that makes
> wdt-uclass fit better into the uclass model, in
Brackets '[' need to be escaped to avoid a build warning
lib/efi_loader/efi_image_loader.c:223:
WARNING: Inline strong start-string without end-string.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/efi_image_loader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
On 6/4/21 6:51 PM, Patrick Delaunay wrote:
Provide a man-page for the ums command - USB Mass Storage.
Signed-off-by: Patrick Delaunay
---
Changes in v2:
- clarify description
- add reference to and align parameter name
- correct information for partition = 0 (expose all partitions)
- update
On 6/4/21 6:51 PM, Patrick Delaunay wrote:
Add the missing dependency for the command ums:
- CONFIG_BLK: call of blk_* functions in usb_mass_storage.c
- CONFIG_USB_GADGET: required to select CONFIG_USB_FUNCTION_MASS_STORAGE
Signed-off-by: Patrick Delaunay
Reviewed-by: Heinrich Schuchardt
On Mon, Jun 07, 2021 at 10:26:32PM +0200, Marek Vasut wrote:
> I found this one left over in the queue ...
>
> The following changes since commit e3b64beda5dd1a6b6bedfd1fe0e50be1ddea7044:
>
> Prepare v2021.07-rc4 (2021-06-07 09:26:39 -0400)
>
> are available in the Git repository at:
>
>
Hi Jaehoon,
On Mon, Jun 7, 2021 at 11:50 PM Jaehoon Chung wrote:
> Is your target success to boot finally after 20sec?
Yes, it boots fine after 20s.
> I didn't have target to use fsl_esdhc_imx driver.
>
> If booted after 20sec, how about below code?
>
> #ifdef CONFIG_FSL_ESDHC_IMX_TIMEOUT
>
On Sat, May 08, 2021 at 01:46:52PM -0600, Simon Glass wrote:
> At present when logging is not enabled, all log() calls become nops. This
> does not seem right, since if the log level is high enough then there
> should be some sort of message. So in that case, this series updates it to
> print the
On Sat, May 08, 2021 at 06:59:55AM -0600, Simon Glass wrote:
> At present we have two ways of showing a hex dump. Once has been in U-Boot
> since the dawn of time and the other was recently added from Linux.
>
> They both have their own unique features.
>
> This series makes a few changes to
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main
From: Chris Morgan
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
From: Chris Morgan
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan
---
From: Chris Morgan
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/dts/px30.dtsi | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index
From: Chris Morgan
Changes from v2:
- Resending due to glitch with patch file truncating final two lines
on patch 1/5 and incorrect patch version number on patch 5/5.
Changes from v1:
- Reworked code to utilize spi-mem framework, and based it closely
off of work in progress code for
From: Chris Morgan
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/px30/px30.c | 64 ++
1 file changed, 64 insertions(+)
diff --git
From: Chris Morgan
The Odroid Go Advance uses a Rockchip Serial Flash Controller with an
XT25F128B SPI NOR flash chip. This adds support for both. Note that
while both the controller and chip support quad mode, only two lines
are connected to the chip. Changing the pinctrl to bus2 and setting tx
From: Chris Morgan
Adds support for XT25F128B used on Odroid Go Advance. Unfortunately
this chip uses a continuation code which I cannot seem to parse, so
there are possibly going to be collisions with chips that use the same
manufacturer/ID.
Signed-off-by: Chris Morgan
---
From: Chris Morgan
Add the serial flash controller to the devicetree for the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/dts/px30.dtsi | 38 ++
1 file changed, 38 insertions(+)
diff --git a/arch/arm/dts/px30.dtsi b/arch/arm/dts/px30.dtsi
index
From: Chris Morgan
This patch adds support for setting the correct pin configuration
for the Rockchip Serial Flash Controller found on the PX30.
Signed-off-by: Chris Morgan
---
arch/arm/mach-rockchip/px30/px30.c | 64 ++
1 file changed, 64 insertions(+)
diff --git
From: Chris Morgan
This patch adds support for the Rockchip serial flash controller
found on the PX30 SoC. It should work for versions 3-5 of the SFC
IP, however I am only able to test it on v3.
This is adapted from the WIP SPI-MEM driver for the SFC on mainline
Linux. Note that the main
From: Chris Morgan
Changes from v1:
- Reworked code to utilize spi-mem framework, and based it closely
off of work in progress code for mainline Linux.
- Removed DMA, as it didn't offer much performance benefit for
booting (in my test cases), added complexity to the code, and
A system clock of 66MHz was chosen for the pg-wcom-ls102xa.
Compared to the Evalboard, this corresponds to a reduction of 1/3.
The system counter clock should have been reduced accordingly,
but that was not the case, so we had a system time that was
1/3 behind the real time.
This patch corrects
This patch adds the front led initialization and the application
buffer enable to the eraly board inititlaization.
Signed-off-by: Rainer Boschung
Signed-off-by: Aleksandar Gerasimovski
---
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
In order to improve power consumption ls102x allows to disable peripherals
that are not in use.
This patch follows SELI8 HW design description and disables peripherals
that are not in use in our designs, the same configuration is applicable
and for EXPU1.
This patch uses available hwconfig option
The default behavior in the latest u-boot revisions is to rotate the
active net device to the next available if the requested link is not
established.
For our ls102x based devices this would mean that if active debug net
device is not available, u-boot will rotate and set the next net device
that
This is most probably a typo, and in older u-uboot versions is same as
'saveenv', in the newer uboot versions there is a separate 'save' command
that is different from 'saveenv'.
Signed-off-by: Aleksandar Gerasimovski
---
board/keymile/scripts/ramfs-common.txt | 2 +-
1 file changed, 1
In our designs we reserve PRAM area at the end of the RAM, and in order
this area to be visible and taken into account by the u-boot memory mgmt
CONFIG_PRAM has to be defined.
Signed-off-by: Aleksandar Gerasimovski
---
include/configs/km/pg-wcom-ls102xa.h | 4
1 file changed, 4
>From production view this is standard test executed during production on
all linux based foxmc cards.
On CENT2 HW defined memory region is zero means that some DDR accesses are
done by memory_post_dataline and memory_post_addrline but pattern tests
are skipped that's why mem_regions is fast
The EXPU1 design is a new 40G capable ethernet service unit card for
Hitachi-Powergrids wired-com product lines.
The base SoC is same as for already added SELI8 card, consequently the
already added u-boot support for SELI8 is reused.
Signed-off-by: Rainer Boschung
Signed-off-by: Aleksandar
Hi,
This is in 90 minutes. If you plan to join tomorrow and want to add a
topic, please do so at [1].
Regards,
Simon
[1] https://bit.ly/3bFvwA1
or
https://docs.google.com/document/d/1YBOMsbM19uSFyoJWnt7-PsOLBaevzQUgV-hiR88a5-o/edit#heading=h.flytinyefvov
On 08/06/21, Jorge Ramirez-Ortiz, Foundries wrote:
> On 08/06/21, Michal Simek wrote:
> > Hi,
> >
> > On 6/7/21 8:41 PM, Jorge Ramirez-Ortiz, Foundries wrote:
> > > On 07/06/21, Jorge Ramirez-Ortiz, Foundries wrote:
> > >> hi Michal
> > >>
> > >> um, when we exchanged emails about enabling ECC
On 08/06/21, Michal Simek wrote:
> Hi,
>
> On 6/7/21 8:41 PM, Jorge Ramirez-Ortiz, Foundries wrote:
> > On 07/06/21, Jorge Ramirez-Ortiz, Foundries wrote:
> >> hi Michal
> >>
> >> um, when we exchanged emails about enabling ECC support for MPSoC, I
> >> left with the understanding that there
On 08.06.21 12:07, Timothée Cercueil wrote:
> From: Timothée Cercueil
>
> OP-TEE OS inserts a 6-byte header before a raw RPMB frame which makes
> RPMB data buffer not 32bit aligned. Many RPMB drivers implicitly expect
> 32bit alignment of the eMMC frame including arm_pl180_mmci.c, sandbox_mmc.c
>
On Tue, Jun 08, 2021 at 07:36:31AM +, Priyanka Jain wrote:
>
>
> >-Original Message-
> >From: Tom Rini
> >Sent: Friday, May 21, 2021 11:09 PM
> >To: Camelia Alexandra Groza (OSS)
> >Cc: u-boot@lists.denx.de; Priyanka Jain
> >Subject: Re: [PATCH 25/27] ppc: Remove T4160RDB board
>
On 6/8/21 12:37 PM, Adrian Fiergolski wrote:
> The default register configuration after powerup for PSSYSMON_ANALOG_BUS
> register is incorrect. Hence, fix this in SPL by writing correct fixed
> value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
> sw_apps:zynq
Hi,
On 6/7/21 8:41 PM, Jorge Ramirez-Ortiz, Foundries wrote:
> On 07/06/21, Jorge Ramirez-Ortiz, Foundries wrote:
>> hi Michal
>>
>> um, when we exchanged emails about enabling ECC support for MPSoC, I
>> left with the understanding that there already was a DMA driver
>> available in u-boot that
The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in
Hi,
On 14/05/21 10:48AM, Kishon Vijay Abraham I wrote:
> Hi Simon,
>
> On 14/05/21 5:26 am, Simon Glass wrote:
> > Hi Kishon,
> >
> > On Thu, 13 May 2021 at 00:15, Kishon Vijay Abraham I wrote:
> >>
> >> Hi Simon,
> >>
> >> On 11/05/21 10:09 pm, Simon Glass wrote:
> >>> Hi Kishon,
> >>>
> >>>
0x0400- 0x0600 is reserved memory. We cannot load to anything here.
Signed-off-by: Heinrich Schuchardt
---
include/configs/mvebu_armada-8k.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/configs/mvebu_armada-8k.h
On Monday 07 June 2021 16:34:51 Marek Behún wrote:
> Enable configuration options to support Turris network boot. This
> includes FIT support and some crypto commands.
>
> Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
> ---
> configs/turris_mox_defconfig | 8
> 1 file changed,
On Monday 07 June 2021 16:34:50 Marek Behún wrote:
> Add nodes for SPI NOR partitions to the device tree of Turris MOX, as
> are in Linux' device tree.
This patch is not needed (for now) as U-Boot cannot parse SPI NOR
partitions from DT yet. U-Boot for SPI NOR currently supports specifying
On Monday 07 June 2021 16:34:49 Marek Behún wrote:
> Add default fdtfile environment variable with value
> marvell/armada-3720-turris-mox.dtb.
>
> This can be useful for some boot scenarios.
>
> Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
> ---
> include/configs/turris_mox.h | 1 +
>
On Monday 07 June 2021 16:34:48 Marek Behún wrote:
> Configure blinking on ethernet PHY LEDs on the MOX A board when entering
> rescue mode via reset button.
>
> Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
> ---
> board/CZ.NIC/turris_mox/turris_mox.c | 35
On Monday 07 June 2021 16:34:47 Marek Behún wrote:
> Add necessary config options and board code to support board factory
> reset / rescue mode on Turris MOX.
>
> In order to also support invoking rescue mode from U-Boot console,
> without having to press the factory reset button, put the rescue
On Monday 07 June 2021 16:34:46 Marek Behún wrote:
> Add nodes for indicator LED and reset button so that board code can
> implement board factory reset mechanism.
>
> Signed-off-by: Marek Behún
Reviewed-by: Pali Rohár
> ---
> arch/arm/dts/armada-3720-turris-mox.dts | 24
On Mon, 7 Jun 2021 14:05:10 +0200
Frieder Schrempf wrote:
> From: Frieder Schrempf
>
> Add the clocks for the ECSPI controllers. This is ported from
> Linux v5.13-rc4.
>
> Signed-off-by: Frieder Schrempf
> ---
> drivers/clk/imx/clk-imx8mm.c | 23 ++-
> 1 file changed,
On Fri, Jun 4, 2021 at 1:51 PM Bin Meng wrote:
>
> The SPDX license header is currently missing. Add one.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/riscv/dts/ae350_32.dts | 2 ++
> arch/riscv/dts/ae350_64.dts | 2 ++
> 2 files changed, 4 insertions(+)
>
Ping for this series?
Add "Priyanka Jain " as
MAINTAINER for t102xrdb board.
Signed-off-by: Priyanka Jain
---
board/freescale/t102xrdb/MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t102xrdb/MAINTAINERS
b/board/freescale/t102xrdb/MAINTAINERS
index
Add "Priyanka Jain " as
MAINTAINER for p2041rdb board.
Signed-off-by: Priyanka Jain
---
board/freescale/p2041rdb/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/p2041rdb/MAINTAINERS
b/board/freescale/p2041rdb/MAINTAINERS
index
Add "Priyanka Jain " as
MAINTAINER for p1_p2_rdb_pc board.
Signed-off-by: Priyanka Jain
---
board/freescale/p1_p2_rdb_pc/MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS
b/board/freescale/p1_p2_rdb_pc/MAINTAINERS
index
Add "Priyanka Jain " as
MAINTAINER for t4rdb board.
Signed-off-by: Priyanka Jain
---
board/freescale/t4rdb/MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/freescale/t4rdb/MAINTAINERS
b/board/freescale/t4rdb/MAINTAINERS
index 4ba5c3a546..7380408aae
Hi Marek,
On 2021/06/08 2:33, Marek Vasut wrote:
On 6/7/21 9:54 AM, Kunihiko Hayashi wrote:
Hi,
[...]
I would expect that after relocation, if all you have is env_nowhere
driver, the env_nowhere_init() is called again from the first for() loop
of env_init() [1], which would set
>-Original Message-
>From: Tom Rini
>Sent: Friday, May 21, 2021 11:09 PM
>To: Camelia Alexandra Groza (OSS)
>Cc: u-boot@lists.denx.de; Priyanka Jain
>Subject: Re: [PATCH 25/27] ppc: Remove T4160RDB board
>
>On Fri, May 21, 2021 at 04:10:12PM +, Camelia Alexandra Groza (OSS)
On 6/8/21 12:35 PM, Lokesh Vutla wrote:
>
>
> On 07/06/21 7:47 pm, Vignesh Raghavendra wrote:
>> This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM
>> Rearch.
>>
>> Depends on Tero's base HSM rearch support series.
>>
>> v2:
>> Use IS_ENABLED() consistentially instead of
The only difference between the 1G and 4G models is the required bootloader.
4G R4S version: LPDDR4 4GiB
1G R4S version: DDR3-1866 1GB
Kever Yang 于2021年6月8日周二 下午2:51写道：
> Hi xiaobo,
>
> There is already a nonopi-r4s board, why we need a 1GB? This should
> be already support.
>
>
On 6/7/21 7:53 PM, Adrian Fiergolski wrote:
> The default register configuration after powerup for PSSYSMON_ANALOG_BUS
> register is incorrect. Hence, fix this in SPL by writing correct fixed
> value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
> sw_apps:zynq
On 2021/5/26 下午4:46, Elaine Zhang wrote:
From: Elaine Zhang
Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../include/asm/arch-rockchip/cru_rk3568.h| 504 +++
drivers/clk/rockchip/Makefile
On 2021/6/2 上午11:39, Elaine Zhang wrote:
Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
Thanks,
- Kever
---
.../include/asm/arch-rockchip/cru_rk3568.h| 504 +++
drivers/clk/rockchip/Makefile |1 +
On 2021/5/26 下午4:46, Elaine Zhang wrote:
From: Elaine Zhang
Add dts binding header for rk3568, files origin from kernel.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
Thanks,
- Kever
---
include/dt-bindings/clock/rk3568-cru.h | 925 +
1 file changed,
On 2021/6/4 下午12:56, Anand Moon wrote:
Replace msleep occurences by udelay.
drivers/pci/pcie_dw_rockchip.c:254:3: warning: implicit
declaration of function 'msleep' [-Wimplicit-function-declaration]
Cc: Patrick Wildt
Cc: Neil Armstrong
Cc: Kever Yang
Signed-off-by: Anand Moon
On 07/06/21 7:47 pm, Vignesh Raghavendra wrote:
> This series add DMA support for R5 SPL on J721e/J7200 SoCs post HSM
> Rearch.
>
> Depends on Tero's base HSM rearch support series.
>
> v2:
> Use IS_ENABLED() consistentially instead of #ifdef
> Reword commit msg for 5/7 as suggested by Lokesh
On 2021/6/4 下午12:56, Anand Moon wrote:
Drop the unused variable warning below.
drivers/pci/pcie_dw_rockchip.c:161:6: warning: unused variable
'val' [-Wunused-variable]
161 | u32 val;
| ^~~
Cc: Patrick Wildt
Cc: Neil Armstrong
Cc: Kever Yang
Reviewed-by: Neil Armstrong
On 2021/6/4 下午12:56, Anand Moon wrote:
Use the generic error number instead of specific error number.
Changes fix the below error.
drivers/pci/pcie_dw_rockchip.c: In function 'rk_pcie_read':
drivers/pci/pcie_dw_rockchip.c:70:10: error: 'PCIBIOS_UNSUPPORTED'
undeclared
On 2021/6/7 上午11:45, Artem Lapkin wrote:
Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard)
Add missed USB OHCI configuration
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Human
On 2021/6/7 上午11:45, Artem Lapkin wrote:
Problem: USB2.0 port can recognize any USB1.1 devices (like usb keyboard)
Add missed USB OHCI configuration
USB device tree:
1 Hub (480 Mb/s, 0mA)
u-boot EHCI Host Controller
1 Hub (12 Mb/s, 0mA)
| U-Boot Root Hub
|
+-2 Human
Hi xiaobo,
There is already a nonopi-r4s board, why we need a 1GB? This should
be already support.
Thanks,
- Kever
On 2021/6/8 上午9:28, xiaobo wrote:
NanoPi R4s is SBC base on Rockchip RK3399 hexa-core processor with
dual-Core Cortex-A72 and Mali-T864 GPU with 1GiB(DDR3-1866) of RAM
On 08/06/2021 09:32, Lokesh Vutla wrote:
On 08/06/21 11:57 am, Tero Kristo wrote:
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
On 08/06/21 11:57 am, Tero Kristo wrote:
> On 07/06/2021 14:22, Lokesh Vutla wrote:
>>
>>
>> On 03/06/21 12:02 pm, Tero Kristo wrote:
>>> Hi,
>>>
>>> As requested, this is just a rebase to the latest u-boot tip.
>>>
>>> Boot tested on j721e to make sure nothing got broken.
>>
>> There are some
On 07/06/2021 14:22, Lokesh Vutla wrote:
On 03/06/21 12:02 pm, Tero Kristo wrote:
Hi,
As requested, this is just a rebase to the latest u-boot tip.
Boot tested on j721e to make sure nothing got broken.
There are some build errors. Can you take a look?
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