Add support for xilinx multirate(MRMAC) ethernet driver.
This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC.
Added support for 4 ports of MRMAC for speeds 10G and 25G.
MCDMA supports upto 16 channels but in this driver we have setup only
one channel which is enough.
Tested 10G an
This patch set adds Xilinx AXI Multirate MAC(MRMAC) driver support.
This MRMAC is a high performance, low latency, adaptable Ethernet integrated
hard IP. This can be configured up to four ports with MAC rates from 10GE to
100GE.
Supported Configuration Combinations:
1 × 100GE
2 × 50GE
1 × 40GE
4
Enable Xilinx AXI MRMAC for Versal platforms.
Signed-off-by: Ashok Reddy Soma
---
configs/xilinx_versal_virt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/xilinx_versal_virt_defconfig
b/configs/xilinx_versal_virt_defconfig
index f4e9a80728..75feae318e 100644
--- a/confi
Add speed macro's for higher ethernet speeds to be used in u-boot
networking drivers. Added Macros for speeds 14G, 20G, 25G, 40G, 50G,
56G, 100G and 200G inline with linux.
Signed-off-by: Ashok Reddy Soma
---
include/linux/ethtool.h | 8
1 file changed, 8 insertions(+)
diff --git a/in
Add support for 10G/25G (XXV) high speed ethernet. This Makes use of
the exiting AXI DMA, similar to 1G.
Signed-off-by: Alessandro Temil
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 162 +-
1 file changed, 118 insertions(+), 44 deletions(-
There are lot of accesses to priv data in of_to_plat(), which is incorrect.
Create a platform data structure and use it in of_to_plat(), then copy all
platform data to priv data in probe.
Signed-off-by: Ashok Reddy Soma
---
drivers/net/xilinx_axi_emac.c | 47 ---
- Cleanup of_to_plat() to access platform data only in it
- Copy plat data to priv data in probe function
- Add support for 10G/25G to the AXI emac driver
- Keep all phy related activity in the driver for 1G only
Ashok Reddy Soma (2):
net: xilinx: axi_emac: Cleanup of of_to_plat()
net: xi
On Mon, Jun 7, 2021 at 1:47 PM Jaime Liao wrote:
>
> Macronix NAND Flash devices are available in different configurations
> and densities.
>
> MX"35" means SPI NAND
> MX35"UF" , UF meands 1.8V
> MX35LF"2G" , 2G means 2Gbits
> MX35LF2G"E4" , E4 means internal ECC and Quad I/O(x4)
>
> MX35UF4GE4AD/
> Hi Kwon,
>
> On Wed, Jun 23, 2021 at 10:13 PM Kwon Tae-young wrote:
> >
> > At the current clock setting, the maximum clock for QSPI is 25 MHz.
> > In my case I use M-RAM which supports up to 100 MHz for QSPI, and with
> > this change the QSPI can be clocked up to 66 MHz.
> >
> > Signed-off-by:
At the current clock setting, the maximum clock for QSPI is 25 MHz.
In my case I use M-RAM which supports up to 100 MHz for QSPI, and with
this change the QSPI can be clocked up to 66 MHz.
Signed-off-by: Kwon Tae-young
---
arch/arm/mach-imx/imx8m/clock_imx8mq.c | 4 ++--
1 file changed, 2 insert
On Wed, Jun 23, 2021 at 11:18 PM 권태영 wrote:
> The clocks I tested are as follows.
> CLK_ROOT_SOURCE_SEL(0): 6.25 Mhz
> CLK_ROOT_SOURCE_SEL(1): 100 Mhz
> CLK_ROOT_SOURCE_SEL(2): 100 Mhz
> CLK_ROOT_SOURCE_SEL(3): 125 Mhz
> CLK_ROOT_SOURCE_SEL(4): 90.36 Mhz
> CLK_ROOT_SOURCE_SEL(5): 66.69 Mhz
> CLK_
On Wed, Jun 23, 2021 at 05:28:42PM -0700, Tim Harvey wrote:
> On Wed, Jun 23, 2021 at 3:37 AM Vladimir Oltean
> wrote:
> >
> > On Tue, Jun 22, 2021 at 09:38:52AM -0700, Tim Harvey wrote:
> > > On Mon, Jun 21, 2021 at 4:49 PM Vladimir Oltean wrote:
> > > >
> > > > On Mon, Jun 21, 2021 at 04:10:51
Hi Kwon,
On Wed, Jun 23, 2021 at 10:13 PM Kwon Tae-young wrote:
>
> At the current clock setting, the maximum clock for QSPI is 25 MHz.
> In my case I use M-RAM which supports up to 100 MHz for QSPI, and with
> this change the QSPI can be clocked up to 66 MHz.
>
> Signed-off-by: Kwon Tae-young
>
From: weichangzheng
This adds platform code and the device tree for the Phytium Pomelo Board.
The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng
---
arch/arm/Kconfig | 8 ++
arch/arm/dts/Makefile| 1 +
arch/arm/dts/phytium-pomelo
On Wed, Jun 23, 2021 at 3:37 AM Vladimir Oltean wrote:
>
> On Tue, Jun 22, 2021 at 09:38:52AM -0700, Tim Harvey wrote:
> > On Mon, Jun 21, 2021 at 4:49 PM Vladimir Oltean wrote:
> > >
> > > On Mon, Jun 21, 2021 at 04:10:51PM -0700, Tim Harvey wrote:
> > > > Greetings,
> > > >
> > > > I've written
Enable AVS, PMIC and dependent configs.
Signed-off-by: Gowtham Tammana
---
configs/j7200_evm_r5_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 08fad3e04b..7593b32dfc 100644
--- a/configs/j7200_evm_r5_defco
Add voltage and thermal management (VTM) node. The efuse values for the
OPPs are stored under the VTM, and is needed for AVS class 0 support.
Signed-off-by: Gowtham Tammana
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/
Hook buck1_reg to vtm avs supply.
Signed-off-by: Gowtham Tammana
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 23a2a5060c..45200b18
Add pmic lp876411 node needed for CPU AVS support.
Signed-off-by: Gowtham Tammana
---
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-boar
The J7200 EVM has PMIC LP876441 for supporting CPU AVS. This patchset
adds dt nodes, compatible string, and configs to enable the
corresponding driver.
v2:
- rebased the changes are reordered patches 3/4
v1:
- https://lore.kernel.org/u-boot/20200915113633.25449-1-g-tamm...@ti.com/
Gowtham Tamm
TI J7200 EVM has lp876441 pmic that is similar to tps65941. Add support
for same with existing driver with new compatible.
Signed-off-by: Gowtham Tammana
---
drivers/power/pmic/tps65941.c | 1 +
include/power/tps65941.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/power/pmi
gpio_request_by_name should be called with proper flags.
The 0 value flag is invalid, and causes bad initialization of the gpio.
Signed-off-by: Eugen Hristev
---
drivers/w1/w1-gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c
i
The GPIO polarity for onewire must be GPIO_ACTIVE_HIGH.
On previous versions this used to work as it looks like the right flag values
are being passed since :
https://lists.denx.de/pipermail/u-boot/2020-April/407195.html
And that series broke the old functionality for onewire nodes.
Some boards ha
On Wed, 2021-06-16 at 14:19 +0200, Wasim Khan wrote:
> From: Wasim Khan
>
> NXP platforms expect bootcmd and mcinitcmd to be updated
> as per boot source.
>
> commit cbf77d201870f2d12227e2d95718a416b16ec98b breaks this
> behaviour.
> Revert commit cbf77d201870f2d12227e2d95718a416b16ec98b
As I a
On Wed, May 5, 2021 at 3:11 PM Pratyush Yadav wrote:
>
> Hi,
>
> This series adds support for octal DTR flashes in the SPI NOR framework,
> and then adds hooks for the Cypress S28HS512T and Micron MT35XU512ABA
> flashes.
>
> The Cadence QSPI controller driver is also updated to run in Octal DTR
>
Now that u-boot gained DSA support, and it is already enabled for the
kontron_sl28 board, add the last missing piece and enable the
corresponding devices it in the device tree.
Signed-off-by: Michael Walle
---
changes since v1:
- renamed ethernet alias stem, because it was changed in
commit 8
Hi Kunihiko,
On 6/23/21 12:52 PM, Kunihiko Hayashi wrote:
> Hi Michal,
>
> On 2021/06/22 21:44, Michal Simek wrote:
>> Hi,
>>
>> On 6/22/21 6:24 AM, Kunihiko Hayashi wrote:
>>> This adds serial parameters that include stop bit mode, parity mode,
>>> and character length. Mark parity and space par
Hi Tom,
This PR includes the following changes for v2021.07 release:
- x86: Discard .note.gnu.property sections
- nvme: Skip block device creation for inactive namespaces
- nvme: Convert NVMe doc to reST, and various minor fixes
Azure results: PASS
https://dev.azure.com/bmeng/GitHub/_build/resul
Hi Michal,
On 2021/06/22 21:44, Michal Simek wrote:
Hi,
On 6/22/21 6:24 AM, Kunihiko Hayashi wrote:
This adds serial parameters that include stop bit mode, parity mode,
and character length. Mark parity and space parity modes are not
supported.
Signed-off-by: Kunihiko Hayashi
---
drivers/s
On Tue, Jun 22, 2021 at 09:38:52AM -0700, Tim Harvey wrote:
> On Mon, Jun 21, 2021 at 4:49 PM Vladimir Oltean wrote:
> >
> > On Mon, Jun 21, 2021 at 04:10:51PM -0700, Tim Harvey wrote:
> > > Greetings,
> > >
> > > I've written a U-Boot phy driver for a Microchip KSZ9477 ethernet
> > > switch that
Hi,
Adding Andre, Lukasz and Marek in Cc
On Mon, Jan 25, 2021 at 09:43:59PM +0800, peng.fan at nxp.com wrote:
> From: Li Jun
>
> Change to use wMaxPacketSize of current speed EP desc for request
> length wrap up.
>
> Reviewed-by: Peter Chen
> Signed-off-by: Li Jun
> Signed-off-by: Peng Fan
Dear Roland,
In message you wrote:
>
> > ...
> >> + /* hexadecimal to decimal conversion: "setexpr name dec value" */
> >> + if (argc == 4 && (strcmp(argv[2], "dec") == 0)) {
> >> + w = cmd_get_data_size(argv[3], 4);
> >> + a = get_arg(argv[3], w);
> >> +
On Tue, Jun 22, 2021 at 9:16 PM Bin Meng wrote:
>
> At present the block device creation happens in the NVMe uclass
> driver post_probe() phase. In preparation to support multiple
> namespaces, we should issue namespace identify before creating
> block devices but that touches the underlying hardw
On Wed, Jun 23, 2021 at 5:14 PM Bin Meng wrote:
>
> On Tue, Jun 22, 2021 at 11:35 AM Wesley Sheng wrote:
> >
> > From: Wesley Sheng
> >
> > AQA (Admin Queue Attributes) register is a dword size with
> > lower word of ASQS, and higher word of ACQS.
> >
> > The code set the variable aqa twice, but
On Wed, Jun 23, 2021 at 4:53 PM Bin Meng wrote:
>
> On Tue, Jun 22, 2021 at 11:34 AM Wesley Sheng wrote:
> >
> > From: Wesley Sheng
> >
> > Each prp is 8 bytes, calculate the number of prps
> > per page should just divide page size by 8
> > there is no need to minus 1
> >
> > Signed-off-by: Wesl
Add a driver for Macronix SPI controller IP.
This patch referred from linux spi-mxic.c. The difference from the
linux version is described here.
1. To adapt uboot spi framework, modify some functions naming.
2. Remove the incompatible functions of Uboot.
3. Add dummy byte recalculattion functio
On Tue, Jun 22, 2021 at 11:35 AM Wesley Sheng wrote:
>
> From: Wesley Sheng
>
> AQA (Admin Queue Attributes) register is a dword size with
> lower word of ASQS, and higher word of ACQS.
>
> The code set the variable aqa twice, but it is redundant.
>
> Signed-off-by: Wesley Sheng
> ---
> drivers
Dear Wolfgang,
On Wed, 23. Jun 2021 08:03, Wolfgang Denk wrote:
>
> Dear Roland,
>
> In message <20210622135042.133904-2-roland.gaudig-...@weidmueller.com> you
> wrote:
>>
>> This patch extends the setexpr command with a dec operator to
>> convert an input value to decimal.
> ...
>> + /* h
On Tue, Jun 22, 2021 at 11:34 AM Wesley Sheng wrote:
>
> From: Wesley Sheng
>
> Each prp is 8 bytes, calculate the number of prps
> per page should just divide page size by 8
> there is no need to minus 1
>
> Signed-off-by: Wesley Sheng
> ---
> drivers/nvme/nvme.c | 2 +-
> 1 file changed, 1 in
Hi Simon,
On Tue, 22. Jun 2021 at 21:25, Simon Glass wrote:
>
> Hi Roland,
>
> On Tue, 22 Jun 2021 at 07:51, wrote:
>>
>> From: Roland Gaudig
>>
>> This patch extends the setexpr command with a dec operator to
>> convert an input value to decimal.
>>
>> Signed-off-by: Roland Gaudig
>> ---
>>
On Sat, Jun 19, 2021 at 10:15 PM Bin Meng wrote:
>
> On Sat, May 8, 2021 at 12:49 AM David Lamparter wrote:
> >
> > writel() and co. already include the endian swap; doing the swap twice
> > is, er, unhelpful.
> >
> > Tested on a P4080DS, which boots perfectly fine off NVMe with this.
> >
> > Si
Add dts binding header for rk3568, files origin from kernel.
Signed-off-by: Elaine Zhang
Reviewed-by: Kever Yang
---
include/dt-bindings/clock/rk3568-cru.h | 925 +
1 file changed, 925 insertions(+)
create mode 100644 include/dt-bindings/clock/rk3568-cru.h
diff --git
Add basic clock for rk3568 which including cpu, bus, mmc,
i2c, pwm, gmac ...clocks init.
Change in V2:
[PATCH v2 0/1]: No change.
[PATCH v2 0/2]: update the copyright info and remove unused clock set/get.
Elaine Zhang (2):
rockchip: rk3568: add device tree file
rockchip: rk3568: add clock dri
Add rk3568 clock driver and cru structure definition.
Signed-off-by: Elaine Zhang
---
.../include/asm/arch-rockchip/cru_rk3568.h| 504 +++
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rk3568.c | 2832 +
3 files changed, 3337 in
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