Hi Marek,
Am 2022-02-21 17:49, schrieb Marek Vasut:
On 2/21/22 11:10, Michael Walle wrote:
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+
Hi Marek,
Am 21.02.22 um 17:49 schrieb Marek Vasut:
> On 2/21/22 11:10, Michael Walle wrote:
>
> Hi,
>
>>> +int board_phy_config(struct phy_device *phydev)
>>> +{
>>> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
>>> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
On 2/22/22 01:58, Masahisa Kojima wrote:
UEFI specification requires that 5 minutes watchdog timer is
armed before the firmware's boot manager invokes an EFI boot option.
This watchdog timer is updated as follows, according to the
UEFI specification.
1) The EFI Image may reset or disable the
QSGMII PHY present on the j721e common processor board requires
to be initialized before the core boots up. Therefore, run the
corresponding command during boot to do the same.
Signed-off-by: Aswath Govindraju
---
configs/j721e_hs_evm_a72_defconfig | 2 +-
1 file changed, 1 insertion(+), 1
Add the command "boot_rprocs" that is required for booting remote
processors in U-Boot.
Fixes: 5980925e2a5a ("include: configs: j721e_evm: Add support to boot ethfw
core in j721e")
Reported-by: Jesse Villarreal
Signed-off-by: Aswath Govindraju
---
configs/j721e_evm_a72_defconfig | 2 +-
1
QSGMII PHY initialization should only be done for J721E EVMs and not for
J721E-SK boards. Therefore, fix the environment variables accordingly.
Also, by default remote processors should not be booted in U-Boot but
rather be left to the users to enable this by setting dorprocboot.
Therefore,
The following series of patches,
- Fix the initialization of QSGMII PHY such that it is only applicable to
J721E EVM
- Remove the default setting of dorprocboot
- Add boot_rprocs command in the GP bootcmd
- Add phy initialization command in hs bootcmd
Changes since v1:
- Add checks such that
Hi,
On 18/02/22 6:59 pm, Aswath Govindraju wrote:
> The following series of patches fix the bootcmd for J721e,
> - adds the command 'run boot_rpocs' for booting remote processors
> from U-Boot (As it was earlier)
> - removes setting of dorprocboot to 1. Since this should be
> set by the user
From: Haibo Chen
After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use
VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it
involve issue in mmc_switch_voltage(), because of the special
design of usdhc.
For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN,
these are
This patch attempts to fix ram detection on rk3568.
Prior to this, the rk3568 incorrectly detected 8gb ram as 2gb.
On top of this, the board panics when u-boot accesses ram above 4gb.
Fix this by correcting ram detection in hopefully a backwards compatable
way, and extend board_f.c to enforce an
The dwc3 code in the mach-rockchip board file is specific to the rk3399.
Move it to the rk3399 chip specific code.
Signed-off-by: Peter Geis
---
arch/arm/mach-rockchip/board.c | 24 -
arch/arm/mach-rockchip/rk3399/rk3399.c | 29 ++
2 files
Add the required platform data to the rk3568 chip config, in order to
support dwc3 otg on this chip.
Signed-off-by: Peter Geis
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 29 ++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c
Fixup the bootrom recovery mode code to function in spl, so we can
handle recovery mode in case u-boot loading is broken.
Signed-off-by: Peter Geis
---
arch/arm/mach-rockchip/Makefile| 6 +++---
arch/arm/mach-rockchip/boot_mode.c | 4 +++-
arch/arm/mach-rockchip/rk3568/rk3568.c |
Enable rk3568 spl to detect which device it was booted from.
Signed-off-by: Peter Geis
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c
b/arch/arm/mach-rockchip/rk3568/rk3568.c
index
Enable automatic clock gating on rk3568, which solves a 7c temperature
difference on SoQuartz compared to downstream.
Signed-off-by: Peter Geis
---
arch/arm/mach-rockchip/rk3568/rk3568.c | 23 +++
1 file changed, 23 insertions(+)
diff --git
The rockchip-sfc driver sanity checks the maximum frequency, but not the
minimum frequency.
This causes the probe to fail when a frequency isn't defined, such as
with `sf probe 0`.
Clamp the minimum frequency to the rockchip default clock rate.
Signed-off-by: Peter Geis
---
In order to handle the rockchip recovery handler in spl, we need the adc
code to be available in spl.
Add a toggle to allow adc drivers to function in spl.
Signed-off-by: Peter Geis
---
common/spl/Kconfig | 5 +
drivers/Makefile | 1 +
2 files changed, 6 insertions(+)
diff --git
Rockchip emmc devices have a similar issue to Rockchip dwmmc devices,
where performing dma to sram causes errors with suspend/resume.
Allow us to toggle sdma in spl for sdhci similar to adma support, so we
can ensure dma is not used when loading the sram code.
Signed-off-by: Peter Geis
---
The rockchip-sfc driver is missing an include to build correctly.
Signed-off-by: Peter Geis
---
drivers/spi/rockchip_sfc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/rockchip_sfc.c b/drivers/spi/rockchip_sfc.c
index e098acac..851a6482985b 100644
---
to: Simon Glass
to: Philipp Tomsich
to: Kever Yang
to: Lukasz Majewski
to: Sean Anderson
to: Peng Fan
to: Jaehoon Chung
to: Heiko Stübner
cc: u-boot@lists.denx.de
Good Evening,
The following is a few patches for rockchip mainline u-boot support.
Patches 1-3 are fixes for the rk3568 reset
The reset handler for rk3568 is missing its private data. This leads to
an abort when a reset is triggered.
Add the missing dev_set_priv to the rk3568 clk driver.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Peter Geis
---
drivers/clk/rockchip/clk_rk3568.c | 2 ++
UEFI specification requires that 5 minutes watchdog timer is
armed before the firmware's boot manager invokes an EFI boot option.
This watchdog timer is updated as follows, according to the
UEFI specification.
1) The EFI Image may reset or disable the watchdog timer as needed.
2) If control is
On Sat, Feb 19, 2022 at 5:09 PM Adam Ford wrote:
> With the NOP PHY driver available, it can support toggling the
> GPIOS to handle coming out of reset. This series cleans up
> the OMAP EHCI host driver, enables PHY support, and removes
> the code to toggle the reset GPIO's.
>
> This series was
On 2/18/22 21:28, Lukasz Majewski wrote:
> In the Linux kernel (v5.16) for this SoC there are two separate drivers
> - namely sdhci-omap.c and omap_hsmmc.c which have separate set of
> compatibles.
>
> The U-Boot's drivers/mmc/omap_hsmmc.c driver supports both eMMC and
> SD devices - hence the
> From: Simon Glass
> Date: Sun, 20 Feb 2022 21:40:09 -0700
Hi Simon,
> Hi Mark,
>
> On Sun, 20 Feb 2022 at 08:13, Mark Kettenis wrote:
> >
> > > From: Simon Glass
> > > Date: Sat, 19 Feb 2022 15:21:19 -0700
> > >
> > > Hi Mark,
> > >
> > > On Sat, 19 Feb 2022 at 13:37, Mark Kettenis
> > >
The serial_check_stdout() has code to bind devices that are not
marked to be bound before relocation. This code had a known bug
in the past and should not be needed if targets correctly mark
these devices as bound before relocation in the device tree or
mark the appropriate device drivers using
The stdout-path property in the device tree does not necessarily
point at a serial device. On machines such as the Apple M1 laptops
where the serial port isn't easy to access and users expect to see
console output on the integrated display stdout-path may point at
the device tree node for the
Implement PSCI system suspend and placement of DRAM into SSR while the
CPUs are in suspend. This saves non-trivial amount of power in suspend,
on 2x W632GU6NB-15 ~710mW.
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: - Lowercase all the hex values
- Sort bit
Enable DRAM ASR, auto self-refresh, unconditionally. This saves non-trivial
amount of power both at runtime and in suspend (on 2x W632GU6NB-15 ~150mW).
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
V2: Rebase on latest changes in this driver past v2022.01
---
On 2/10/22 20:20, Patrick DELAUNAY wrote:
[...]
+ writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR);
+ setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF);
+
+ setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
+ PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS |
On 2/21/22 01:43, AKASHI Takahiro wrote:
Hi Simon,
On Sat, Feb 19, 2022 at 04:11:08PM -0700, Simon Glass wrote:
Hi,
On Sun, 13 Feb 2022 at 17:54, AKASHI Takahiro
wrote:
Heinrich,
On Fri, Feb 11, 2022 at 08:16:34PM +0100, Heinrich Schuchardt wrote:
On 2/9/22 11:10, AKASHI Takahiro wrote:
On 2/21/22 17:39, Tom Rini wrote:
On Mon, Feb 21, 2022 at 02:31:02PM +0100, Michal Simek wrote:
Hi Tom,
please pull these patches to your tree. I can't see any issue in CI loop.
https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/11047
The biggest problem was that one
On 2/21/22 11:10, Michael Walle wrote:
Hi,
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+
On Sat, Feb 19, 2022 at 9:52 AM Leo Liang wrote:
>
> Hi Alex,
> On Thu, Feb 17, 2022 at 11:28:46AM +0100, Alexandre Ghiti wrote:
> > Hi Leo,
> >
> > On Thu, Feb 17, 2022 at 10:25 AM Leo Liang wrote:
> > >
> > > Hi Alexandre,
> > > On Fri, Jan 28, 2022 at 02:47:13PM +0100, Alexandre Ghiti wrote:
On Tue, Feb 15, 2022 at 09:10:09PM +0300, Nikita Yushchenko wrote:
> Per documentation, dm_i2c_ops.probe_chip() shall return -EREMOTEIO if
> probe fails.
>
> Currently, omap_i2c_probe_chip() returns 1 instead. Fix that.
>
> Signed-off-by: Nikita Yushchenko
> Reviewed-by: Heiko Schocher
On Tue, Feb 15, 2022 at 06:14:40PM +0800, Neal Liu wrote:
> Check interrupt status to see if RSA engine is completed. After completion
> of the task, write-clear the status to finish operation.
> Add missing register base for completion.
>
> Fixes: 89c36cca0b6 ("crypto: aspeed: Add AST2600 ACRY
On Mon, Feb 14, 2022 at 10:09:26PM +0100, Mark Kettenis wrote:
> U-Boot now supports NVMe storage and on the laptop models, the
> SPI keyboard. Since we now disable the debug console by default
> provide instructions on how the enable the debug console including
> a table listing the appropriate
On Mon, Feb 14, 2022 at 10:09:25PM +0100, Mark Kettenis wrote:
> The address of the debug UART varies differs between the M1 and
> the M1 Pro/Max SoCs. So we have to disable it to make a single
> U-Boot binary that works on all SoC generations. Leave the
> settings for the base address and
On Sun, Feb 13, 2022 at 12:48:48PM -0600, Suman Anna wrote:
> The default U-Boot environment variables and design are all set up for
> the MAIN R5FSS cluster to be in Split-mode. This is the setting used
> when the dts nodes were originally added in v2021.01 U-Boot and the
> dt nodes are synched
On Sat, Feb 12, 2022 at 06:12:41AM -0600, Adam Ford wrote:
> There are a few memory functions for both the emif4 (AM3517)
> and sdrc (OMAP35/DM37) code that can be defined as static,
> because those functions are not used externally. Make them
> static and clean up some of the corresponding
On Sat, Feb 12, 2022 at 06:12:40AM -0600, Adam Ford wrote:
> With LTO enabled, some functions appear to be optimized in a
> way that causes hanging on some OMAP3 boards after some
> unrelated patches were applied. The solution appears to make
> several functions __used. There also appears be to
On Thu, Feb 10, 2022 at 09:25:58AM +0530, Keerthy wrote:
> Correct the min/max voltages of VDD_CPU. As per data sheet the VDD_CPU
> minimum voltage is .6V & maximum voltage is .9V.
>
> Correct the same. While at it fix the comment to reflect VDD_CPU
> instead of VDD_MPU.
>
> Data Sheet Link:
On Tue, Feb 08, 2022 at 10:27:49PM +0100, Janne Grunau wrote:
> For the purpose of this driver (activating bypass mode) t6000-dart
> and t8103-dart are fully compatible.
>
> Signed-off-by: Janne Grunau
> Reviewed-by: Mark Kettenis
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Tue, Feb 08, 2022 at 10:00:09PM +0100, Mark Kettenis wrote:
> Choose the memory map based on the compatible property from the
> device tree passed to us by m1n1. Since DRAM on the M1 Pro/Max
> starts at a different address avoid hardcoding the top of usable
> memory. Also make sure that the
On Mon, Feb 21, 2022 at 02:31:02PM +0100, Michal Simek wrote:
> Hi Tom,
>
> please pull these patches to your tree. I can't see any issue in CI loop.
> https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/11047
>
> The biggest problem was that one fdt patch broke all ZynqMP
From: Jan Kiszka
When running against RC_OSC_32k, the watchdog may suffer from running
faster than expected, expiring earlier. The Linux kernel adds a 10%
margin to the timeout calculation by slowing down the read clock rate
accordingly. Do the same here, also to have comparable preset values
Signed-off-by: Peter Griffin
---
configs/rock-pi-4-rk3399_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/rock-pi-4-rk3399_defconfig
b/configs/rock-pi-4-rk3399_defconfig
index 4f15627d59..93dfeb9d95 100644
--- a/configs/rock-pi-4-rk3399_defconfig
+++
Allow u-boot to probe optee so we can access secure os
from the bootloader.
Signed-off-by: Peter Griffin
---
arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi
Allow u-boot to probe optee so we can access secure os
from the bootloader.
Signed-off-by: Peter Griffin
---
arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rk3399-rock-pi-4b-u-boot.dtsi
On Mon, Feb 21, 2022 at 02:50:19PM +0100, Felix Brack wrote:
> Hi Tom,
>
> On 21.02.22 14:34, Tom Rini wrote:
> > On Mon, Feb 21, 2022 at 02:26:05PM +0100, Felix Brack wrote:
> >
> >> To make sure we get a working console as soon as possible in the SPL the
> >> UART pins require to be configured
Hi Tom,
On 21.02.22 14:34, Tom Rini wrote:
> On Mon, Feb 21, 2022 at 02:26:05PM +0100, Felix Brack wrote:
>
>> To make sure we get a working console as soon as possible in the SPL the
>> UART pins require to be configured earlier. This is especially
>> true for the pins of UART3, since the
On Mon, Feb 21, 2022 at 02:26:05PM +0100, Felix Brack wrote:
> To make sure we get a working console as soon as possible in the SPL the
> UART pins require to be configured earlier. This is especially
> true for the pins of UART3, since the PDU001 board uses this UART for
> the console by
Hi Tom,
please pull these patches to your tree. I can't see any issue in CI loop.
https://source.denx.de/u-boot/custodians/u-boot-microblaze/-/pipelines/11047
The biggest problem was that one fdt patch broke all ZynqMP platforms in a
configuration which we are using it.
I will work to get
To make sure we get a working console as soon as possible in the SPL the
UART pins require to be configured earlier. This is especially
true for the pins of UART3, since the PDU001 board uses this UART for
the console by default.
Signed-off-by: Felix Brack
---
board/eets/pdu001/board.c | 30
Hi Marc, Zhiqiang
> -Original Message-
> From: Marc Zyngier
> Sent: Monday, February 21, 2022 4:23 PM
> To: Michael Walle
> Cc: Wasim Khan (OSS) ; s...@chromium.org;
> Priyanka Jain ; tred...@nvidia.com;
> twar...@nvidia.com; Varun Sethi ; u-
> b...@lists.denx.de; Wasim Khan
> Subject:
Hi Simon,
On 2022-02-19 14:12, Simon Glass wrote:
On Wed, 2 Feb 2022 at 16:16, Angus Ainslie wrote:
Put guards around the devres code so that it isn't compiled during the
SPL.
Signed-off-by: Angus Ainslie
---
drivers/core/devres.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
út 15. 2. 2022 v 8:57 odesílatel Michal Simek napsal:
>
> This header shouldn't be in this file and there is already pointer to
> dt-bindings/gpio/gpio.h.
>
> Fixes: d2d14383bae4 ("arm64: zynqmp: Add support for DLC21 (Smartlynq+)
> board")
> Signed-off-by: Michal Simek
> ---
>
>
čt 17. 2. 2022 v 14:28 odesílatel Michal Simek napsal:
>
> Hi,
>
> I found that two commits which were recently merged to u-boot are breaking
> especially Xilinx ZynqMP boards.
> The commit 985503439762 ("fdt: Don't call board_fdt_blob_setup()
> and commit 0dba45864b2a ("arm: Init the debug
Add support for Data Modul i.MX8M Mini eDM SBC board. This is an
evaluation board for various custom display units. Currently
supported are serial console, ethernet, eMMC, SD, SPI NOR,
USB host and USB OTG.
Signed-off-by: Marek Vasut
Cc: Fabio Estevam
Cc: Peng Fan
Cc: Stefano Babic
---
On Mon, 21 Feb 2022 10:24:36 +,
Michael Walle wrote:
>
> Hi,
>
> Am 2022-02-21 11:16, schrieb Wasim Khan:
> > From: Wasim Khan
> >
> > Memory after gd->arch.resv_ram is reserved for MC block.
> > Use ALIGN_DOWN to avoid updating MC block for unaligned
> > address.
>
> I cannot really
Hi,
Am 2022-02-21 11:16, schrieb Wasim Khan:
From: Wasim Khan
Memory after gd->arch.resv_ram is reserved for MC block.
Use ALIGN_DOWN to avoid updating MC block for unaligned
address.
I cannot really tell what you are trying to do here. But I
know Marc has offered to also take a look at the
On 2/18/22 17:46, Marek Behún wrote:
From: Marek Behún
Enable ext4 write support in Turris Omnia's defconfig. Some users find
it useful.
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
configs/turris_omnia_defconfig | 1 +
1 file changed, 1 insertion(+)
diff
From: Wasim Khan
Memory after gd->arch.resv_ram is reserved for MC block.
Use ALIGN_DOWN to avoid updating MC block for unaligned
address.
Signed-off-by: Wasim Khan
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Hi Marek,
> +int board_phy_config(struct phy_device *phydev)
> +{
> + /* enable rgmii rxc skew and phy mode select to RGMII copper */
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
> + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
> +
> + phy_write(phydev, MDIO_DEVAD_NONE,
Switch to use binman to pack images
Signed-off-by: Oliver Graute
Reviewed-by: Simon Glass
---
Changes for v2
- added imx8qm-u-boot.dtsi here to
- rebased on master
arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
arch/arm/dts/imx8qm-u-boot.dtsi | 133
On 18/02/22, Stefano Babic wrote:
> Hi Oliver,
>
> On 16.02.22 20:00, Simon Glass wrote:
> > On Wed, 16 Feb 2022 at 07:02, Oliver Graute
> > wrote:
> > >
> > > Switch to use binman to pack images
> > >
> > > Signed-off-by: Oliver Graute
> > > ---
> > > arch/arm/dts/imx8qm-cgtqmx8.dts |
As per DT bindings since Linux kernel v5.14, the device tree can define
only 1 SCMI agent node that is named scmi [1]. As a consequence, change
implementation of the SCMI driver test through sandbox architecture to
reflect that.
This change updates sandbox test DT and sandbox SCMI driver
Implements SCMI APIs to retrieve the number exposed SCMI clocks using
SCMI_PROTOCOL_ATTRIBUTES messages and the names of the clocks using
SCMI_CLOCK_ATTRIBUTES messages.
This change updates sandbox SCMI clock test driver to manage these
2 new message IDs.
Cc: Lukasz Majewski
Cc: Sean Anderson
Updates sandbox SCMI clock driver and tests since enabling CCF will
mandate clock discovery that is all exposed SCMI clocks shall be
discovered at initialization. For this reason, sandbox SCMI clock
driver must emulate all clocks exposed by SCMI server, not only those
effectively consumed by some
Changes devm_scmi_process_msg() first argument from target parent device
to current SCMI device and lookup the SCMI agent device among SCMI device
parents for find the SCMI agent operator needed for communication with
the firmware.
This change is needed in order to support CCF in clk_scmi driver
Changes SCMI bindings documentation to relate to Linux kernel
source tree that recently changed the bindings description to YAML
format.
Reviewed-by: Patrick Delaunay
Signed-off-by: Etienne Carriere
---
Changes since v1:
- Apply R-b tag.
---
doc/device-tree-bindings/arm/arm,scmi.txt | 236
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