From: Tien Fong Chee
Switching to watchdog 1, because there is a hardware bug found in
watchdog 0, it cannot reliable trigger a reset to the CPU.
More details can be referred in :
Linux commit "59d94d2ed45d598211feb52566e6a806d17f8a3f"
Signed-off-by: Tien Fong Chee
Signed-off-by: Teik Heng
From: Tien Fong Chee
Add watchdog 1 support to A10, ensure the same enable/disable process as
watchdog 0.
Signed-off-by: Tien Fong Chee
Signed-off-by: Teik Heng Chong
---
.../mach-socfpga/include/mach/base_addr_a10.h | 1 +
.../include/mach/reset_manager_arria10.h | 1 +
From: Tien Fong Chee
It's confusing to have timer related words along with watchdog reset
dessert function, because the function is only release watchdog from
reset, so it has no related to any timer setting.
Signed-off-by: Tien Fong Chee
Signed-off-by: Teik Heng Chong
---
From: Tien Fong Chee
There is a potential risk that memset on DDR taking too long than the
timeout set for watchdog, hence the function is restructured so that
splitting up the DDR into chunks for memset and resetting the watchdog for
each chunk memory.
Signed-off-by: Tien Fong Chee
From: Tien Fong Chee
Some bootROMs enable the watchdog before jumping to SPL, so calling
WATCHDOG_RESET() is required to reset watchdog timely especially
in long looping. Enable Designware watchdog driver is required to
support WATCHDOG_RESET().
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley
On Thu, 15 Sept 2022 at 03:15, Sughosh Ganu wrote:
> +/**
> + * fwu_get_active_index() - Get active_index from the FWU metadata
> + * @active_idxp: active_index value to be read
> + *
> + * Read the active_index field from the FWU metadata and place it in
> + * the variable pointed to be the
On Monday 19 September 2022 10:57:10 Chris Packham wrote:
> Having looked more into mox-imager (and WtpDownloader) I've realised
> that the AlleyCat5 uses something called "TIM" but it's different to
> the format used by Armada-3700. I suspect what I'm actually dealing
> with is a TIMv0 that
Hi Pali,
On Sat, Sep 17, 2022 at 12:37 AM Pali Rohár wrote:
>
> On Friday 16 September 2022 22:34:52 Chris Packham wrote:
> > I do wonder if the boot seqence and xmodem stuff could be abstracted out to
> > something that could be reused by other tools.
>
> In the past I was thinking about it...
> From: Fabio Estevam
> Currently, when running ./scripts/get_maintainer.pl on serial_mxc.c
> no i.MX maintainer is returned.
> Fix it by adding an entry for this driver.
> Reported-by: Pali Rohár
> Signed-off-by: Fabio Estevam
> Acked-by: Peng Fan
Applied to u-boot-imx, master, thanks !
Best
> Fix copy-paste error of the I2C5 bus recovery GPIO assignment,
> the I2C5 GPIOs are on gpio3 instead of gpio5.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> This PHY is not used on PDK2, the header was added due to copy-paste
> error, drop it.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> From: Peng Fan
> "alloc space exhausted" happens in very early stage, which could be seen
> with DEBUG_UART options enabled and leeds to an non-functional board.
> kontron_pitx_imx8m:
> CONFIG_DEBUG_UART_BASE=0x3088 # for serial3
> CONFIG_DEBUG_UART_CLOCK=2400
> imx8mqevk:
>
> Enable both USB CDC ethernet and USB host ethernet on i.MX8M Plus DHCOM.
> This is useful for bringing up systems without ethernet plug, but with
> either USB host or gadget plug.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to
> Erase the entire U-Boot area during U-Boot update instead of just
> a subset of it. This way, in case u-boot-with-spl.imx grows, the
> sf write won't write over non-erased part of the SPI NOR.
> Signed-off-by: Marek Vasut
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> From: Marcel Ziswiler
> Prepare for optional job ring driver model. Sec may be initialized based
> on the job ring information processed from the device tree.
> Signed-off-by: Marcel Ziswiler
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> only waiting for TXEMPTY leads to corrupted messages going over the
> wire - which is fixed by making use of the FIFO
> this change is following the linux kernel uart driver
> (drivers/tty/serial/imx.c), which also checks UTS_TXFULL
> instead of UTS_TXEMPTY
> Signed-off-by: Johannes Schneider
>
> Enable GPIO hog support in SPL to match the GPIO hog support in U-Boot proper.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
> Reviewed-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Adjust the DRAM timing settings for this board per ones provided
> by hardware department. The change is applied to the LPDDR4 MR11
> register CA ODT configuration, from RZQ/6 to RZQ/3, which fixes
> stability issues on subset of boards. The DDR PHY PIE block has
> been updated accordingly.
>
> From: Marcel Ziswiler
> - integrate bootcount using SNVS_LP general purpose register LPGPR0
> - enable link-time optimisation
> - explicitly set a boot delay of one second
> - enable CRC32 and MD5
> - enable command for low-level access to data in a partition
> - enable time commands
> - enable
> From: Marcel Ziswiler
> - Annotate boot devices available in spl_board_boot_device().
> - Drop SD3_BOOT/MMC3_BOOT not available for boot on Verdin iMX8M Mini.
> Signed-off-by: Marcel Ziswiler
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Commit 99c7cc58e12 ("ddr: imx: Add i.MX9 DDR controller driver")
> contains an inobvious side-effect which renders all systems using
> DRAM controller at 3732 MT/s unbootable. The change is located in
> ddrphy_init_set_dfi_clk(), where the switch case statement entry
> 3732 changed to entry
> The GW73xx-C revision and onward replaced the 5-port PCIe switch with a
> 4-port (dropping PCIe to one of the miniPCIe sockets) due to part
> availability. This moved the PCI bus of the GbE eth1 device. Use a fixup
> to adjust the dt accordingly so that local-mac-address assigned from dt
> works
> From: Denys Drozdov
> This code part is broken, remove it.
> Signed-off-by: Andrejs Cainikovs
> Signed-off-by: Denys Drozdov
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
> Add information about which exact SoM variant is used on which PDK2 variant.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Initial commit of Librem5 u-boot and SPL
> Signed-off-by: Angus Ainslie
> Co-developed-by: Sebastian Krzyszkowiak
> Signed-off-by: Sebastian Krzyszkowiak
> Reviewed-by: Fabio Estevam
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> Rename imx8mp-dhcom-pdk2-u-boot.dtsi to imx8mp-dhcom-u-boot.dtsi, since
> this file is shared by PDK2, PicoITX and DRC02. No functional change.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best
> The ECSPI1 is on I2C1/I2C2 pins of the SoC, update the pinmux accordingly.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> When the imx8mm.dtsi file was pulled in from Linux, the UARTs
> were moved into an spba sub-node which wasn't being included
> in the SPL device tree. This meant the references to the UART
> weren't being handled properly and when booting the system would
> constantly reboot. Fix this by
> From: Denys Drozdov
> This code part is broken, remove it.
> Signed-off-by: Andrejs Cainikovs
> Signed-off-by: Denys Drozdov
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software
> The ddrphy_utils.c is now deduplicated in drivers/ddr/imx/phy/ddrphy_utils.c ,
> this drivers/ddr/imx/imx8m/ddrphy_utils.c is a remnant from when the
> deduplication was implemented and was not removed. Remove it as it is
> unused.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng
> Add SoM compatible string into i.MX8MP DHCOM PDK2 compatible strings.
> Signed-off-by: Marek Vasut
> Cc: Fabio Estevam
> Cc: Peng Fan
> Cc: Stefano Babic
> Cc: uboot-imx
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
> From: Marcel Ziswiler
> Update the distro config env memory layout for the Verdin iMX8M Mini and
> Verdin iMX8M Plus:
> - loadaddr=0x4828 allows for 128.5MB area for uncompressing (ie FIT
> images, kernel_comp_addr_r, kernel_comp_size)
> - fdt_addr_r = loadaddr + 127.5MB : allows for
> on imx8(mm) the RXDMUXSEL needs to be set for data going over the wire
> (as observable on a connected 'scope) to actually make it into the
> RXFIFO
> the reference manual is not overly clear about this, and only
> mentiones that "UCR3_RXDMUXSEL should always be set." - and since the
> CR3
On Sun, Sep 18, 2022 at 03:38:52PM +0200, Marek Behún wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> Hello Tom,
>
> I am sending some fixes for mpc85xx v2022.10-rc5. The other patches
> from Pali require some more work, I am working on them.
>
> The following changes since
BootROM loads kwbimage header to L2-SRAM and BootROM reserve only 192 kB for it.
Signed-off-by: Pali Rohár
---
tools/kwbimage.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tools/kwbimage.c b/tools/kwbimage.c
index 94b768539222..6abb9f2d5c01 100644
--- a/tools/kwbimage.c
+++
Implement setbrg in amlogic/meson serial device with driver model
similar to how the meson_uart.c driver does it in Linux. Also
configure (probe) the serial device with the new reg5 register.
Signed-off-by: Edoardo Tomelleri
---
drivers/serial/serial_meson.c | 70
On 8/10/22 00:29, Joel Stanley wrote:
LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.
Signed-off-by: Joel Stanley
---
include/linux/litex.h | 83
drivers/net/liteeth.c | 214
On Sun, Sep 18, 2022 at 12:09 PM Michael Trimarchi
wrote:
>
> Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
> imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
>
> Add support for imx6ulz BSH SMM M2 board:
>
> - 128 MiB DDR3 RAM
> - 256MiB Nand
> - USBOTG1 peripheral -
On Sun, Sep 18, 2022 at 12:39:17PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
Applied to u-boot/next, thanks!
--
Tom
signature.asc
Description: PGP signature
From: Ley Foon Tan
Setting up firewall regions based on SDRAM memory banks configuration
(up to CONFIG_NR_DRAM_BANKS banks) instead of using whole address space.
First 1 MiB (0 to 0xf) of SDRAM is configured as secure region,
other address spaces are non-secure regions. The ARM Trusted
From: Ley Foon Tan
Add section 3.2 for SDRAM secure region update.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
doc/README.socfpga | 327 -
1 file changed, 174 insertions(+), 153 deletions(-)
diff --git a/doc/README.socfpga
From: Ley Foon Tan
spl_board_prepare_for_boot() function is only called in U-boot flow, not
for ATF flow.
Change to use spl_perform_fixups() to support U-boot and ATF flow.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/spl_soc64.c | 2 +-
1 file changed,
From: Ley Foon Tan
socfpga_init_smmu() change the L3 masters (eg: SDMMC, NAND and etc) to
non-secure , this cause the failure when L3 masters loading SSBL image to
secure region in DDR.
Move socfpga_init_smmu() to spl_perform_fixups(), so, it is called prior
running SSBL.
Signed-off-by: Ley
From: Ley Foon Tan
Move spl_board_prepare_for_boot() to spl_soc64.c.
spl_board_prepare_for_boot() will use for all SoC64 platforms.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/spl_soc64.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
Add support for imx6ulz BSH SMM M2 board:
- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.
Signed-off-by: Michael Trimarchi
---
Changes V4->V5:
- Add
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hello Tom,
I am sending some fixes for mpc85xx v2022.10-rc5. The other patches
from Pali require some more work, I am working on them.
The following changes since commit 4f2c559b9a2ad86e03dffeef720257ea680707d0:
Merge tag
From: Yau Wai Gan
Reset the watchdog within functions that require long processing
time to prevent watchdog timeout.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
drivers/spi/cadence_qspi_apb.c | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Ley Foon Tan
Add checking for INTEL_SIP_SMC_STATUS_BUSY (1).
Status busy means transfer is accepted but SDM does not have more freed
buffer. It is not an error. Continue process the data if receive OK and
BUSY status.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
On Sun, Sep 18, 2022 at 02:00:09PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull these last minute fixes for Armada / Kirkwood:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
From: Andy Yan
Specification
- Rockchip RK3399
- LPDDR3 4GB
- TF sd scard slot
- eMMC
- AP6255 for WiFi + BT
- Gigabit ethernet
- HDMI out
- 40 pin header
- USB 2.0 x 2
- USB 3.0 x 1
- USB 3.0 Type-C x 1 work in otg mode
- 12V DC Power supply
The dts file is sync from linux-next[0].
From: Siew Chin Lim
Add SDRAM driver for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/misc.h |4 +
arch/arm/mach-socfpga/misc_soc64.c| 70 +-
drivers/ddr/altera/sdram_dm.c | 1227
From: Siew Chin Lim
Add base dtsi and devkit dts for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
Signed-off-by: Jit Loon Lim
---
arch/arm/dts/socfpga_dm-u-boot.dtsi | 102
arch/arm/dts/socfpga_dm.dtsi | 640 ++
From: Siew Chin Lim
Enable build for Intel Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/Kconfig| 18
arch/arm/mach-socfpga/Makefile | 31 +
configs/socfpga_dm_atf_defconfig | 77
From: Siew Chin Lim
Add CONFIGs for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
include/configs/socfpga_dm_socdk.h | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 include/configs/socfpga_dm_socdk.h
diff --git
From: Siew Chin Lim
Add SPL for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/spl_dm.c | 97 ++
1 file changed, 97 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_dm.c
diff --git
From: Siew Chin Lim
Add memory clock manager driver for Diamond Mesa. Provides
clock initialization and enable functions.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
drivers/clk/altera/clk-mem-dm.c | 135
drivers/clk/altera/clk-mem-dm.h | 84
From: Siew Chin Lim
Add clock manager driver for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/clock_manager_dm.c | 79 +++
.../include/mach/clock_manager_dm.h | 14
2 files changed, 93 insertions(+)
From: Siew Chin Lim
Add socdk board support for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
board/intel/dm-socdk/MAINTAINERS | 7 +++
board/intel/dm-socdk/Makefile| 7 +++
board/intel/dm-socdk/socfpga.c | 7 +++
3 files changed, 21
From: Siew Chin Lim
Add clock manager driver for Diamond Mesa. Provides clock
initialization and get_rate functions.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
drivers/clk/altera/clk-dm.c | 504 +++
drivers/clk/altera/clk-dm.h | 217
Hi Tom,
please pull these last minute fixes for Armada / Kirkwood:
- mvebu: turris_omnia: Fix setting switch CONFIG pins on new board
design (Marek)
- orion-timer: Use timer_conv_64() to fix timer wrap around (Stefan)
On Monday 12 September 2022 17:58:09 Sean Anderson wrote:
> You can use TEST_STATIC from test/export.h this case.
Now I sent new patch version where I extended comment.
I have still issue with test framework. Could you help me how to write
that unit test and run it? Scenario should really
32-bit U-Boot builds cannot use more than around 2 GB of DDR memory. But on
some platforms/boards it is possible to connect also 4 GB SODIMM DDR memory.
U-Boot currently prints only effective size of RAM which can use, which may
be misleading as somebody would expect that this line prints total
From: Siew Chin Lim
Diamond Mesa support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced in Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Jit Loon Lim
---
On 15.09.22 16:20, Stefan Roese wrote:
While testing on some Kirkwood platforms it was noticed that the timer
did not function correctly all the time. The driver did not correctly
handle 32bit timer value wrap arounds. Using the timer_conv_64()
conversion function fixes this issue.
Fixes:
On 13.09.22 18:10, Marek Behún wrote:
It seems that waiting only 10 ms after releasing LAN switch from reset
is not enough for the strapping pins to latch the requested values.
P6_MODE[0] is latched to 0 instead of 1.
Increasing the delay to 50 ms fixes this issue.
Signed-off-by: Marek Behún
Hi Tom,
please pull the following watchdog related patches:
- Migrate watchdog reset to cyclic infrastructure (Stefan)
Here the Azure build, without any issues:
Hi Michael,
On 16.09.22 14:53, Michael Nazzareno Trimarchi wrote:
Hi Stefano
I have more patches on m2 and I need to know if you are going to
request the merge to Tom soon or later. Alternative you can drop
this one and keep the new one
I am checking which patches should flow into the
On Tue, Aug 9, 2022 at 2:53 PM Rasmus Villemoes
wrote:
>
> Currently, U-Boot doesn't parse a "max-speed" DT property in a phy's
> DT node. That property is a standard binding which should be honoured,
> and in linux that is done by the core phy code via a call to an
> of_set_phy_supported()
On Wed, Aug 10, 2022 at 7:30 AM Joel Stanley wrote:
>
> LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
> network device that is commonly used in LiteX designs.
>
> Signed-off-by: Joel Stanley
> ---
> include/linux/litex.h | 83
> drivers/net/liteeth.c |
On Tue, Sep 13, 2022 at 9:25 AM Jim Liu wrote:
>
> The original patch is use phy_get_interface_by_name to set interface.
> The new patch is use dev_read_phy_mode to replace it.
>
> Signed-off-by: Jim Liu
> ---
> drivers/net/npcm750_eth.c | 8
> 1 file changed, 4 insertions(+), 4
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