Hello Conor,
On 26.10.22 09:49, Conor Dooley wrote:
> A late ack is currently being sent at the end of a transfer due to
> incorrect logic in mchp_corei2c_empty_rx(). Currently the Assert Ack
> bit is being written to the controller's control reg after the last
> byte has been received, causing it
Hello Conor,
On 26.10.22 09:49, Conor Dooley wrote:
> "Master receive mode" was not correctly sending ACKs/NACKs in the
> interrupt handler. Bring the handling of M_SLAR_ACK, M_RX_DATA_ACKED &
> M_RX_DATA_NACKED in line with the Linux driver.
>
> Fixes: 0dc0d1e094 ("i2c: Add Microchip PolarFire S
Hello Sergei,
On 20.10.22 16:28, Sergei Antonov wrote:
> Add newline at the end of the printed string.
>
> Signed-off-by: Sergei Antonov
> ---
> drivers/i2c/i2c-gpio.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks!
Reviewed-by: Heiko Schocher
bye,
Heiko
--
DENX Software En
On Fri, 11 Nov 2022 at 21:53, Ilias Apalodimas
wrote:
>
> [...]
>
> > +/**
> > + * prepare_signature_list_menu() - create the signature list menu entry
> > + *
> > + * @efimenu: pointer to the efimenu structure
> > + * @varname: pointer to the variable name
> > + * @db: pointer to the
On Sun, Nov 13, 2022 at 03:47:38PM -0600, Samuel Holland wrote:
> On 11/5/22 01:02, Yu Chien Peter Lin wrote:
> > We should check the string until it hits underscore, in case it
> > searches for the letters in the custom extension. For example,
> > "rv64imac_xandes" will be treated as D extension s
Hi Ilias,
On Fri, 11 Nov 2022 at 21:33, Ilias Apalodimas
wrote:
>
> Hello Kojima-san!
>
> [...]
>
> > + file_info.current_path = calloc(1, EFICONFIG_FILE_PATH_BUF_SIZE);
> > + if (!file_info.current_path) {
> > + ret = EFI_OUT_OF_RESOURCES;
> > + goto out;
> > +
On 11/5/22 01:02, Yu Chien Peter Lin wrote:
> We should check the string until it hits underscore, in case it
> searches for the letters in the custom extension. For example,
> "rv64imac_xandes" will be treated as D extension support since
> there is a "d" in "andes", resulting illegal instruction
Add test case for 'fdt get value' sub command.
The test case can be triggered using:
"
./u-boot -d u-boot.dtb -c 'ut fdt'
"
Signed-off-by: Marek Vasut
---
Cc: Heinrich Schuchardt
Cc: Simon Glass
Cc: Tom Rini
---
test/cmd/fdt.c | 53 ++
1 file c
Always increment both the iterator and pointer into the string
property value by length of the current element + 1 (to cater
for the string delimiter), otherwise the element extracted from
the string property value would be extracted from an offset that
is multiple of the length of the first elemen
On 9/1/22 23:18, Tom Rini wrote:
On Sat, Jul 09, 2022 at 03:08:04AM +0200, Marek Vasut wrote:
Convert CONFIG_MALLOC_F_ADDR to Kconfig.
The CL IoT gate board used MALLOC_F_ADDR 0x912000 on i.MX8M Mini unlike
all the other platforms which use 0x93 . This has been aligned with
the other i.MX8
From: Ley Foon Tan
HSD #1508586908-6: Software shouldn't hang the system if the HPS bridge reset
is failed.
Change hang() to error message.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
.../include/mach/base_addr_soc64.h| 1 +
arch/arm/mach-socfpga/include/mach/tim
From: Ley Foon Tan
HSD #1508586908-5: Add F2H and F2SDRAM bridges disable/enable support, based on
software
programming flow in HW documentation.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 122 +-
1 file changed
From: Ley Foon Tan
HSD #1508586908-2: Add reset manager registers, preparation for f2s bridge
reset support.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-s
From: Ley Foon Tan
HSD #1508586908-3: Move bridges reset code to common function,
socfpga_s2f_bridges_reset().
This function is an inline function and can be included in normal U-boot
and psci secure section.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/r
From: Ley Foon Tan
HSD #1508586908-1: Add F2SDRAM Manager base address.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
.../include/mach/reset_manager_soc64.h| 26 ---
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/incl
From: "Lokanathan, Raaj"
Update the tested Intel Quartus Software versions and highlight the
major changes in this U-boot version.
Signed-off-by: Lokanathan, Raaj
Signed-off-by: Jit Loon Lim
---
doc/README.socfpga | 104 +++--
1 file changed, 82 inserti
From: Ley Foon Tan
HSD #1508690657-3: Add guide for mkimage for Cyclone V, Arria V and Arria 10.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
doc/README.socfpga | 317 +++--
1 file changed, 193 insertions(+), 124 deletions(-)
diff --git
From: Yau Wai Gan
The official boot-up flow for SoC FPGA 64-bit is with
Arm Trusted Firmware, ATF BL31. The non-ATF flow is
legacy and is not supported officially moving forward.
Update the README to include the information.
Signed-off-by: Yau Wai Gan
Signed-off-by: Jit Loon Lim
---
doc/READM
From: Ley Foon Tan
HSD #1508690657-2: The existing socfpgaimage always pads the image to the
maximum size of
OCRAM size. This will break in the encryption flow where it expects the
image to be un-padded. The encryption tool will do the encryption for
the whole image and append the signature key
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