On 12/15/22 08:16, Miquel Raynal wrote:
Hi Marek & Francesco,
Hi,
ma...@denx.de wrote on Mon, 5 Dec 2022 17:25:11 +0100:
On 12/5/22 14:49, Miquel Raynal wrote:
Hi Francesco,
Hi,
france...@dolcini.it wrote on Mon, 5 Dec 2022 12:26:44 +0100:
On Fri, Dec 02, 2022 at 06:08:22PM +0100,
Hi Marek & Francesco,
ma...@denx.de wrote on Mon, 5 Dec 2022 17:25:11 +0100:
> On 12/5/22 14:49, Miquel Raynal wrote:
> > Hi Francesco,
>
> Hi,
>
> > france...@dolcini.it wrote on Mon, 5 Dec 2022 12:26:44 +0100:
> >
> >> On Fri, Dec 02, 2022 at 06:08:22PM +0100, Marek Vasut wrote:
> >>>
On 12/5/22 18:45, Andre Przywara wrote:
> So far we were open-coding the pincontroller's GPIO output/input access
> in each function using that.
>
> Provide two functions that wrap that nicely, so users don't need to know
> about the internals, and we can abstract the new D1 pinctrl more easily.
>
On 12/13/22 12:01, Niel Fourie wrote:
Hi Marek,
Hi,
On 12/12/2022 17:46, Marek Vasut wrote:
On 12/12/22 16:29, Niel Fourie wrote:
Split out _usb_eth_start() from _usb_eth_init() and
usb_eth_stop() from _usb_eth_halt(). Now _usb_eth_init() only
initialises and registers the gadget device, wh
On Tue, 13 Dec 2022 at 22:45, Marek Vasut wrote:
>
> Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
> forces '$fdtcontroladdr' DT address as a third parameter of bootm command
> even if the PXE transfer pulls in a fitImage which contains configuration
> node with its own
Andre,
On 12/14/22 08:25, Andre Przywara wrote:
> On Wed, 14 Dec 2022 02:37:12 -0600 Samuel Holland wrote:
>> On 12/5/22 18:45, Andre Przywara wrote:
>>> diff --git a/configs/Sinovoip_BPI_M3_defconfig
>>> b/configs/Sinovoip_BPI_M3_defconfig
>>> index ab70eff68eb..bcc8b1fba98 100644
>>> --- a/con
Neural Compute Module 2(Neu2) IO board is an industrial form factor
IO board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansio
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.
Both eMMC and SD boot are tested in Edgeble Neu2 SoM.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
arch/arm/dts/rv11
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT
Industrial grade (-40 °C to +85 °C) version of the same class of
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.
Add arch core support for it.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- drop MONITOR_LEN config
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
Add support for rv1126 package header in mkimage tool.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.
Signed-off-by: Jason Zhu
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
arch/arm/mach-rockchip/rv1126/rv1126.c
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports IN
Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rv1126.c |
Add GRF header for Rockchip RV1126.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../include/asm/arch-rockchip/grf_rv1126.h| 251 ++
1 file changed, 251 insertions(+)
create mode 100
Add pinctrl definitions for Rockchip RV1126.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- pick changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
arch/arm/dts/rv1126-pinctrl.dtsi | 211 +++
1 file changed, 211 in
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- sync changes from linux
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../dt-bindings/power/rockchip,rv1126-power.h
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- sync changes from linux
Changes for v3:
- collect Kever r-b
C
Add pinctrl driver for Rockchip RV1126.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rv1126.
Add clock and reset unit header include for rv1126.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../include/asm/arch-rockchip/cru_rv1126.h| 459 ++
1 file changed, 459 insertions(+)
Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.
Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Cha
Add LPDDR4 detection timings and support for RV1126.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../sdram-rv1126-lpddr4-detect-1056.inc | 78 +++
.../sdram-rv1126-lpddr4-detect-32
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.
This gives an option to configs to enable these prints or
not.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
dri
Add DDR loader parameters for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../rockchip/sdram-rv1126-loader_params.inc | 197 ++
1 file
Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../sdram-rv1126-ddr3-detect-1056.inc | 72 +++
.../ro
Add full ddr pctl registers and bit masks for px30.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
.../asm/arch-rockchip/sdram_pctl_px30.h | 100 +-
driver
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.
Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.
Signed-off-by: Jagan Teki
Reviewed-by: Kever Yang
---
Changes for v4:
- none
Changes for v3:
- collect Kever r-b
Changes for v2:
- none
drivers/ram/Makefile | 2 +-
From: Jagan Teki
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
This patch series add basic core support for Rockchip RV1126
and boot from eMMC and SD.
Tested RV1126 in Edgeble Neural Compute Module 2.
Changes for v4:
- rebased linux merged patches
- updated
On Thu, 3 Nov 2022 at 11:50, Jagan Teki wrote:
>
> fdt_addr will build as part of SPL_LOAD_FIT or SPL_LOAD_FIT_FULL
> which is indeed required to build optee image support in SPL.
>
> common/spl/spl.c: In function ‘jump_to_image_optee’:
> common/spl/spl.c:220:46: error: ‘struct spl_image_info’ has
On 12/12/22 10:40, Patrick DELAUNAY wrote:
Hi,
Hello Patrick
[...]
Hmmm, what does the BootROM use CRYP for then ?
used for SSP = Secure Secret Provisioning
https://wiki.st.com/stm32mpu/wiki/Secure_Secret_Provisioning_(SSP)
Oh, only this part, I see.
It is necessary to have MP15xC/F f
On Fri, Dec 9, 2022 at 8:34 AM Pengfei Fan
wrote:
>
> Use log_warning() instead of printf() to print out driver information
>
> Signed-off-by: Pengfei Fan
> Reviewed-by: Simon Glass
> ---
Applied both to u-boot-spi/master
On Tue, Nov 29, 2022 at 7:47 AM Kunihiko Hayashi
wrote:
>
> Introduce Socionext F_OSPI controller driver. This controller is used to
> communicate with slave devices such as SPI flash memories. It supports
> 4 slave devices and up to 8-bit wide bus, but supports master mode only.
>
> This driver u
Add trace in env save to indicate any errors to end user and avoid
silent output when the command 'env erase' is not executed as it is
done in env_save with commit 8968288cb477 ("env: add failing trace in
env_save")
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
env/env.c
Add support of opts erase for ubi env backend, this opts is used by
command 'env erase'.
This command only zero-fill the env UBI volume CONFIG_ENV_UBI_VOLUME
and CONFIG_ENV_UBI_VOLUME_REDUND, so the saved environment becomes
invalid.
This patch introduces a local define ENV_UBI_VOLUME_REDUND
only
Please submit the patch using git send-email.
On Thu, Nov 10, 2022 at 4:44 PM Peter Robinson wrote:
>
> Add the Gigadevice GD25LQ128E identifers so it can be properly
> used.
>
> Datasheet: https://www.gigadevice.com/datasheet/gd25lq128e/
>
> Signed-off-by: Peter Robinson
> ---
> drivers/mtd/spi/spi-nor-ids.c | 5 +
> 1 file changed, 5
On 12/14/22 16:23, Quentin Schulz wrote:
Hi Marek,
Hi,
On 12/14/22 07:45, Marek Vasut wrote:
Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
forces '$fdtcontroladdr' DT address as a third parameter of bootm command
even if the PXE transfer pulls in a fitImage which
The timer units in the stm32mp15x CPUs have interrupts, depending on the
timer flavour either one "global" or four dedicated ones. Add the irqs
to the timer units on stm32mp15x.
Sync the DT Files with linux kernel v6.1 and with commit a9b70102253ce
("ARM: dts: stm32: Add timer interrupts on stm32m
Remove unnecessary space in device tree stm32mp15xx-dkx.dtsi.
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp15xx-dkx.dtsi | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi
b/arch/arm/dts/stm32mp15xx-dkx.dtsi
index 5a045d7
The include file stm32mp1-clksrc.h is not necessary for the SCMI STM32MP15
dtsi files as the clock tree is not defined in the U-Boot SCMI device tree;
these SCMI device tree only support TFABOOT with stm32mp15_defconfig,
SPL with the basic boot defconfig is not supported.
Signed-off-by: Patrick De
Hi Marek,
On 12/14/22 07:45, Marek Vasut wrote:
Commit d5ba6188dfb ("cmd: pxe_utils: Check fdtcontroladdr in label_boot")
forces '$fdtcontroladdr' DT address as a third parameter of bootm command
even if the PXE transfer pulls in a fitImage which contains configuration
node with its own DT that
On 14/12/2022 05:39, Simon Glass wrote:
Hi Alexey,
On Tue, 13 Dec 2022 at 10:32, Alexey Romanov wrote:
This function can be used by other modules.
Signed-off-by: Alexey Romanov
---
arch/arm/include/asm/arch-meson/sm.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include
On 14/12/2022 11:33, Mattijs Korpershoek wrote:
On Tue, Dec 13, 2022 at 21:31, Alexey Romanov wrote:
It is incorrect to keep commands in the arch/ folder.
Signed-off-by: Alexey Romanov
---
MAINTAINERS | 1 +
arch/arm/mach-meson/sm.c | 144 ---
Hi,
On 14/12/2022 15:45, Mattijs Korpershoek wrote:
Hi Neil,
I'll run some tests on other G12 boards but so far this looks very good, thanks
!
I got my hands on an odroid-c4 board and I also tested:
=> fastboot usb 0
=> # hit Ctrl-c
# disconnection is ok
And tested "usb start" and coul
Hi Neil,
On Thu, Nov 24, 2022 at 10:34, Neil Armstrong wrote:
> Hi Mattijs,
>
> On 23/11/2022 16:42, Mattijs Korpershoek wrote:
>> While working on some USB bugs on the VIM3L board, we stumbled upon the fact
>> that mach-meson still uses legacy board_usb_*() functions instead of using
>> DM [1]
On Wed, 14 Dec 2022 02:37:12 -0600
Samuel Holland wrote:
Hi Samuel,
many thanks for having a look!
> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> > enables the power for a SATA harddisk.
> > In the DT this is described with the
On Wed, 14 Dec 2022 03:09:22 -0600
Samuel Holland wrote:
Hi Samuel,
> Thanks for this cleanup! With the two issues below addressed, it looks
> good to me.
many thanks for having such a thorough look!
> On 12/5/22 18:45, Andre Przywara wrote:
> > The CONFIG_MACPWR Kconfig symbol is used to poin
On 12/12/22 14:19, Marek Vasut wrote:
CAUTION: This message has originated from an External Source. Please use proper
judgment and caution when opening attachments, clicking links, or responding to
this email.
On 12/12/22 11:44, Fabrice Gasnier wrote:
This series adds a driver to support
Hello!
On Tue, Dec 13, 2022 at 08:39:43PM -0800, Simon Glass wrote:
> Hi Alexey,
>
> On Tue, 13 Dec 2022 at 10:31, Alexey Romanov wrote:
> >
> > Keeping the commands code in an arch/ is not correct. This patchset
> > moves the meson smc commands from arch/arm/mach-meson to cmd/meson
> > folder a
Hello!
On Tue, Dec 13, 2022 at 08:39:46PM -0800, Simon Glass wrote:
> Hi Alexey,
>
> On Tue, 13 Dec 2022 at 10:32, Alexey Romanov wrote:
> >
> > This function can be used by other modules.
> >
> > Signed-off-by: Alexey Romanov
> > ---
> > arch/arm/include/asm/arch-meson/sm.h | 2 ++
> > 1 file
On Wed, Dec 14, 2022 at 11:33:35AM +0100, Mattijs Korpershoek wrote:
> On Tue, Dec 13, 2022 at 21:31, Alexey Romanov
> wrote:
>
> > It is incorrect to keep commands in the arch/ folder.
> >
> > Signed-off-by: Alexey Romanov
> > ---
> > MAINTAINERS | 1 +
> > arch/arm/mach-meson/
Hi Hector and Marek,
Thanks for your reply. I am glad that there is already a thread open for this
problem. As reverting the commit seems to be the best way to resolve this
problem, we will take the same approach in our forked U-Boot mainline source
code.
I am looking forward to the solution i
On Tue, Dec 13, 2022 at 21:31, Alexey Romanov wrote:
> It is incorrect to keep commands in the arch/ folder.
>
> Signed-off-by: Alexey Romanov
> ---
> MAINTAINERS | 1 +
> arch/arm/mach-meson/sm.c | 144
> cmd/Kconfig | 7 ++
>
Switch off SCSI related config options to get rid of the board
removal warning. We don't use this interface. Also disable UBIFS
to decrease the image size, as this is also not used.
Signed-off-by: Holger Brunck
---
configs/pg_wcom_expu1_defconfig| 6 --
configs/pg_wcom_expu1_update_d
On 14/12/2022 04:39, Simon Glass wrote:
> Hi Paul,
>
> On Wed, 23 Nov 2022 at 10:50, Paul Barker wrote:
>>
>> This addition allows UEFI applications running under u-boot to access
>> peripherals on SPI busses. It is based on the UEFI Platform
>> Initialization (PI) Specification, Version 1.7 Erra
On Tue, Dec 13, 2022 at 10:39:09PM +0100, Vincent Stehl?? wrote:
> When the HII protocol function get_package_list_handle() is called with an
> invalid package list handle, it returns EFI_NOT_FOUND but this is not in
> its list of possible status codes as per the EFI specification.
> Return EFI_INV
Hi Andre,
Thanks for this cleanup! With the two issues below addressed, it looks
good to me.
On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_MACPWR Kconfig symbol is used to point to a GPIO that enables
> the power for the Ethernet "MAC" (mostly PHY, really).
> In the DT this is described wi
Hi Andre,
On 12/5/22 18:45, Andre Przywara wrote:
> The CONFIG_SATAPWR Kconfig symbol was used to point to a GPIO that
> enables the power for a SATA harddisk.
> In the DT this is described with the target-supply property in the AHCI
> DT node, pointing to a (GPIO controlled) regulator. Since we n
Add a test for the case when the HII database protocol
get_package_list_handle() function is called with an invalid package list
handle.
Signed-off-by: Vincent Stehlé
Cc: Heinrich Schuchardt
Cc: Ilias Apalodimas
---
lib/efi_selftest/efi_selftest_hii.c | 10 ++
1 file changed, 10 insert
When the HII protocol function get_package_list_handle() is called with an
invalid package list handle, it returns EFI_NOT_FOUND but this is not in
its list of possible status codes as per the EFI specification.
Return EFI_INVALID_PARAMETER instead to fix conformance.
Signed-off-by: Vincent Stehlé
Hi,
The following couple of patches fixes a small UEFI HII conformance issue and
adds a selftest demonstrating the issue.
This is sent in this order to avoid breaking `bootefi selftest' in the middle
but feel free to apply in any order if preferred.
Best regards,
Vincent.
Vincent Stehlé (2):
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