On 5/13/23 03:36, Ralph Siemsen wrote:
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
On 5/13/23 03:36, Ralph Siemsen wrote:
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
On 5/13/23 03:36, Ralph Siemsen wrote:
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB,
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
-
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v7:
- replace broken link to binman.rst
Changes in v5:
- added renesas dir to
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v6)
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
(no changes since v6)
Changes in v6:
- use wait_for_bit macros instead of endless while loop
Changes in v5:
- move board-specific init out of the driver.
Changes in v3:
- assorted small
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car
On 5/12/23 22:03, Francis Laniel wrote:
If one defines HUSH_2021_PARSER, it is then possible to use 2021 parser with:
=> cli get
old
=> cli set 2021
=> cli get
2021
We don't need such a command. Just allow only one parser.
Best regards
Heinrich
Reviewed-by: Simon Glass
Signed-off-by:
On 5/12/23 22:03, Francis Laniel wrote:
This command can be used to print the current parser with 'cli print'.
It can also be used to set the current parser with 'cli set'.
For the moment, only one value is valid for set: old.
What would be the benefit having multiple alternative parsers in
On 5/12/23 22:03, Francis Laniel wrote:
This flag is used to indicate we are using the hush parser.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
common/cli.c | 2 ++
include/asm-generic/global_data.h | 4
2 files changed, 6 insertions(+)
diff --git
On 5/12/23 22:03, Francis Laniel wrote:
For the moment, the menu contains only entry: HUSH_OLD_PARSER which is the
default.
The goal is to prepare the field to add a new hush parser which guarantees
actual behavior is still correct.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
Executing an EFI binary fails for files loaded via semihosting.
Construct a dummy device path for EFI binaries loaded via semihosting.
A future complete solution may include the creation of a handle with a
simple file system protocol.
Reported-by: Andre Przywara
Signed-off-by: Heinrich
For testing semihosting we need to pass parameter -semihosting.
Signed-off-by: Heinrich Schuchardt
---
bin/travis-ci/conf.qemu_arm64_na | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bin/travis-ci/conf.qemu_arm64_na b/bin/travis-ci/conf.qemu_arm64_na
index 14577d8..e195b5e
On 4/27/23 7:25 PM, Yanhong Wang wrote:
+struct starfive_eeprom {
+ struct eeprom_header header;
+ struct starfive_eeprom_atom1 atom1;
+ struct starfive_eeprom_atom4 atom4;
+};
+
+static uchar eeprom_buf[STARFIVE_EEPROM_HATS_SIZE_MAX];
+
+struct starfive_eeprom *pbuf = (struct
If a file does not exist, it should be created.
Fixes: f676b45151c3 ("fs: Add semihosting filesystem")
Signed-off-by: Heinrich Schuchardt
---
fs/semihostingfs.c | 4
1 file changed, 4 insertions(+)
diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c
index 96eb3349a2..3592338a68 100644
Hi Francis,
On Fri, May 12, 2023 at 1:07 PM Francis Laniel
wrote:
>
> This commit set CONFIG_HUSH_PARSER_2021 as the default to trigger the CI with
> this parser.
>
> Nonetheless, the keymile (i.e. VENDOR_KM) board family is not compatible with
> new 2021 hush parser.
> Indeed, This boards used
On 5/12/23 22:15, Ralph Siemsen wrote:
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
On 5/12/23 22:15, Ralph Siemsen wrote:
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB,
If one defines HUSH_2021_PARSER, it is then possible to use 2021 parser with:
=> cli get
old
=> cli set 2021
=> cli get
2021
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
cmd/Kconfig | 8 +
cmd/cli.c | 7 -
common/Makefile
The RZ/N1 is a family of SoC devices from Renesas [1], featuring ARM
Cortex-A7 and/or Cortex-M3 CPU, industrial ethernet protocols,
integrated Ethernet switch, and numerous peripherals.
This is a first step in upstreaming support for the RZ/N1 family.
Currently it contains just enough to boot to
Add support for Schneider Electric RZ/N1D and RZ/N1S boards, which
are based on the Reneasas RZ/N1 SoC devices.
The intention is to support both boards using a single defconfig, and to
handle the differences at runtime.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- move board-specific DDR
As a starting point, list all currently supported Renesas boards.
For the RZ/N1 board, add details about booting and flashing.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- added renesas dir to doc/board/index.rst
- corrections to list of
Renesas RZ/N1 devices contain BootROM code that loads a custom SPKG
image from QSPI, NAND or USB DFU. Support this format in mkimage tool.
SPKGs can optionally be signed, however creation of signed SPKG is not
currently supported.
Example of how to use it:
tools/mkimage -n
Clock driver for the Renesas RZ/N1 SoC family. This is based on
Linux kernel 6.2.y drivers/clk/renesas/r9a06g032-clocks.c as found in
commit 02693e11611e ("clk: renesas: r9a06g032: Repair grave increment error"),
with the following additional patch series applied:
The RZ/N1 is a family of SoC devices from Renesas, featuring:
* ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3
* Integrated SRAM up to 6MB
* Integrated gigabit ethernet switch
* Optional DDR2/3 controller
* I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD
Add basic support for this
Driver for Cadence EDAC DDR controller, as found in the Renesas RZ/N1.
Signed-off-by: Ralph Siemsen
---
Changes in v6:
- use wait_for_bit macros instead of endless while loop
Changes in v5:
- move board-specific init out of the driver.
Changes in v3:
- assorted small cleanups
- support
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Changes in v5:
-
Pinctrl/pinconf driver for Renesas RZ/N1 (R906G032) SoC.
This is quite rudimentary right now, and only supports applying a
default pin configuration as specified by the device tree.
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
(no changes since v5)
Changes in v5:
- add R-b tag
Add new CONFIG_CLK_RCAR to control compilation of shared code for R-Car
clock drivers (renesas-cpg-mssr.c). Enable this for R-Car Gen2 and 3.
This is necessary so that CONFIG_CLK_RENESAS can be enabled, allowing
recursion into the drivers/clk/reneasas directory, without bringing in
the R-Car
Commit 2564fce7eea3 ("sunxi: move Cortex SMPEN setting into start.S")
added SPL_ARMV7_SET_CORTEX_SMPEN to enable setting SMP bit. For
platforms not using SPL boot, add the corresponding non-SPL config,
so that CONFIG_IS_ENABLED(ARMV7_SET_CORTEX_SMPEN) works as expected.
Signed-off-by: Ralph
On Tue, May 09, 2023 at 11:42:30AM -0400, Ralph Siemsen wrote:
On Tue, May 09, 2023 at 04:52:45PM +0200, Marek Vasut wrote:
Do we have some sort of global (?) state structure which exists
during the whole work cycle of the tool ? If so, add a link list
into there.
There is struct
On Tue, May 09, 2023 at 09:21:02AM -0400, Ralph Siemsen wrote:
On Tue, May 09, 2023 at 04:26:57AM +0200, Marek Vasut wrote:
On 5/8/23 20:23, Ralph Siemsen wrote:
I moved it to board-specific directory as an interim step.
Hopefully we can do some consolidation of the multiple CDNS DDR
This commit adds the following hush busybox upstream commits:
3a7f00eadcf4 ("hush: add comment about abort on syntax error %{^}")
acae889dd972 ("ash,hush: tab completion of functions and aliases")
90b607d79a13 ("hush: quote variable values printed by "set" (match ash
behavior)")
6748e6494c22
Modifies return code got from while loop as hush 2021 always returns 0 from
while loop.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
test/hush/loop.c | 34 ++
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/test/hush/loop.c
Adds support for "if then else" construct both for command line interface and
through run_command().
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
common/cli_hush_2021.c | 11 +++
common/cli_hush_upstream.c | 12
2 files changed, 15 insertions(+), 8
This commit set CONFIG_HUSH_PARSER_2021 as the default to trigger the CI with
this parser.
Nonetheless, the keymile (i.e. VENDOR_KM) board family is not compatible with
new 2021 hush parser.
Indeed, This boards used set_local_var() to store some variables as local shell.
They then used
This command can be used to print the current parser with 'cli print'.
It can also be used to set the current parser with 'cli set'.
For the moment, only one value is valid for set: old.
Signed-off-by: Francis Laniel
---
cmd/Makefile | 2 +
cmd/cli.c | 120
For the moment, the menu contains only entry: HUSH_OLD_PARSER which is the
default.
The goal is to prepare the field to add a new hush parser which guarantees
actual behavior is still correct.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
cmd/Kconfig | 13 +
In Busybox hush, '<' and '>' are used as redirection operators.
For example, cat foo > bar will write content of file foo inside file bar.
In U-Boot, we do not have file system, so we can hardly redirect command output
inside a file.
But, in actual U-Boot hush, these operators ('<' and '>') are
Modifies the expected result for hush 2021.
Indeed, there were bugs in actual U-Boot hush which were fixed in upstream
Busybox.
As hush 2021 is based on upstream Busybox, these bugs no longer exist.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
test/hush/dollar.c | 79
Modifies the expected result for hush 2021.
Indeed, there were bugs in actual U-Boot hush which were fixed in upstream
Busybox.
As hush 2021 is based on upstream Busybox, these bugs no longer exist.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
test/hush/list.c | 69
This flag is used to indicate we are using the hush parser.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
common/cli.c | 2 ++
include/asm-generic/global_data.h | 4
2 files changed, 6 insertions(+)
diff --git a/common/cli.c b/common/cli.c
index
Enables the use of for, while and until loops for command line as
well as with run_command().
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
common/cli_hush_2021.c | 1 +
common/cli_hush_upstream.c | 15 ++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff
Enables using, in code, hush 2021 as parser for run_command function family.
It also enables the command run to be used by CLI user of hush 2021.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
common/cli.c | 63 --
Adds new file cli_hush_2021.c, it is a copy of Busybox hush file as it was of
time to commit 37460f5da.
This commit modifies Busybox hush to not compile some part specific to Busybox
and adds some code needed by U-Boot.
The modifications consists mainly on adding code #if(n)def guards.
For the
run_command() is called internally by the command run and it can also be called
directly from U-Boot code, e.g. to do unit tests.
This commit adds this path to go to hush 2021.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
common/cli_hush_upstream.c | 66
Enables variables expansion for hush 2021, both for local and environment
variables.
So the following commands:
foo=bar
echo $foo
setenv bar foo
echo $bar
leads to "bar" and "foo" being printed on console output.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
common/cli_hush_2021.c
The added tests verifies correct behavior of for, while and until loops.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
test/hush/Makefile | 1 +
test/hush/loop.c | 65 ++
2 files changed, 66 insertions(+)
create mode 100644
Verifies behavior of commands separated by ';', '&&' and '||'.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
test/hush/Makefile | 1 +
test/hush/list.c | 79 ++
2 files changed, 80 insertions(+)
create mode 100644 test/hush/list.c
Verifies shell variables are replaced by their values.
Reviewed-by: Simon Glass
Signed-off-by: Francis Laniel
---
test/hush/Makefile | 1 +
test/hush/dollar.c | 167 +++
test/py/tests/test_ut.py | 8 +-
3 files changed, 175 insertions(+), 1
5804ebfeb1ce ("test: hush: Test hush if/else") translated this test to a C test,
so this python file is no more needed.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
test/py/tests/test_hush_if_test.py | 197 -
1 file changed, 197 deletions(-)
delete
As asked in commit 9c6bf1715f6a ("test/py: hush_if_test: Add tests to cover
octal/hex values"), this commit translates test_hush_if_test.py to a C test.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
test/hush/Makefile | 1 +
test/hush/if.c | 316
Introduce a new subcommand to ut: ut hush.
For the moment, this command does nothing, future commits will add tests which
will be run on command call.
Note that CONFIG_HUSH_PARSER must be defined to compile this new subcommand.
Signed-off-by: Francis Laniel
Reviewed-by: Simon Glass
---
Hi.
During 2021 summer, Sean Anderson wrote a contribution to add a new shell, based
on LIL, to U-Boot [1, 2].
While one of the goals of this contribution was to address the fact actual
U-Boot shell, which is based on Busybox hush, is old there was a discussion
about adding a new shell versus
Helloworld.efi should print the file path even if the boot device is
not set.
Signed-off-by: Heinrich Schuchardt
---
lib/efi_loader/helloworld.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/lib/efi_loader/helloworld.c b/lib/efi_loader/helloworld.c
index
Hi Bhavya!
On May 11, 2023 thus sayeth Bhavya Kapoor:
> Add main_uart5 clocks in clk-data.c for J721S2. Now,
> main_uart5 clocks will be set up while booting the J721S2 SoC.
>
> Signed-off-by: Bhavya Kapoor
> ---
> arch/arm/mach-k3/j721s2/clk-data.c | 7 +--
> 1 file changed, 5
From: Chris Morgan
Add support for panel auto detection for the Anbernic RGxx3 series.
This requires us to probe the DSI and DSI-DPHY controllers so that
we may send a MIPI_DCS_GET_DISPLAY_ID command to the panel to find
out which panel we are running. This requires creating a kind of
"skeleton"
Hi Roger,
On Fri, May 12, 2023 at 02:53:07PM +0300, Roger Quadros wrote:
>
>
> On 10/05/2023 18:38, Colin Foster wrote:
> >
> > This is still out-of-U-Boot. I have an include/configs/our_product.h
> > file with this:
> >
> > """
> > #define CFG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7,
Hi Jonas,
On 5/6/23 19:41, Jonas Karlman wrote:
Loading part of TF-A into SRAM from eMMC using DMA fails on RK3399
similar to other Rockchip SoCs. Checksum validation fails with:
## Checking hash(es) for Image atf-2 ... sha256 error!
Bad hash value for 'hash' hash node in 'atf-2' image
Hi Jonas,
On 5/6/23 19:41, Jonas Karlman wrote:
The workaround to limit number of blocks to read in a single command
should only be applied to RK3568 and RK3588. Change to be more strict
when to apply the workaround.
Fixes: 2cc6cde647e2 ("mmc: rockchip_sdhci: Limit number of blocks read in a
Add support for TPS6594 PMIC devices :
- overlaying regulators definition with compatible device,
- watchdog on MCU_I2C0 bus.
Signed-off-by: Apelete Seketeli
---
arch/arm/dts/k3-j784s4-evm-u-boot.dtsi | 12
1 file changed, 12 insertions(+)
diff --git
Enable TPS6594 PMIC support (regulators and watchdog) for j784s4 SoC.
PMIC is controlled by SoC through I2C interface.
Signed-off-by: Apelete Seketeli
---
configs/j784s4_evm_a72_defconfig | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git
Add support for TPS6594 PMIC devices :
- regulators (bucks and LDOs) on WKUP_I2C0 bus,
- watchdog on MCU_I2C0 bus.
Signed-off-by: Apelete Seketeli
---
arch/arm/dts/k3-j784s4-r5-evm.dts | 134 ++
1 file changed, 134 insertions(+)
diff --git
From: Esteban Blanc
Signed-off-by: Esteban Blanc
Signed-off-by: Apelete Seketeli
---
board/ti/j721s2/evm.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index ec7abea387..818edea686 100644
--- a/board/ti/j721s2/evm.c
+++
From: Esteban Blanc
Signed-off-by: Esteban Blanc
Signed-off-by: Apelete Seketeli
---
board/ti/j721s2/evm.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 8eaca9d5af..ec7abea387 100644
--- a/board/ti/j721s2/evm.c
From: Esteban Blanc
Add support for TPS6594 family regulators and watchdog.
Add support for AVS0.
PMIC is controlled by SoC through I2C interface.
Add dm, pmic and regulators commands to allow testing.
Signed-off-by: Esteban Blanc
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
From: Jerome Neanne
Add support for TPS6594 PMIC family devices:
- regulators (bucks and LDOs) on main WKUP_I2C0 bus,
- watchdog on MCU_I2C0 bus.
Signed-off-by: Esteban Blanc
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
.../k3-j721s2-common-proc-board-u-boot.dtsi | 37
From: Jerome Neanne
Add support for TPS6594 PMIC family devices:
- regulators (bucks and LDOs) on WKUP_I2C0 bus,
- watchdog on MCU_I2C0 bus.
Signed-off-by: Esteban Blanc
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
.../k3-j7200-common-proc-board-u-boot.dtsi| 27
From: Esteban Blanc
Add support for TPS6594 family regulators and watchdog.
PMIC is controlled by SoC through I2C interface.
Add dm, pmic and regulators commands to allow testing
Signed-off-by: Esteban Blanc
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
From: Jerome Neanne
Add support for TPS6593 PMIC devices:
- regulators (bucks and LDOs) on main I2C0 bus,
- watchdog on MCU I2C0 bus.
Signed-off-by: Julien Panis
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
arch/arm/dts/k3-am62a7-sk-u-boot.dtsi | 24
From: Julien Panis
Add support for TPS6593 regulators and watchdog.
PMIC is controlled by SoC through I2C interface.
Signed-off-by: Julien Panis
Signed-off-by: Apelete Seketeli
---
configs/am62ax_evm_a53_defconfig | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git
From: Jerome Neanne
Change node name to reuse Linux common dts naming style.
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Jerome Neanne
Use a copy of Linux dts for TPS6594 PMIC description
instead of custom u-boot
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
.../arm/dts/k3-j721e-r5-common-proc-board.dts | 48 +--
1 file changed, 22 insertions(+), 26 deletions(-)
diff
From: Jerome Neanne
Add PMIC and regulators feature support for j721e.
PMIC is controlled by SoC through I2C interface.
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
configs/j721e_evm_a72_defconfig | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Jerome Neanne
j721e board includes 2 instances of TPS6594:
- Primary PMIC
- Secondary PMIC
Add AVS class0 in u-boot SPL.
AVS is supported only on CPU rail: vdd_cpu_avs.
This rail is supplied by the primary PMIC: tps659413
This rail is supplied by a dual-phased buck: buck12.
Other PMICs
From: Jerome Neanne
Using uclass_probe_all forces probe on all devices:
Only probe for WD stop is really needed here.
Probing other devices has no impact.
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
board/ti/j721e/evm.c | 8
1 file changed, 8 insertions(+)
diff
From: Jerome Neanne
Fixes: 065a452ae6a power: regulator: tps65941: add regulator support
LDO voltage conversion was incorrect.
This was checked by writing and reading back value.
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
drivers/power/regulator/tps65941_regulator.c |
From: Jerome Neanne
This is not a proper WD driver because it's not planned to
support WD driver for PMIC in u-boot at any time.
The purpose is just WD disable.
Signed-off-by: Jerome Neanne
Signed-off-by: Apelete Seketeli
---
drivers/power/pmic/tps65941.c | 61
TPS6594 is a Power Management IC which provides regulators and others
features like GPIOs, RTC, watchdog, ESMs (Error Signal Monitor), and
PFSM (Pre-configurable Finite State Machine). The SoC and the PMIC can
communicate through the I2C or SPI interfaces.
TPS6594 is the super-set device while
On Fri, May 12, 2023 at 03:40:37PM +0800, Peng Fan wrote:
> Hi Tom,
>
> On 5/6/2023 1:14 AM, Tom Rini wrote:
> > On Fri, May 05, 2023 at 03:19:27AM +, Peng Fan wrote:
> >
> > > Hi Tom,
> > >
> > > Please pull fsl-qoirq-2023-5-5
> > >
> >
> > I've applied this to u-boot/master now, thanks.
On Thu, 11 May 2023 17:23:13 +0200
Heinrich Schuchardt wrote:
Hi Heinrich, Ilias,
> On 5/11/23 10:59, Andre Przywara wrote:
> > On Thu, 11 May 2023 08:22:30 +0200
> > Heinrich Schuchardt wrote:
> >
> >> On 5/11/23 02:00, Andre Przywara wrote:
> >>> On Wed, 10 May 2023 23:19:33 +0200
> >>>
Hi,
On 5/5/23 02:11, Tom Rini wrote:
The ITS file used to build the images here lists three dtb files as
being used. Today, these are built by the logic that will over-build dtb
files based on SOC/etc symbols being set. To future proof this platform
and be generally correct, we list all 3 of
Hi,
On 5/6/23 04:03, Simon Glass wrote:
This should be declared in a header file so that type-checking works
correctly.
Add a single declaration to usb.h and remove the others.
Signed-off-by: Simon Glass
---
cmd/usb.c | 1 -
common/usb.c | 2 +-
On 5/12/23 15:43, Patrick DELAUNAY wrote:
Hi,
Hi,
+ /* Ping IWDG2 and ACK pretimer IRQ */
+ if (iwdg2_wake) {
+ writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR);
+ writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR);
+ }
+ }
Hi,
On 5/4/23 21:52, Marek Vasut wrote:
The get_stm32mp_rom_api_table() function is defined in sys_params.h ,
add the missing header to avoid compiler warning.
Fixes: dbeaca79b79 ("ARM: stm32: Factor out save_boot_params")
Signed-off-by: Marek Vasut
---
Cc: Patrice Chotard
Cc: Patrick
Hi,
On 5/4/23 21:52, Marek Vasut wrote:
The correct specifier of the section is ".data" and not "data",
use the former to place the variables in ".data" section.
Fixes: 731fd50e27f ("ARM: stm32: Implement board coding on AV96")
Fixes: 92ca0f7446c ("ARM: dts: stm32: Synchronize DDR setttings on
Hi,
On 5/11/23 21:55, Marek Vasut wrote:
In case the IWDG is enabled by either U-Boot or Linux, the IWDG can never
be disabled again. That includes low power states, which means that if the
IWDG is enabled, the SoC would reset itself after a while in suspend via
the IWDG. This is not desired
Hi,
On 5/11/23 13:54, Marek Vasut wrote:
On 5/11/23 08:39, Patrice CHOTARD wrote:
Hi,
On 5/11/23 02:22, Marek Vasut wrote:
In case the IWDG is enabled by either U-Boot or Linux, the IWDG can
never
be disabled again. That includes low power states, which means that
if the
IWDG is enabled,
Hi Simon,
>
> On Wed, 12 Apr 2023 at 03:43, Abdellatif El Khlifi
> wrote:
> >
> > Provide armffa command showcasing the use of the U-Boot FF-A support
> >
> > armffa is a command showcasing how to invoke FF-A operations.
> > This provides a guidance to the client developers on how to
> > call
Add device data for main_uart1 in dev-data.c for J7200. Now,
main_uart1 will be powered on while booting the J7200 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j7200/dev-data.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/j7200/dev-data.c
Add main_uart1 clocks in clk-data.c for J7200. Now,
main_uart1 clocks will be set up while booting the J7200 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j7200/clk-data.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j7200/clk-data.c
Add device data and clock data for main_uart1 for J7200 SoC so that
main_uart1 will be powered on and its clock will be set up while
booting the J7200 SoC.
Bhavya Kapoor (2):
arm: mach-k3: j7200: dev-data.c: Add main_uart1 device data
arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock data
Hi,
I hope this is the right mailing list to ask beginners questions. I've
asked this question also a the Xilinxs forum (Petalinux based board),
without much help.. but it must be something simple, but I don't know
much about u-boot yet.
Previously using Petalinux 2019.1 (not sure which
On 3/28/23 8:42 PM, Yanhong Wang wrote:
+void harts_early_init(void)
+{
+ ulong *ptr;
+ u8 *tmp;
+ ulong len, remain;
+ /*
+* Feature Disable CSR
+*
+* Clear feature disable CSR to '0' to turn on all features for
+* each core. This
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