Hi Tom,
On 11:30-20230516, Tom Rini wrote:
> On Tue, May 16, 2023 at 12:11:24PM +0530, Manorit Chawdhry wrote:
>
> > Hi All,
> >
> > I recently came upon a discussion that had happened a while back [0].
> > I want to continue the discussion as I believe the issue still persists
> > and the
On 2023/5/11 00:59, Dmitrii Merkurev wrote:
Add TCP/IP6 related headers and reuse refactored TCP/IP
implementation
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
---
include/net/tcp6.h | 106
Hi Tim,
On Fri, May 19, 2023 at 8:00 PM Tim Harvey wrote:
> Fabio,
>
> There's more to be done here also. With this patch, and with the
> spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> you get:
> starting USB...
> Bus usb@3820:
> Enable clock-controller@3038
On 5/24/2023 3:21 AM, Gilles Talis wrote:
Add support for the Polyhex Debix Model A SBC board.
It is an industrial grade single board computer based on
NXP's i.MX 8M Plus.
Currently supported interfaces are:
- Serial console
- Micro SD
- eQOS and FEC Ethernet
imx8mp-debix-model-a.dts is
On 2023/5/11 00:59, Dmitrii Merkurev wrote:
Changes:
1. Separate reusable part from net_set_tcp_header to
net_set_tcp_header_common
2. Make TCP signatures reusable by receiving particular
IP agnostic TCP headers
3. Extract net_send_ip_packet6 from net_send_udp_packet6
to reuse the code
4.
Reviewed-by: Ying-Chun Liu (PaulLiu)
On 2023/5/11 00:59, Dmitrii Merkurev wrote:
This allows us to reuse TCP logic between IP and IP6 stack.
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
---
include/net/tcp.h | 54
Hi Maxim, Tom,
On 24.05.2023 16:05, Maxim Uvarov wrote:
On Tue, 23 May 2023 at 03:23, Tom Rini wrote:
On Mon, May 22, 2023 at 12:40:49PM -0400, Maxim Uvarov wrote:
On Mon, 22 May 2023 at 10:20, Tom Rini wrote:
On Mon, May 22, 2023 at 04:33:57PM +0300, Ilias Apalodimas wrote:
Hi Maxim
On Tue, 23 May 2023 at 03:23, Tom Rini wrote:
> On Mon, May 22, 2023 at 12:40:49PM -0400, Maxim Uvarov wrote:
> > On Mon, 22 May 2023 at 10:20, Tom Rini wrote:
> >
> > > On Mon, May 22, 2023 at 04:33:57PM +0300, Ilias Apalodimas wrote:
> > > > Hi Maxim
> > > >
> > > > On Mon, 22 May 2023 at
On 2023/5/23 19:28, Conor Dooley wrote:
> On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote:
>> On Tue, 23 May 2023 09:28:39 +0100
>> Conor Dooley wrote:
>>
>> > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu wrote:
>> > > On 2023/5/19 22:16, Conor Dooley wrote:
>> > > > On Fri,
Hi Sam,
Thanks for testing!
> By any chance do you happen to know when in sunxi history the SPI
> controller grew QuadSPI/DualSPI support?
Unfortunately I don't know the history of Allwinner's SoCs that well :)
> I might be interested in taking a stab at supporting them.
Oh, that will be
On Wed, May 24, 2023 at 05:00:02PM +0800, Xingyu Wu wrote:
> On 2023/5/23 19:28, Conor Dooley wrote:
> > On Tue, May 23, 2023 at 01:10:06PM +0200, Torsten Duwe wrote:
> >> On Tue, 23 May 2023 09:28:39 +0100
> >> Conor Dooley wrote:
> >>
> >> > On Tue, May 23, 2023 at 10:56:43AM +0800, Xingyu Wu
On Wed, 24 May 2023 at 10:33, Masahisa Kojima
wrote:
>
> Current code expects that SPI_TX_BYTE is single bit mode
> but it is wrong. It indicates byte program mode,
> not single bit mode.
>
> If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
> the default transfer bus width is single
Current code expects that SPI_TX_BYTE is single bit mode
but it is wrong. It indicates byte program mode,
not single bit mode.
If SPI_TX_DUAL, SPI_TX_QUAD and SPI_TX_OCTAL bits are not set,
the default transfer bus width is single bit.
Signed-off-by: Masahisa Kojima
---
Hi Pali,
On 5/23/23 19:17, Pali Rohár wrote:
Hello! I have looked at this change and below are my comments.
Many thanks.
On Tuesday 23 May 2023 14:57:38 Stefan Roese wrote:
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver
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