e earliest.
Thanks & Regards
Ajeesh Kumar
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Hi Wolfgang,
We have a custom board with MPC8548E processor, please help me in
suggesting/sharing
Ethernet Internal/External Loopback testing code piece. Also any Phy level
loop back too.
Please do help me in this regard.
Thanks,
Ajeesh Kumar
The information contained in this electronic
phy_cmd[]){ /* shutdown */
{miim_end,}
},
};
Thanks,
Ajeesh Kumar
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this message are intended for the exclusive use of the addressee(s) and may
contain proprietary, confidentia
Hi All,
Reset problem got fixed, actually the reset command isn't doing a full board
reset and just the core was regging resetted.
Now its solved. Thanks a lot.
Thanks,
Ajeesh Kumar
-Original Message-
From: Jayakrishnan M [mailto:jay.krishn...@gmail.com]
Sent: Tuesday, Janua
Hello,
I too got this info, but due to stipulated time, I cant shift to newer
version now.
I assumed that as development used the same u-boot thought of going with the
same.
Please help me.
Thanks,
Ajeesh Kumar
-Original Message-
From: Wolfgang Denk [mailto:w...@denx.de]
Sent
of now, I have
issues only in the reset.
Please help me in this regard
Thanks,
Ajeesh Kumar
-Original Message-
From: Roman Mashak [mailto:romez...@gmail.com]
Sent: Tuesday, January 27, 2009 6:46 PM
To: aje...@tataelxsi.co.in
Cc: Wolfgang Denk; u-boot@lists.denx.de; u-b...@avr32linux.org
* Figure out memory size in Megabytes.
*/
memsize = 512;
/*
* Establish Local Access Window and TLB mappings for DDR memory.
*/
memsize = setup_laws_and_tlbs(memsize);
if (memsize == 0) {
return 0;
}
return memsize * 1024 * 1024;
}
/**
Hi All,
I'm using a u-boot.1.2.0 code base, do we have a "scanf()" type of function
call where i can use.
Please help me in this regard.
Thanks,
Ajeesh Kumar
The information contained in this electronic message and any attachments to
this message are intended for the exclu
monitor code from the Flast to the ram. If this fails then it might be some
problem in accessing ram. This happens when the LAW is not properly
initialized and the memory is not mapped properly. Make sure you map ur DDR.
Thanks,
Ajeesh Kumar
-Original Message-
From: u-boot-boun...@lists.den
1.2 is several years old, so I
wouldn't know where to >start, there.
What do you mean by "the POR strappings for the 8548 are not set up to
enable MDIO." I dint understand...
Also, I've a similar hard ware as EP8548A board, with marvel 88E1145 E1
version..
Please let
interface will be fine.
Actually, We are configuring the PHY chip have an address 0,1,2 and 3 but I
dunno why I could read only the address 0x12??
Could you help me in giving the MUST required hardware configuration that
should be done so as to make the PHY chip come up.
Thanks,
Ajeesh Kumar
-Orig
cted in Configuration, and also in Four
Independented Serial Management Mode.
Please help me in this regard.
Thanks,
Ajeesh Kumar
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this message are intended for the exclusive use of the addressee(s) and may
contain
Hi Andy,
Thank you for your Info, so if my compiled output is <200k, my .bin file
will easily fit into the boundary?
Regards,
AJEESH KUMAR
-Original Message-
From: Andy Fleming [mailto:[EMAIL PROTECTED]
Sent: Tuesday, September 09, 2008 3:16 AM
To: [EMAIL PROTECTED]
Cc: u-b
ICH LOCATION I SHOULD FLASH THE
UBOOT.BIN(SIZE IS NOT EQUAL TO 512)
FOR Eg. If my uboot.bin size is >512K ?
Please help me out in this.
Regards,
AJEESH KUMAR
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this message are intended for the exclusive use of
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